JPS582943A - Memory extending substitution system - Google Patents

Abstract

PURPOSE:To substitute a storage part for a faulty ROM without stopping devices, by reading instructions from the second storage part when register address information, where a specific address of a program storage ROM is registered, coincides with read address information. CONSTITUTION:Controlling micro mu programs are stored in the first storage ROM1, and substitutional instructions for mu instructions stored in optional addresses of the ROM1 are stored in an address area other than that of the ROM1 on the second storage WCS3. Address information from an address controlling circuit 2 is supplied to the ROM1, the WCS2, and an address comparing circuit 4. Information of a specific address of the ROM1 is registered in the circuit 4, and this registered address information is compared with address information from the circuit 2; and when they coincide with each other, a coincidence signal 8 is supplied form the circuit 4 to a mu instruction register 6, an instruction discrimination controlling circuit 7, and the circuit 2. Simultaneously, the address of the substitutional instruction in the WCS3 is outputted to the circuit 2 from a substitutional address information register part 5, and the substitutional instruction of the WCS3 is outputted to the circuit 7 through the register 6.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention is a memory expansion device used, for example, to replace any storage location in a storage circuit or to patch a program stored in a storage path. Concerning alternative methods. Note that in this specification, a program refers to a microprogram stored in a control storage device and a machine language program stored in a main storage device.

A microprocessor (M1croPrO(
iessOrLJnit (hereinafter referred to as MPU) is increasingly being used. A system program (machine language program) executed by the MPU and a control program used to execute machine language instructions are often stored in a read-only memory (hereinafter referred to as ROM). Now, once the program is stored in the ROM like this, it will be stored in the ROM once.
If a failure occurs in M, the program cannot be read from the ROM, so the MPU cannot operate normally. Conventionally, as a treatment for this, when a ROM abnormality occurs,
The ROM was being reread, but the ROM
In case of permanent failure, there was no other option than to replace the ROM.

In addition, even if a bug (BUa) is found in a program stored in ROM, if a bug (BUa) is found in a program stored in ROM,
It was necessary to replace it with OM.

Now, when replacing the ROM, the operation of the device in which the ROM is mounted must be stopped. for example,
If this device is a peripheral terminal built into the system, stopping the operation of this device (power source 1Ii) would force the complete system to be stopped. Furthermore, the capacity of ROMs is currently increasing, and the number of programs stored in ROM elements is also increasing. For this reason, it is extremely wasteful to replace the entire program and the entire element due to a malfunction in a part of the ROM element or an insect in a part of the program. Furthermore, as the capacity of ROM elements increases, the probability of element failure increases, and as the amount of programs increases, the frequency of insect occurrence also increases.

Therefore, cutting off or stopping the power to the equipment each time a failed ROM is replaced or a batch is performed against insects will lead to deterioration of system efficiency.

In order to solve this problem, the present invention has been developed to easily replace a failed ROM or to perform a batch against insects without shutting off or stopping the power supply of the device. The purpose is to provide an alternative method for memory expansion that can perform

Hereinafter, the alternative memory expansion method of the present invention will be described in detail through embodiments of the present invention.

FIG. 1 shows an alternative memory expansion method of the present invention.
FIG. 2 is a block diagram of an embodiment implemented in a gram-controlled chin rest. Note that this block diagram does not show circuits that are not directly related to the present invention, even if they are naturally necessary for the microprogram control device (for example, a timing control circuit, etc.).

1! This is the first storage unit that stores the control microprogram, and is a read-only memory (ReadOnly M
emory) is used. 2 is an address Ill Ill that outputs address information (micro address) for reading micro instructions from ROM 1 to ROM 1 etc.
It is a circuit. Address control I@J path 2 comprises a microprogram sequencer 21 and a microaddress register 22. In this embodiment, the microinstruction read address information output from the address control circuit 2 is sent to an address comparison circuit 4, WO2 (Writable Co., Ltd.), which will be described later.
ntrol 8trage) 3 is also supplied.

3 is a second storage section allocated to an address area different from ROM1, and WO2 is used. WO83
An alternative instruction that replaces the microinstruction stored at an arbitrary location of ROMI is stored in . 4 is an address comparison circuit.

Reference numeral 5 denotes an alternative address information register section serving as means for holding alternative address information (described later). The alternative address information register section 5 is a register section in which address information (hereinafter referred to as alternative address information) in the WO2 in which the alternative instruction is stored is stored.

6 is a microinstruction register. 7 is an instruction determination control circuit. 8 is an alternative command signal line. This alternative instruction signal @[1B is connected to the microinstruction register 6, instruction judgment control circuit 7, and microprogram sequencer 21.

9 is an alternative address bus. 10 is a micro address bus.

FIG. 2 is an internal circuit diagram showing a specific embodiment of the address comparison circuit 4 and the alternative address information register section 5.
41a, 41b, 41c are specific memory locations 1 of ROM1
This is a register (I-registered address register) in which address information (hereinafter referred to as registered address information 1) is stored. 42a, 42
b, 42C is the registered address information and address control circuit 2;
This is a comparator that compares the address information output from the address information. In this embodiment, these comparators 42a, 42b, 42
c outputs a logic "1" match signal when the address matches. 43 is an OR gate. The output of this OR gate 43 is the alternative instruction signal. 51a, 51b,
51c is a register (alternative address information register) in which alternative address information is stored.

The operation of the microprogram control equipment according to the embodiment to which the alternative memory expansion method of the present invention is applied will be described below with reference to FIG. FIG. 3 is a conceptual diagram of the operation of this embodiment.

Suppose now that the SUB instruction stored at address 137 in the ROMI is incorrect and must be changed to an ADD instruction. This changed instruction (ADD instruction in this example) is called a substitute instruction. At this time, the maintenance panel or O
The address information of the ROM 1 in which the sUB instruction is stored (in this example, address 137) is registered in the registration address register 41a by an S (Operation System) or the like. This address information is registered address information. Further, the alternative address information of WO83 (address 500 in this example) is registered in the alternative address information register 51a corresponding to the registered address register 41a by the maintenance panel, O8, or the like.

Assume that address information (address 137) for reading instructions stored in the ROMI is output from the microprogram sequencer 21 when the microprogram is executed. This address information is stored in the micro address register 22. When the address information is stored in the micro address register 22, this address information is transferred to the micro address bus 10.
The signal is supplied to the ROM 1, WO 83, and address comparison circuit 4 via the ROM 1, the WO 83, and the address comparison circuit 4. As a result, 5LJ from address 137 of ROM1
The B instruction is read and stored in the microinstruction register 6.

However, since the corresponding address does not exist from WO2, reading does not occur. On the other hand, the address information supplied to the address comparison circuit 4 is sent to comparators 42a, 42a, 42b,
42c. And this comparator 42a,
In each of 42b and 42c, the registered address information stored in the registered address registers 41a, 41b, and 41c is compared with the supplied address information.

Since the address information of address 137 is now registered in the registered address register 41a, a match signal of logic "1" is output from the comparator 41a. As a result, an alternative instruction signal is output from the OR gate 43. This alternative instruction signal is supplied to the micro-program sequencer 21, the micro-instruction register 6, and the instruction determination control circuit 7 via the signal chain 8.

As a result, the microphone 0 program sequencer 21 is prohibited from outputting the instruction read address at the next address (in this example, address 138). It is also set to select a microinstruction read from the microinstruction register 6awcsa. In the instruction judgment control circuit 7, the ROM1 read out via the microinstruction register 6 first
NOP the microinstruction (SUS instruction in this example) from
(No Operation) Invalidate as a command. On the other hand, the coincidence signal is the alternative address information register 51a.
As a result, the alternative address information register 51
Alternative address information (address 500) is output from a to the microaddress register 22 via the alternative address bus 10. Furthermore, this alternative address information (address 500) is supplied from the microaddress register 22 to the WO 83 via the microaddress bus 10. As a result, 5 of WO33
An alternative instruction (ADD instruction) is read from address 00 and stored in the microinstruction register 6. This alternative instruction (ADD instruction) is then executed by the instruction determination control circuit 7. Through the above operations, the SUB instruction stored at address 137 in ROM1 is replaced by the ADD instruction stored at address 500 in WO83.

According to the above method, if the ROMI location 1374 fails (for example, a parity error occurs), the memory stored at address 137 (in this example, the SUB instruction) will also be destroyed.
Even if it becomes impossible to read the ROM1, failure of ROM1 can be avoided by registering the information at address 137 in the registered address register (for example, 41a) and storing the SUB instruction at any address in WO83 (for example, address 500). be done. Further, the above-mentioned command may be information such as a numerical value or data.

Next, a second embodiment of the present invention will be described. Figure 4 is the second
It is a 10-step diagram of an example. Components that are the same as those in the block diagram of the first embodiment shown in FIG. 1 are given the same numbers and their explanations will be omitted. 52 is a branch instruction section. 11 is a branch instruction signal line. This signal line 11 is connected to a microprogram sequencer 21. The alternative address bus 9 is also connected to a microphone program sequencer 21 .

The feature of the second embodiment is that the alternative address information registration section 5 (branch instruction section 52) is provided.

Below is the 68th! The operation of the second embodiment will be explained with reference to FIG. However, the description of the first embodiment will be omitted. FIG. 6 is a conceptual diagram of the operation of the second embodiment.

First, the branch instruction section 52 will be explained. This branch instruction 5
lI52 is the alternative address information register 51a, 51
It may be any bit of bits b and 51c, or a separate instruction register or instruction switch may be provided. In this example, the fifth
As shown in the figure, alternative address information registers 51a, 5jt),
The top pit of S1c is the branch instruction part 52a, 52b
, 52c. A branch instruction is, for example, as shown in FIG.
After the SFT instruction) is replaced with the alternative instruction (ADD instruction) stored at address 524 of WO83, 525 of WO83
This means that the programs stored after the address (hereinafter referred to as alternative programs) will continue to be executed sequentially. In this embodiment, it is assumed that when the branch instruction section 52 is set to 1'', the branch is instructed.

Now, assume that address information for address 490 is output from the microprogram sequencer 21 when the microprogram is executed. Thereafter, the instructions stored in address 490 of ROM1 and WO8 are processed according to the procedure detailed in the first embodiment.
The replacement instruction is replaced with the replacement instruction stored at address 524 of No. 3. However, in the second embodiment, the following operations are performed in the above processing procedure. Alternative address information (52
When address 4) is read out, the branch instruction section @"1" is simultaneously read out from the branch instruction section 52c and output to the signal line 11. Then, when this branch instruction signal "1" is supplied to the microprogram sequencer 21, the microprogram sequencer 21 inputs the alternative address information (address 524) input via the alternative address bus 9 to the internal counter. (or register).

As a result, the alternative program stored after address 525 of CS 3 where the alternative instruction (ADD instruction) was executed is read out and executed.

According to this second embodiment, a trace program or the like can be easily inserted into a batch of programs in the ROMI or into 70 grams in the ROM1.

The first point explained above. In the second example, WO2 is R
It may be either OM%RAM.

In addition, registration address registers 41a, 41b, 41
c can be changed to a RAM or switch setting method instead of a register. Similarly, alternative address information register 51
A, 51b, and 51c can also be changed to RAM or switch setting methods. Furthermore, the configuration of the address comparison circuit 4 is not limited to the above embodiment, and any circuit configuration may be adopted. Furthermore, WO83, address comparison circuit 4
, - The alternative address information register section 5 may be provided in a portable external casing and designed so that it can be connected to the microprogram control i-device only when necessary.

As described above, according to the memory expansion alternative method of the present invention, (1) the second
Alternative allocations can be made in the memory of

(2) When a change occurs in a program, it can be modified without destroying the hardware, which is convenient, for example, when developing a program.

(3) Changes can be made without powering off the device when changing the bending position.

(4) When a problem occurs, you can easily insert a program to trace program operations.

(5) It is possible to restore the program in the first storage unit without changing it at all.

It has the following effects.

In addition, in the embodiment, explanation will be given by taking a microprogram control device as an example. Other memories such as decorations Vi
It can also be used for Il.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of the first embodiment of the present invention, FIG. 2 is an internal circuit diagram of the address control circuit and alternative address information register section of FIG. 1, and FIG. 3 is the operation of the first embodiment. 4 is a block diagram of the second embodiment of the present invention, FIG. 5 is an internal circuit diagram of the address comparison circuit and substitute address information register section of FIG. 4, and FIG. 6 is a block diagram of the second embodiment of the present invention. FIG. 3 is a conceptual diagram of the operation of the embodiment. 1... First memory section (ROM) 2... Address control circuit 3... Second memory section (WO2) 4... Address comparison circuit 5... Alternative address information register section 52... Branch instruction unit 7... Command judgment control circuit <7317) Agent patent attorney Kensuke aide (1 idiot) No.
1 Figure 2

Claims (2)

[Claims] (1) A first V storage section in which a program is stored, an address control circuit that outputs address information, and an address area that is allocated to a separate address area from the first storage section and stored at an arbitrary address in the storage section of the W41. Address information of the first storage unit and a second storage unit in which an alternative instruction to replace the stored instruction is stored, and this registered address information and read address information from the address control circuit are stored. When a match is found between the address comparing means to be compared, the alternative address information holding means in which the alternative address information of the second storage section in which the alternative instruction is stored, and the address comparing means, the alternative address information is stored. The alternative address information read from the address information holding means is supplied to the second storage section, and the instruction previously read from the first storage section is invalidated according to the signal from the address comparison means. An alternative method for expanding memory, comprising means for: (2) The alternative address information holding means includes an alternative address information registration section and a branch instruction section, and when branch instruction information is output from the branch instruction section, registers the alternative address information in the address and control direction path. Claim 1, characterized in that alternative address information of the unit is set, and a plurality of instructions are sequentially read from a plurality of consecutive addresses of the second storage unit based on the alternative address information of ε. Alternative methods of memory expansion described.