JP4853620B2 - Multiprocessor system and initial startup method and program - Google Patents

Description

  The present invention relates to a multiprocessor system that implements processors (CPUs: central processing units) of different architectures by emulation, and more particularly to a multiprocessor system that enables repair processing corresponding to the occurrence of a failure when the multiprocessor system is started up.

  Conventionally, in a multiprocessor system having a plurality of processors, when there is a failed processor when the system is started up, the failed processor is separated and started up.

  As a technique for preventing performance degradation caused by disconnecting a failed processor as described above, Patent Document 1 (Japanese Patent Laid-Open No. 2000-76216) is provided with a plurality of spare processors in advance, and the spare processor is provided when a failure occurs. A technique of switching to is disclosed.

  Patent Document 2 (Japanese Patent Application Laid-Open No. 2000-181890) discloses a technique for selecting an optimum slave processor for executing a function of a main processor from a plurality of slave processors when a failure occurs in the main processor. Is disclosed.

Further, in Patent Document 3 (Japanese Patent Application Laid-Open No. 2001-14290), when any one of the processors fails, the system control processor is determined from the non-failed processors. It is disclosed to provide means for restarting the system by the system processor.
JP 2000-76216 A JP 2000-181890 A JP 2001-14290 A

  In any of the multiprocessor systems disclosed in Patent Document 1 to Patent Document 3 described above, if there is a failed processor when the system is started up, the failed processor is separated and started up. In the technique disclosed in Patent Document 1, a plurality of spare processors are provided in advance, and when a failure occurs, the spare processor is switched to.

  In the technique disclosed in Patent Document 2, the optimum slave processor for executing the function of the master processor is selected from the plurality of slave processors.

  In the technique disclosed in Patent Document 3, when any of the processors fails in each of the processors, the system control processor is determined from the non-failed processors and used.

  In any of the techniques described in the above-mentioned patent documents, a spare processor whose function is limited in advance is used as a main processor. In a multiprocessor system, each processor has a unique function. Therefore, there is a problem in that the system becomes redundant when a spare is provided for each type of processor.

  Of the functions of the processors constituting the multiprocessor system, a processor having a function of controlling input / output is indispensable for controlling the system. If a processor having such an essential function does not function, the processor is restarted. This is particularly important because the system operation cannot be continued.

  The present invention has been made in view of the problems of the prior art as described above, and aims to realize a multiprocessor system in which a reliable restart is performed and the system does not become redundant. To do.

  An object of the present invention is to provide a multiprocessor system that can solve the above-described problems and can always continue operation at the time of the next system startup even if a processor that shares functions essential to the system fails. is there.

The multiprocessor system of the present invention is a multiprocessor system that includes a plurality of processors and realizes a system having an architecture in which each processor has different functions by emulation,
A configuration register for holding a result of an initial diagnostic test performed by each of the plurality of processors at the time of system startup;
Among the plurality of processors, the processor having the lowest physical processor number among the processors having the normal initial diagnostic test result held in the configuration register is the bootstrap processor,
The bootstrap processor includes, for a logical processor number realized by emulation, an attribute indicating whether it is an input / output control processor, a physical ID indicating a physical processor number, and valid / invalid information of the logical processor. Assigns its own physical processor number to the logical processor with the lowest physical processor number among the logical processors defined for I / O control in the logical processor information table. The logical processor to which the physical ID is assigned is invalidated.

An initial start-up method of a multiprocessor system according to the present invention is an initial start-up method performed in a multiprocessor system that includes a plurality of processors, and each processor realizes a system having an architecture having different functions by emulation.
A plurality of processors each performing an initial diagnostic test at the time of system startup;
Among the processors having normal results of the initial diagnostic test, the processor having the youngest physical processor number as a bootstrap processor;
The bootstrap processor includes, for a logical processor number realized by emulation, an attribute indicating whether it is an input / output control processor, a physical ID indicating a physical processor number, and valid / invalid information of the logical processor. Assigns its own physical processor number to the logical processor with the lowest physical processor number among the logical processors defined for I / O control in the logical processor information table. And a step of invalidating the logical processor to which the physical ID is assigned.

  The program of the present invention causes a computer system to execute the above method.

  In the present invention configured as described above, the processor that is normal as a result of the initial diagnostic test is first set as the bootstrap processor. Thereafter, the bootstrap processor assigns its own physical processor number to the processor defined to be for input / output control, and thereafter, the startup process is surely performed by the processor for input / output control.

  The effect of the present invention is that when a computer with a different architecture is realized by emulation on a multiprocessor, it is possible to always configure a processor that performs input / output control of a system core device such as a system disk, and the system continues to operate. There is an effect that it can be done.

  The reason is that the processor can always be configured by assigning a bare multiprocessor BSP (bootstrap processor) to the input / output control processor.

  Next, embodiments of the present invention will be described in detail with reference to the drawings.

  FIG. 1 is a block diagram showing a configuration of a multiprocessor system as an embodiment of the present invention.

  The system shown in FIG. 1 includes CPUs (processors) 1 to 4, a chip set 5, a memory 6, an ID bus 7, and a CPU bus 8.

  The chip set 5 is connected to the CPUs 1 to 4, the memory 6, the ID bus 7, and the CPU bus 8.

  The CPUs 1 to 4 are assigned with physical identification numbers as hardware constituting the system, and are connected to the chip set 5 via the CPU bus 8 and connected to the memory 6 via the chip set 5. And peripheral devices (not shown) can be accessed via the IO bus 7.

  A unique identification number 9 (physical ID # 0 to ID # 3) in the system is distributed by the chipset 5 to each of the CPUs 1 to 4.

  The configuration register 51 that constitutes the chipset 5 is a register that stores a CPU in which an abnormality is detected as a result of an initial diagnostic test or the like performed at the time of system startup, and stores validity / invalidity thereof.

  The CPUs 1 to 4 and the chip set 5 execute programs stored in the memory 6. As the memory 6, an external storage medium such as a floppy disk or a CD-ROM or a ROM (read only memory) can be used, and the present invention includes a program stored in the memory 6.

  The present invention is a computer system realized by emulation. Each of the CPUs 1 to 4 realizes a system with an architecture having different functions by emulation. The external device connected via the chipset 5, the memory 6, and the IO bus 7 functions as an emulator, and the multiprocessor system The configuration is determined.

  In the following description, the following are used as CPU (processor) identification numbers.

Logical processor number (0 to n): Identification number of the processor constituting the computer realized by emulation Physical processor number (0 to m): Identification number of the physical processor constituting the hardware shown in FIG. 1 Identification number 9: Signal for isolating the physical processor number, which may be considered the same as the physical processor number Physical ID: Indicates the physical processor number actually encoded, and the content is the same as the physical processor number Although the details of the CPUs 1 to 4 and the chip set are well known to those skilled in the art and are not directly related to the present invention, the detailed configuration is omitted.

  FIG. 3 is a flowchart showing the operation of the present embodiment. Hereinafter, the operation of the present embodiment will be described with reference to FIG.

  When the multiprocessor system is turned on, each of the processors (CPU1 to CPU4) first starts an initial diagnostic test, and the result is sent to the chipset 5 via the CPU bus 8, It is reflected in the configuration register 51 (step S31).

  In the configuration register 51, “1” is set for each processor if the initial diagnosis result is good, and “1” is not set if it is abnormal or cannot be reached until it is set. That is, a processor with “1” set is present and is a normal processor without any abnormality.

  Next, each processor determines a processor having the youngest physical processor number among normal processors as a BSP (bootstrap processor), that is, a first processor (step S32). In the example shown in FIG. 3, the processor 1 (CPU 1 in FIG. 1) having the physical processor number 1 is determined as the BSP. The subsequent steps S33 to S37 are performed by the processor 1.

  The processor 1 that has become the BSP operates as a master for subsequent initial setting processing and performs the following control.

  First, the stored contents of the configuration register 51 are fetched from the chip set 5 and a physical processor information table is created (step S33).

  As shown in FIG. 2B, the physical processor information table includes information on whether or not the physical processor numbers 0 to m are valid (normal), information on whether or not a BSP, a physical ID, and the like.

  A physical processor information table is generated, and the physical ID (coded physical processor number) of the BSP (only one BSP) is obtained (step S34).

  Next, an initial logical processor information table is obtained (step S35). As shown in FIG. 2A, the logical processor information table includes attributes, logical IDs, physical IDs, and the like for the logical processor numbers 0 to n.

  The logical processor information table defines the configuration of a computer system (initial configuration free of faults) realized by emulation, and is obtained by importing from an external storage device (not shown) or an internal storage device (flash memory). . The initial value of the logical processor information table indicates a prescribed configuration predetermined for each processor.

  The attribute shown in the logical processor information table represents whether the processor is assigned as an arithmetic processing processor or a processor assigned as an input / output control processor.

  When the processor 1 determined as BSP in step S32 obtains the initial logical processor information table, the processor 1 whose attribute is shown is the input / output control processor and whose physical processor number indicated by the physical ID is the youngest is shown. The search is performed, and the physical ID obtained in step S34 is assigned to the search (step S36).

  Subsequently, the logical processor (self) assigned with its own physical ID in the initial logical processor information table is invalidated (step S37), and the process is terminated.

  With the above configuration, the logical processor with the attribute having the input / output control processor and the lowest physical processor number controls core devices such as the system disk of the system realized by emulation. A physical processor that is a BSP is allocated and used as described above. A BSP usually has the lowest physical processor number, but it may have moved due to a processor failure. In this case, a physical processor that newly became a BSP was assigned with an initial value. The valid display of the logical processor is released.

  Thus, the creation of the logical processor information table is completed, the configuration of the multiprocessor to be realized by emulation is determined, and the respective processors are initialized according to the logical processor configuration table.

  In the above embodiment, the effective display of the logical processor originally scheduled to use the physical processor that became the new BSP is canceled to determine a new configuration. One or more physical processors may be reserved as spares, and if they are not assigned on the initial logical processor information, the originally planned configuration may be reduced to a new configuration without reducing performance.

It is a block diagram which shows the hardware constitutions of one Embodiment of this invention. (A) is a diagram showing the contents of the logical processor configuration information table, (b) is a diagram showing the contents of the physical processor configuration information table. The structure determination operation | movement flow of one Example of this invention is shown.

Explanation of symbols

1-4 processor (CPU)
5 Chipset 6 Memory 7 IO Bus 8 CPU Bus 9 Processor Individual Dedicated Line 51 Configuration Register S31 to S37 Processing Step

Claims (3)

A multiprocessor system comprising a plurality of processors and realizing a system having an architecture in which each processor has different functions by emulation,
A configuration register for holding a result of an initial diagnostic test performed by each of the plurality of processors at the time of system startup;
Among the plurality of processors, the processor having the lowest physical processor number among the processors having the normal initial diagnostic test result held in the configuration register is the bootstrap processor,
The bootstrap processor includes, for a logical processor number realized by emulation, an attribute indicating whether it is an input / output control processor, a physical ID indicating a physical processor number, and valid / invalid information of the logical processor. Assigns its own physical processor number to the logical processor with the lowest physical processor number among the logical processors defined for I / O control in the logical processor information table. A multiprocessor system in which a logical processor to which a physical ID is assigned is invalidated. An initial start-up method performed in a multiprocessor system that includes a plurality of processors, and each processor realizes a system having an architecture with different functions by emulation,
A plurality of processors each performing an initial diagnostic test at the time of system startup;
Among the processors having normal results of the initial diagnostic test, the processor having the youngest physical processor number as a bootstrap processor;
The bootstrap processor includes, for a logical processor number realized by emulation, an attribute indicating whether it is an input / output control processor, a physical ID indicating a physical processor number, and valid / invalid information of the logical processor. Assigns its own physical processor number to the logical processor with the lowest physical processor number among the logical processors defined for I / O control in the logical processor information table. And a step of invalidating the logical processor to which the physical ID is assigned, and an initial startup method of the multiprocessor system. The program which makes a computer system perform the method of Claim 2.

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