JPH0619376B2 - Waveform display device - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a waveform display device, and more particularly to improvement of waveform display by equivalent time sampling.

(Prior Art) As a kind of waveform display device, an analog input signal is digitized by equivalent time sampling and stored in a waveform memory,
Some are configured to reproduce and display an analog input signal based on the waveform data stored in the waveform memory.

Here, the equivalent time sampling is one in which one portion is sampled from each repetition of the repetitive signal waveform to reproduce the input waveform. Sequential sampling in which the phase of the sample clock is made to differ by a constant time for each repetition, and each repetition There is random sampling in which the phase of each sample clock is randomly varied for an arbitrary time.

According to such equivalent time sampling, the input signal must be a stable repetitive signal in order to reproduce one complete waveform, but even if the input signal has a frequency higher than the frequency of the sample clock, can do.

By the way, the conventional random sampling is configured to perform sampling once for each repetition, as shown in FIG.

FIG. 8 is an explanatory diagram of the reconstruction of the waveform based on the data sampled in this way. Let the repetition period be T,
When the number of data points is N, the time slot width at each data position is T / N. Here, the probability P of randomly sampling m times and having N pieces of data in all time slots is become.

(Problems to be Solved by the Invention) However, according to such a conventional configuration, in order to reconstruct the waveform, it is necessary to perform a large number of samplings and to measure the time from the trigger point to the sampling pulse at each sampling. However, there is a problem that the data processing time becomes long.

The present invention focuses on such a point, and an object thereof is to provide a random sampling type waveform display device capable of data processing in a relatively short time.

(Means for Solving Problems) A waveform display device of the present invention includes a trigger generation circuit that selectively outputs a trigger pulse at a trigger point at which an analog input signal repeatedly crosses a trigger level, a phase disturbance signal generator, A sampling pulse generator that outputs the output signal of the phase disturbance signal generator via a switch and outputs a sampling pulse train of a predetermined frequency; a digitization circuit that converts the analog input signal into digital waveform data according to the sampling pulse; and a trigger Point and trigger point, the time interval measuring device up to the first sampling pulse, the memory for storing the digital waveform data output from the digitizing circuit and the measurement result of the time interval measuring device, and the time interval measurement The measurement result of the measuring instrument and the measurement result of the time interval measuring instrument stored in the memory And a time matching circuit that selectively drives the switch by detecting the same measurement result and controls to selectively update the digital waveform data related to the corresponding time measurement result stored in the memory, A display data generation circuit for generating waveform display data according to the time measurement result and the digital waveform data stored in the memory.

(Example) Hereinafter, an example of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the present invention.
In FIG. 1, reference numeral 1 is an amplifier for amplifying an analog input signal, and its output signal is applied to a digitizing circuit 2 and a trigger generating circuit 3. The output signal of the trigger generation circuit 3 is applied to the time interval measuring device 7 and the address generator 8. A sampling pulse generator 4 outputs a sampling pulse train having a predetermined frequency. Reference numeral 5 denotes a phase disturbance signal generator that gives a disturbance to the phase of the output signal of the sampling pulse generator 4, and is connected to the sampling pulse generator 4 via a switch 6. Such a phase disturbance signal generator 5
For example, a random noise generator is used, and as the sampling pulse generator 4, for example, a crystal oscillator as shown in FIG. 2 is used. The output signal of the sampling pulse generator 4 is applied to the digitizing circuit 2, the time interval measuring device 7 and the address generator 8. Digitization circuit 2
Converts the analog input signal into a digital signal according to the sampling pulse and outputs the digital signal to the memory 9. The time interval measuring device 7 measures the time interval between the trigger pulse output from the trigger generating circuit 3 and the sampling pulse following this trigger pulse, and applies it to the memory 9 and the time collating circuit 10. The address generator 8 outputs address data updated according to the sampling pulse to the memory 9. According to the address data output from the address generator 8, the memory 9 stores the time interval measurement result in each trigger cycle and the sampling waveform data string by the sampling pulse train in the trigger cycle. Time matching circuit 1
When 0, the measurement result of the time interval measuring device 7 and the measurement result of the time interval measuring device 7 stored in the memory 9 are sequentially compared to detect the same measurement result. Then, by detecting the same measurement result, the switch 6 is selectively driven to disturb the output signal phase of the sampling pulse generator 4, and the digital waveform associated with the corresponding time measurement result stored in the memory 9 is generated. The address generator 8 is controlled to selectively update the data. Reference numeral 11 denotes a display data generation circuit that generates display data based on the time interval measurement result and sampling waveform data stored in the memory 9.
Reference numeral 12 is a trigger control circuit for controlling the trigger pulse generation operation of the trigger generation circuit 3 according to the control signal applied from the address generator 8.

The operation of the apparatus thus configured will be described with reference to FIG.

When the power is turned on, the switch 6 is off, and the sampling pulse generator 4 outputs a sampling pulse train with a period T _S. The trigger control circuit 12 first outputs an output command signal to the trigger generation circuit 3 immediately after the power is turned on, and then selectively outputs the output command signal according to the control signal applied from the address generator 8. The trigger generation circuit 3 outputs a trigger pulse to the time interval measuring device 7 and the address generator 8 when the analog input signal first crosses the trigger level after the output command signal is applied from the trigger control circuit 12, and thereafter, The output of the trigger pulse is waited until the trigger control circuit 12 instructs the trigger pulse output. The time interval measuring device 7 includes a trigger generating circuit 3
The time interval T ₁ between the trigger pulse output from the device and the sampling pulse following this trigger pulse is measured and added to the memory 9 and the time collation circuit 10. Digitization circuit 2
The analog input signal is sampled and converted into a digital signal according to the sampling pulse train added from the sampling pulse generator 4, and is output to the memory 9 as a first digital waveform data train. These time interval measuring devices 7
The measurement data and the first waveform data string output from the digitizing circuit 2 are stored in the memory 9 according to the address data output from the address generator 8.

The address generator 8 is preset with the number of data forming each digital waveform data string calculated according to the waveform display setting condition and the total number of digital waveform data strings to be stored, and counts down according to the sampling pulse. By doing so, the number of data taken in is managed. Here, when the length of the time axis on the display is T ₀ , the number of display dots is i, and the sampling pulse cycle is T _S , the number m of digital waveform data strings is m = T _S · i / T It becomes ₀ . The number N of data forming each digital waveform data string is N = T ₀ / T _S.

That is, when the first trigger pulse is output after the power is turned on, the address generator 8 includes the time interval measurement data up to the first sampling pulse following the trigger pulse and the N digital waveform data following the trigger pulse. The head address data for storing one digital waveform data string is output to the memory 9. Then, when N sampling pulses are applied, the trigger control circuit 12 outputs a control signal for controlling the trigger generation circuit 3 to generate the second trigger pulse. Trigger control circuit 1
2 receives this control signal and outputs an output command signal of the second trigger pulse to the trigger generation circuit 3. This allows
The trigger generation circuit 3 outputs the second trigger pulse to the time interval measuring device 7 and the address generator 8, and thereafter waits for the trigger pulse output until the trigger control circuit 12 instructs the trigger pulse output again. . The time interval measuring device 7 measures the time interval T ₂ between the trigger pulse output from the trigger generating circuit 3 and the sampling pulse following this trigger pulse, and applies it to the memory 9 and the time collating circuit 10. The digitizing circuit 2 is a sampling pulse generator 4
The analog input signal is sampled and converted into a digital signal in accordance with the sampling pulse train added from, and is output to the memory 9 as a second digital waveform data train.

The measurement data of the time interval measuring device 7 and the waveform data string output from the digitizing circuit 2 are the address generator 8
It is stored in the memory 9 in accordance with the address data output from.

That is, when the second trigger pulse is output after the power is turned on, the address generator 8 uses the time interval measurement data up to the first sampling pulse following the trigger pulse and the N digital waveform data following the trigger pulse. The head address data for storing the second digital waveform data string is output to the memory 9.

Thereafter, such a series of operations is repeated until the total number of digital waveform data strings stored in the memory 9 reaches the number preset in the address generator 8.

The time collation circuit 10 sequentially collates the measurement result of the time interval measuring device 7 with the measurement result of the time interval measuring device 7 stored in the memory 9 in the course of such a series of data storage. When the same measurement result is detected, the switch 6 is selectively driven to disturb the phase of the sampling pulse output from the sampling pulse generator, and the corresponding time measurement result stored in the memory 9 is added. Control to selectively update the associated digital waveform data. This prevents the same point from being sampled for each repetition when the relationship between the repetition frequency of the analog input signal and the repetition frequency of the sampling pulse is an integral multiple or an integer fraction. For example, it is assumed that the time interval measurement result of the fifth digital waveform data string matches the time interval measurement result of the second digital waveform data string stored in the memory 9. In this case, the current measurement data is stored as the data of the fifth column, and the measurement data of the second column is updated with the next measurement data. By repeating such a procedure, the required number of digital waveform data strings are stored in the memory 9.

The display data generation circuit 11 generates the waveform display data as shown in FIG. 4 according to the time measurement result and the digital waveform data thus stored in the memory 9. In FIG. 4, a circle indicates a digital waveform data string obtained by the first sampling, and a cross indicates a digital waveform data row obtained by the second sampling. Here, assuming that the repetition cycle T is T = K · T _S and the number of data points is N, the time slot width of each data position is T / N. The probability P _K of randomly sampling m times and having N pieces of data in all time slots is become.

That is, with such a configuration, the probability that N pieces of data are available in all time slots is 1 compared to the conventional case.
It becomes higher than the / K power ratio, the number of time data stored can be reduced, and the waveform reconstruction processing can be performed relatively easily.
A quick waveform display can be realized.

As the phase disturbance signal generator 5, for example, a crystal oscillator as shown in FIG. 5 may be used. In this case, these sampling pulse generator 4 and phase disturbance signal generator 5
Of the output signals are uncorrelated with each other, and the fundamental frequencies f ₁ and f _{2 of the two} output signals are substantially equal to each other, or one fundamental frequency and the odd harmonics of the other are approximately equal to each other. When the fundamental frequencies f ₁ and f _{2 of} both output signals are set to be substantially equal to each other, a switch 13, which is driven to open and close complementarily to the switch 6, is provided as shown by a broken line, and sampling from the sampling pulse generator 4 is performed. In outputting the pulse train signal, the switch 6 is closed and once pulled into the output signal of the phase disturbance signal generator 5, then the switch 6 is opened to cause self-excitation, and when the sampling pulse generator 4 is self-excited, the switch is turned on. 13 is closed to draw the phase disturbance signal generator 5 into the output signal of the sampling pulse generator 4. As a result, the phase of the sampling pulse can be substantially disturbed, and a phase disturbing signal having a relatively high amplitude level can be obtained as compared with the configuration using the random noise generator, so that the circuit can be simplified. It should be noted that the switch 13 is not necessary when the one fundamental frequency and the other odd high frequency are made substantially equal.

Further, according to the present invention, by applying a pre-trigger, it is possible to display and observe a waveform before the trigger point.

FIG. 6 is a block diagram showing an embodiment of an apparatus capable of such pre-trigger measurement, and the same parts as those in FIG. 1 are designated by the same reference numerals. In the figure, reference numeral 14 is a pre-trigger control circuit, which presets the number of digital waveform data to be taken into the address generator 8 before the trigger point is reached. In such a configuration, for example, assuming that each digital waveform data string is composed of 100 pieces of data and that 50 pieces of data are fetched before the trigger point is reached, these values are stored in the address generator 8. It is set in advance. The address generator 8 outputs a control signal to the trigger control circuit 12 at the time when 50 pieces of data as the first column of data are fetched in the memory 9, and the trigger control circuit 12 outputs a trigger pulse to the trigger generation circuit 3. Output a command signal. Until the trigger pulse is output, 10 to 1 to 100 assigned to the first column of the memory 9 are assigned.
Data is sequentially updated and stored in a ring shape in the 0 data area. For example, if the trigger pulse is output after the 55th data is stored as shown in the first sample row in FIG. 7, the 50th data following the 56th becomes the data after the trigger point, and for example, the 2nd time in FIG. As shown in the sample sequence of, if the data is output after the 11th data is stored, the 50th data starting from the 12th data becomes the data after the trigger point. In the former case, 50 pieces of data from No. 56 to No. 100 to No. 5 become the data after the trigger point, and 50 pieces of data from No. 6 to 55 become the data before the trigger point (pre-trigger area). In the latter case, 50 pieces of data from No. 12 to 61 become data after the trigger point, and 50 pieces of data from No. 62 to 100 through No. 11 exist before the trigger point (pre-trigger area). Become data. The memory 9 is provided with a pointer for indicating the position of the data from which the trigger pulse is output for each data string, and also stores the time measurement data up to the first sampling pulse following the trigger point. When the time measurement data match, the phase of the sampling pulse is disturbed as in the case of FIG. By repeating such a procedure, the required number of digital waveform data strings are stored in the memory 9.
The display data generation circuit 11 generates the waveform display data as shown in FIG. 8 according to the time measurement result and the digital waveform data thus stored in the memory 9. Note that, in FIG. 8, a circle indicates a digital waveform data string by the first sampling, and a cross indicates a digital waveform data string by the second sampling.

With this configuration, the waveform before the trigger point can be displayed and observed.

By the way, in the configuration of FIG. 6, as shown in FIG. 9, the frequency of the analog input signal is the frequency f of the sampling pulse.
_When it is higher than ₁ , the trigger pulse generation positions are concentrated in a specific area and random data cannot be fetched, and when the waveform is reconstructed, the continuity of the displayed waveform becomes as shown in FIG. The inconvenience of being damaged occurs. In FIG. 9, (a) shows a trigger output command signal, (b) shows a sampling pulse train, and (c) shows an analog input signal. Here, the frequency f of the sampling pulse
₁ (= 1 / T _S ) is almost half of the analog input signal. As a result, the position where the trigger pulse is generated is
The trigger pulse is not output in the second repetitive waveform B, which is limited to the first repetitive waveform A following the sampling pulse. When the waveform is reconstructed based on such sampling data, the portion A is displayed as shown in FIG. 10, but the portion B cannot be displayed because the sampling data is missing.

Such inconvenience can be solved by randomly generating the trigger output control signal. FIG. 11 is a block diagram showing an embodiment of such an apparatus, and FIG. 12 is a trigger generation circuit 3 and a trigger control circuit 12 of FIG.
It is a block diagram showing a concrete example of. In FIG.
The output frequencies f ₁ and f ₂ of the sampling pulse generator 4 and the phase disturbance generator 5 have the same relationship as in FIG. 15
-18 are flip-flops. Flip flop 1
The output signal of the phase disturbance signal generator 5 is applied to the clock terminal of 5, and the data terminal and the inverting output terminal are commonly connected and connected to the clock terminals of the flip-flops 16 and 17. The flip-flop 15 has a frequency _(f 2/2) <output signal _{f 1} is outputted. An address generator 8 is connected to the data terminal of the flip-flop 16.
Is applied with an output control signal of a trigger pulse, and its non-inverting output terminal is connected to the data terminal of the flip-flop 17. As a result, the phase of the output control signal of the trigger pulse is disturbed by the sampling pulse. The non-inverting output terminal of the flip-flop 17 is connected to the data terminal of the flip-flop 18, a trigger pulse is applied to the clock terminal of the flip-flop 18, and the non-inverting output terminal of the flip-flop 18 responds to the sampling pulse. The trigger pulse is output in a temporally random relationship.

With this configuration, a stable waveform display operation can always be obtained regardless of whether the frequencies of the analog input signal and the sampling pulse are high or low.

In FIG. 12, instead of dividing the output signal of the phase disturbance signal generator 5 by the flip-flop 15, a frequency f ₃ (<f ₁ and uncorrelated with f ₁ ) clock is output as shown by a broken line. It is also possible to provide a clock generator 19 that operates and add the output signal to the clock terminals of the flip-flops 16 and 17.

(Effects of the Invention) As described above, according to the present invention, a random sampling type waveform display device capable of data processing in a relatively short time can be realized, and the practical effects are large.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a circuit diagram showing a concrete example of the main part of FIG. 1, FIG. 3 and FIG.
FIG. 7 is a diagram for explaining the operation of FIG. 1, FIG. 5 is a block diagram showing another specific example of the main part of FIG. 1, FIG. 6 is a block diagram showing another embodiment of the present invention, and FIGS. FIG. 10 is an operation explanatory view of FIG. 6, FIG. 11 is also a block diagram showing another embodiment of the present invention, and FIG. 12 is a block diagram showing operation of a specific example of a main part of FIG. FIG. 13 and FIG. 14 are operation explanatory diagrams of a conventional device. 1 ... Input amplifier, 2 ... Digitizing circuit, 3 ... Trigger generator, 4 ... Sampling pulse generator, 5 ... Phase disturbance signal generator, 6 ... Switch, 7 ... Time interval measuring instrument, 8 ... Address generator, 9 ... Memory, 10 ...
Time collation circuit, 11 ... Display data generation circuit, 12 ...
Trigger control circuit.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (56) Reference JP 62-261963 (JP, A) JP 62-207963 (JP, A) JP 62-195564 (JP, A) JP 59- 34164 (JP, A) JP 59-192969 (JP, A) JP 60-9219 (JP, A)

Claims (1)

[Claims] 1. A trigger generation circuit for selectively outputting a trigger pulse at a trigger point where a repetitive analog input signal crosses a trigger level, a phase disturbance signal generator, and an output signal of the phase disturbance signal generator via a switch. A sampling pulse generator that outputs a sampling pulse train of a predetermined frequency, a digitizing circuit that converts an analog input signal into digital waveform data according to the sampling pulse, and a trigger point and the time until the first sampling pulse following the trigger point. A time interval measuring instrument for measuring the interval, a memory for storing the digital waveform data output from the digitizing circuit and the measurement result of the time interval measuring instrument, a measurement result of the time interval measuring instrument and the time interval stored in the memory By successively comparing the measurement results of the measuring instruments and detecting the same measurement result, The time collation circuit that selectively drives the switch and controls to selectively update the digital waveform data related to the time measurement result stored in the memory, and the time measurement result and the digital waveform stored in the memory. A waveform display device, comprising: a display data generation circuit for generating waveform display data according to the data.