JP3958866B2 - Sampling digitizer - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention receives an input waveform of a high-frequency signal, converts it to a low-frequency signal by sampling, stores only a necessary portion of data obtained by AD (analog / digital) conversion, and stores unnecessary data. The present invention relates to a sampling digitizer that ignores data storage memory by ignoring it. Here, the sampling digitizer means a digitizer that samples a repetitive input waveform of about several tens of MHz to several GHz while shifting the phase with a pulse signal having a frequency lower than the input frequency, and performs AD conversion while maintaining similarity to the input waveform. .
[0002]
[Prior art]
First, the operating principle of the sampling digitizer will be briefly described. The digitizer refers to an AD converter (analog / digital converter: hereinafter referred to as “ADC”) that converts an analog signal into a digital signal. When an analog signal is digitized, an upper limit is generated in the frequency for analyzing the signal due to the conversion speed of the ADC. For example, according to the Nyquist sampling theorem, an ADC having a conversion speed of 10 Msps (samples / second) cannot be analyzed unless it is an analog signal of less than 5 MHz. Therefore, in order to analyze a high-frequency analog signal up to several GHz, a frequency conversion technique is used.
[0003]
FIG. 6 shows the configuration of a conventional sampling digitizer, FIG. 7 shows the configuration of the sampling head, and FIGS. 8 and 9 show the principle of sampling.
In FIG. 6, an analog signal to be measured having a high frequency of several hundred MHz is input from the input terminal 1 to the sampling head 2. The sampling head 2 samples the analog signal to be measured with a sample pulse, converts it into a low frequency signal, converts it into a digital signal with a digitizer 3, and transmits it to a processor 4 such as a memory or an arithmetic unit. The sample pulse is shaped into a sample pulse by the sampling pulse generation circuit 6 from the clock pulse from the sampling clock generator 5. The sample pulse has, for example, a pulse width of 100 ps to 200 ps and a pulse height of about ± 6V. The digitizer 3 performs AD conversion at the timing of the clock pulse slightly delayed from the sample pulse.
[0004]
FIG. 7 shows a configuration diagram of an example of the sampling head. The diode switch 8 composed of four diodes d is conducted only for a short time when the sample pulse is inputted to the sample pulse input terminals 11 and 12, and the voltage of the measured analog signal from the sampling head input terminal 1 is set. A proportional charge is stored in the sample and hold capacitor 9. The voltage of the sample hold capacitor 9 is sent to the digitizer 3 through the buffer amplifier 10.
[0005]
8 and 9 show the operation principle of the sampler. FIG. 8 shows a case where a sine wave signal is input. For example, when an AD converter having a conversion speed of 10 Msps is used to analyze a 20 MHz sine wave signal shown in FIG. 8A, sampling is performed with an 18 MHz sample pulse shown in FIG. 8C, and FIG. Digitize by converting to a frequency of 2 MHz as shown in FIG. That is, when an instantaneous value of a sine wave signal with a repetition period of 50 ns (1/20 MHz) is sampled with a pulse signal with a repetition period of 55.56 ns (1/18 MHz) and smoothed later, a sine wave signal of 20 MHz-18 MHz = 2 MHz Will be reproduced. If the signal is 2 MHz, it can be analyzed with a 10 Msps AD converter. However, in this case, the 20 MHz signal cannot be reproduced unless it is a repetitive signal.
[0006]
FIG. 9 shows a principle diagram for measuring the rising characteristics of a trapezoidal wave having a repetition frequency of 10 MHz (period: 100 ns). I want to sample the rising waveform at least every 1 ns. To sample 1 ns, an AD converter having a conversion speed of 1 Gsps is required as it is. A sampler is used to take waveform data with a 10 Msps AD converter. As shown in FIG. 9A, the original waveform has a period of 100 ns (1/10 MHz). If the period of the sample pulse is 101 ns, the data sampled for each waveform is delayed by 1 ns because it is shifted by 1 ns. Yes. Therefore, the output data of 101 ns step can be measured as waveform data of 1 ns step equivalently. In other words, α data is taken first, and then β data is taken with a shift of 1 ns. Subsequently, by taking data such as γ, δ,..., Κ, data of 1 ns step can be reproduced as shown in FIG. This 1 ns is called an equivalent sampling period. In this way, using the sampler, the rising characteristic of the trapezoidal wave can be measured in a 1 ns step with a 10 Msps AD converter.
[0007]
[Problems to be solved by the invention]
In some cases, it is desired to check the linearity of the output waveform of a DAC (digital-to-analog converter) that generates a high-frequency sine wave of about several hundreds of megahertz using the above-described sampling digitizer at high speed. For example, in an analog semiconductor test apparatus, a DUT (device under test) of an analog IC or an analog / digital mixed IC is tested. Therefore, a DAC and a sampling digitizer are mounted, and an analog signal of several hundred MHz is supplied to the DUT. Since the response signal is digitized and tested, the output signal of the DAC is checked before the test.
[0008]
In order to test the linearity of the high-frequency signal generated by the DAC at high speed, it is desirable to generate a test signal with minimum digital data and check the output signal with a sampling digitizer. Therefore, in the DAC, a test signal is generated with 4-point digital data that generates a sine wave.
FIG. 5A is an explanatory diagram for generating a sine wave with four points of data using a DAC. The sine wave to be generated is X indicated by a dotted line. The data is repeated data of four points (1), (2), (3), and (4). For example, the data of (1) is (777), the data of (2) is (FFF), the data of (3) is (777), the data of (4) is (000), and this data is repeated. Then, the DAC generates a Y rectangular wave indicated by a solid line. A sine wave of X can be obtained by passing this Y waveform through a low-pass filter. Since one waveform can be constructed with 4 data points, 256 waveforms can be output with 1,024 points.
[0009]
FIG. 5B shows a desirable waveform for testing the linearity of the output signal of the DAC at high speed. In order to test accurately at high speed, for example, the data value is increased or decreased by one LSB (minimum bit value) of the sine wave memory data every 1/4 period as compared with FIG. Want to generate. Although the LSB may be increased / decreased for each cycle, it is faster to perform every 1/4 cycle for high-speed measurement. Therefore, for example, if the data value of (1) is (777), the data value of (2) is (FFE), the data of (3) is (779), and the data of (4) is (003), then (773) for data (5), (FFA) for data (6), (77D) for data (7), and (007) for data (8). Generate continuously. Therefore, as shown in FIG. 5 (B), a waveform is generated by increasing / decreasing the LSB by 1 bit every quarter period from FIG. 5 (A).
[0010]
FIG. 4 shows a DAC output waveform of about 100 MHz on the order of μs (10 ⁻⁶ s), which is a repetition frequency generated by increasing / decreasing the LSB by 1 bit at 4 bits per frequency. A waveform obtained by enlarging this to the order of ns (10 ⁻⁹ s) is the waveform shown in FIG.
As shown in FIG. 3, when the waveform of the μs order in FIG. 4 is expanded in the ns order, a trapezoidal waveform is obtained. When this waveform is sampled at an equivalent sampling period of the ns order, the voltage level at the point marked with ○ is measured, and the data at all the measurement points are stored and processed. As described above, the voltage level necessary for the measurement is only a point marked with ●, which is a constant voltage.
[0011]
In the processor 4 that processes the output signal of the digitizer 3, all input data is stored in memory and calculation is performed. However, if all unnecessary data is memorized, it becomes a memory loss, and subsequent calculations are also hindered. May occur.
An object of the present invention is to provide a sampling digitizer that stores and processes only the necessary data indicated by ● shown in FIG. 3 in consideration of the relationship between the period of the test signal of the DAC and the sampling signal of the sampling digitizer. And
[0012]
[Means for Solving the Problems]
In order to achieve the above object, the present invention obtains a relational expression between the period of the test signal generated by the DAC shown in FIG. 3 and the equivalent sampling period, and thins out the sample pulse sent from the sampling clock generator to the digitizer. Digitize the data with only the ● mark.
[0013]
As shown in FIG. 3, the voltage to be measured is the voltage at the point marked with ●. Therefore, the interval between the ● mark and the ● mark is expressed as TD as a test cycle. The equivalent sampling period is the interval between the circles and the circles and is expressed as TS. Then, the thinning-out number N is
N = (TD / TS) -1 Formula (1)
It becomes. The period TD and the equivalent sampling period TS are known because they are determined by setting parameters. When the DAC and sampler sampling clock generator are shared, the timing of the mark ● to be measured can be set easily. Therefore, when the thinning circuit is inserted between the sampling clock generator and the digitizer and the thinning number N is thinned out, the digitizer digitizes only the necessary data marked with the ● mark. As the thinning circuit, a programmable counter is appropriate.
[0014]
According to the present invention, in a sampling digitizer that inputs a high frequency signal to be measured, samples it by a sample pulse, converts it to a low frequency signal and digitizes it, inputs the high frequency signal to be measured from the input terminal, and samples it by the sampling pulse. A sampling head for converting to a low frequency signal, a digitizer for converting the output analog signal of the sampling head to digital data, a processor for storing and processing the digital data output from the digitizer, and the sampling A sampling clock generator for generating a sampling frequency for operating the head and the digitizer, and receiving a clock pulse from the sampling clock generator, generating a predetermined pulse width and pulse voltage, and supplying the pulse to the sampling head Do The sampling pulse generator receives a clock pulse from the sampling pulse generator and the sampling clock generator, and performs decimation determined by performing a certain calculation according to the period (TD) of the test signal generated by the DAC and the equivalent sampling period (TS). There is provided a sampling digitizer comprising: a thinning circuit that supplies a timing pulse to the digitizer for each number of clock pulses corresponding to the number (N).
[0015]
The thinning circuit may be configured with a programmable counter.
[0016]
DETAILED DESCRIPTION OF THE INVENTION
DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the invention will be described based on examples with reference to the drawings. FIG. 1 shows a configuration diagram of one embodiment of the present invention, and FIG. 2 shows a timing chart of FIG. First, FIG. 1 will be described.
The main difference between the configuration of FIG. 1 and the conventional configuration of FIG. 6 is that a thinning circuit 20 is inserted between the sampling clock generator 5 and the digitizer 3. The thinning circuit 20 is most suitably a programmable counter capable of freely setting the thinning number N.
[0017]
When the linearity of the output waveform of the DAC is checked at high speed, the waveform shown in FIG. 3 is generated as described above, and the thinning-out number N is set in the programmable counter as the thinning-out number N obtained by the equation (1). Therefore, the digitizer can digitize only the necessary voltage and store it in the memory, or directly calculate it. The sampling timing of the digitizer is set near the center of the trapezoidal waveform in FIG. By sharing the sampling clock generator 5 supplied to the DAC and the sampling head 2, the position can be easily set.
[0018]
FIG. 2 shows a timing chart of the operation of FIG. FIG. 2A shows a clock waveform of the sampling clock generator 5. As shown in FIG. 2B, the sampling pulse generation circuit 6 applies this clock waveform to the sampling head 2 with a sample pulse having a pulse width of 100 ps to 200 ps and a pulse height of about ± 6 V, for example. As shown in FIG. 7, the sampling head 2 inputs positive or negative sample pulses to the sample pulse input terminals 11 and 12, respectively, and samples the signal under measurement from the input terminal 1. FIG. 2C shows the sampled voltage level.
[0019]
However, FIG. 2C includes many voltage levels unnecessary for measurement. Therefore, the thinning circuit 20 removes an unnecessary voltage level based on N = (TD / TS) −1 shown in the above-described equation (1). FIG. 2D shows a clock pulse given to the digitizer 3 by the thinning circuit 20. Accordingly, the sampling clock is given to the digitizer 3 only at the necessary voltage level shown in FIG. 3, and the digitizer 3 can perform A / D conversion at that timing to obtain only the necessary data. The data is the voltage level shown in FIG.
[0020]
As described above, the thinning circuit 20 is suitably a programmable counter. Since the programmable counter can arbitrarily set the thinning number, programming is easy in any test.
[0021]
【The invention's effect】
As described above in detail, the present invention is very effective for the sampling digitizer that checks the linearity of the output waveform of the DAC at high speed. Furthermore, the effect of the present invention is to reduce the number of memories and facilitate calculation even in a digitizer that deletes unnecessary data that can be predicted in advance in the sampling digitizer regardless of the cooperation with the DAC. This effect can be technically significant in practical use.
[Brief description of the drawings]
FIG. 1 is a configuration diagram of an embodiment of the present invention.
FIG. 2 is a timing chart of FIG. 1 of the present invention.
FIG. 3 is an explanatory diagram of a measured analog waveform measured by the present invention.
FIG. 4 is an output waveform diagram of a DAC measured by the present invention.
FIG. 5 is an explanatory diagram for generating a sine wave with four points of data by a DAC.
FIG. 6 is a block diagram of a conventional sampling digitizer.
FIG. 7 is a configuration diagram of a sampling head.
FIG. 8 is a principle diagram of sampling when a sine wave is input.
FIG. 9 is a principle diagram for sampling a repetitive waveform of a trapezoidal wave.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 Input terminal 2 Sampling head 3 Digitizer 4 Processor 5 Sampling clock generator 6 Sampling pulse generation circuit 7 Delay circuit 8 Diode switch 9 Sample hold capacitor 10 Buffer amplifier 11, 12 Sample pulse input terminal 20 Decimation circuit C Capacitor d Diode X Sine wave Y, Z Rectangular wave

Claims (2)

In a sampling digitizer that inputs a high frequency signal to be measured, samples it with a sample pulse, converts it to a low frequency signal, and digitizes it,
A sampling head that inputs a high-frequency signal to be measured from the input terminal , samples it with a sampling pulse, and converts it to a low-frequency signal;
A digitizer for converting the output analog signal of the sampling head into digital data;
A processor for the digital data output of the digitizer to the memory, to processing,
A sampling clock generator for generating a sample frequency for operating the sampling head and the digitizer ;
A sampling pulse generation circuit that receives a clock pulse from the sampling clock generator, generates a predetermined pulse width and pulse voltage, and supplies the pulse width to the sampling head ;
The clock pulse from the sampling clock generator is received, and a certain calculation is performed according to the period (TD) of the test signal generated by the DAC and the equivalent sampling period (TS) according to the thinning number (N) determined. A decimation circuit for supplying timing pulses to the digitizer for each number of clock pulses;
A sampling digitizer characterized by comprising: The thinning circuit and sampling digitizer according to claim 1, characterized in that it is constituted by a programmable counter.

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