CN113985959A - Method and device for correcting time difference between switched capacitor array chips and storage medium - Google Patents
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Abstract
The invention relates to a method and a device for correcting time difference between switched capacitor array chips and a storage medium, belongs to the technical field of precision time measurement, and solves the problem of low correction efficiency caused by complex correction method in multi-channel timing time measurement in the prior art. The method comprises the following steps: utilizing the FPGA to fan out a plurality of clock signals with consistent phases simultaneously, and respectively inputting the plurality of clock signals into the corresponding switched capacitor array chips; carrying out analog sampling on the received clock signal through each switched capacitor array chip, and carrying out analog-to-digital conversion to obtain a digital clock signal; and performing online calculation on the digital clock signal by using the FPGA to correspondingly obtain the timing time of each switched capacitor array chip, further obtaining a correction coefficient of each switched capacitor array, and correcting the timing time of the corresponding switched capacitor array chip based on the correction coefficient. The method can greatly simplify the correction process and improve the correction efficiency.
Description
Technical Field
The invention relates to the technical field of precision time measurement, in particular to a method and a device for correcting time difference between switched capacitor array chips and a storage medium.
Background
At present, many nuclear physics experiments have applied a mode of 'switched capacitor array chip (SCA) analog sampling + low-speed ADC reading' to perform high-speed data acquisition. Due to the influence of the manufacturing process of the SCA chip, the internal wiring length of the electronic board card, the connector and the like, the timing of waveforms input to different SCA chips is different. Therefore, in the nuclear physics experiment which has high requirement on the time precision, the time difference between different chips needs to be corrected.
In the prior art, when the number of SCA chips is small, the SCA chips are usually directly connected to the acquisition channel of the target chip through an external signal generator, and time correction is performed by generating a standard pulse waveform with completely consistent phase. In some multi-channel and high-time-resolution large-scale data acquisition systems (for example, a positron beam bunch detection system sometimes has hundreds or even thousands of data acquisition channels), a plurality of sets of data acquisition boards are needed, each data acquisition board is provided with a plurality of SCA chips, and due to the limitation of the number of channels of a signal generator, the conventional method is quite complicated.
Firstly, under the condition that a board card with a plurality of SCA chips exists, the number of channels of a signal generator is often small, only a few chips can be corrected each time, repeated operation is needed for many times, a plurality of human error factors are brought, and time and energy are consumed; secondly, the waveform of the signal generator is subjected to multi-path fan-out, a special fan-out system is required to be adopted for time correction, the complexity of the correction system is greatly increased, more time uncertainty is introduced, and the time correction precision is further influenced.
Disclosure of Invention
In view of the foregoing analysis, embodiments of the present invention provide a method and an apparatus for calibrating time difference between switched capacitor array chips, and a storage medium, so as to solve the problems of large error, low efficiency, and complicated calibration apparatus in the conventional method for calibrating time difference between switched capacitor array chips
In one aspect, the present invention provides a method for correcting a time difference between switched capacitor array chips, including:
utilizing an FPGA to fan out a plurality of clock signals with consistent phases at the same time, and respectively inputting the clock signals into corresponding switched capacitor array chips;
carrying out analog sampling on the received clock signal through each switched capacitor array chip, and carrying out analog-to-digital conversion to obtain a digital clock signal;
and utilizing the FPGA to perform online calculation on the digital clock signal to correspondingly obtain the timing time of each switched capacitor array chip, further obtaining the correction coefficient of each switched capacitor array, and correcting the timing time of the corresponding switched capacitor array chip based on the correction coefficient.
Further, the fanning out a plurality of clock signals with the same phase at the same time by using the FPGA includes:
generating a clock signal corresponding to a clock signal output channel by using the FPGA;
and regulating and controlling the phase of the clock signal in each clock signal output channel by using a mixing time manager in the FPGA according to the delay difference of different clock signal output channels in the FPGA so as to enable the phase of the clock signal output by each clock signal output channel pin to be consistent.
Furthermore, a pin of each clock signal output channel in the FPGA is in communication connection with an input pin of the corresponding switched capacitor array chip, and communication distances between the pin of each clock signal output channel and the input pin of the corresponding switched capacitor array chip are equal.
Further, the performing online calculation on the digitized clock signal by using the FPGA to obtain the timing time of each switched capacitor array chip correspondingly includes:
repeating the following steps to obtain the timing time corresponding to the measurement sequence of each switched capacitor array chip: and simultaneously measuring each switched capacitor array chip to obtain a digital clock signal corresponding to each switched capacitor array, and further calculating to obtain the timing time corresponding to the current measurement sequence of each switched capacitor array chip.
Further, the further obtaining a correction coefficient of each of the switched capacitor arrays includes:
taking the timing time corresponding to the measurement sequence of any switched capacitor array chip as reference time;
aiming at a first switched capacitor array chip, correspondingly differentiating the timing time corresponding to the first switched capacitor array chip with the timing time corresponding to any one switched capacitor array chip according to the same measurement sequence, and further obtaining a plurality of time differences corresponding to the first switched capacitor array chip; the first switched capacitor array chip is each of the other switched capacitor array chips except any one switched capacitor array chip;
averaging a plurality of time differences of each first switched capacitor array chip to obtain a correction coefficient of each first switched capacitor array chip.
Further, the method also comprises the following steps:
and storing the correction coefficient of each switched capacitor array chip in a memory of the FPGA, and automatically correcting the timing time of each switched capacitor array chip according to the stored correction coefficient.
Further, the FPGA carries out on-line calculation on the digital clock signal through a leading edge timing algorithm to correspondingly obtain the timing time of each switched capacitor array chip, or,
and the FPGA carries out on-line calculation on the digital clock signal through a digital constant ratio timing algorithm to correspondingly obtain the timing time of each switched capacitor array chip.
On the other hand, the invention provides a device for correcting the time difference between the switched capacitor array chips, which comprises an FPGA and an analog-to-digital conversion circuit;
the FPGA is in communication connection with the plurality of switched capacitor array chips and is used for simultaneously fanning out a plurality of clock signals with consistent phases and respectively inputting the clock signals into the corresponding switched capacitor array chips;
each switched capacitor array chip carries out analog sampling on a received clock signal, and the analog-to-digital conversion circuit carries out analog-to-digital conversion on a signal obtained by the analog sampling to obtain a digital clock signal;
and the FPGA carries out on-line calculation on the digital clock signal to correspondingly obtain the timing time of each switched capacitor array chip, so as to obtain the correction coefficient of each switched capacitor array, and corrects the timing time of the corresponding switched capacitor array chip based on the correction coefficient.
Furthermore, a clock signal output channel pin of the FPGA is in communication connection with any pin of the corresponding switched capacitor array chip, and the communication distances are equal.
In still another aspect, the present invention provides a storage medium for storing a firmware program, and a processor executing the firmware program can implement the aforementioned method for correcting the time difference between the switched capacitor array chips.
Compared with the prior art, the invention can realize at least one of the following beneficial effects:
1. according to the method and the device for correcting the time difference between the switched capacitor array chips, the clock signals with consistent phases are generated through the FPGA, and are directly input into the corresponding switched capacitor array chips for time correction at the same time, an additional signal generator is not needed, the process is simplified, the artificial errors are reduced, the correction precision and the correction efficiency are improved, and meanwhile, the time difference correcting device is simplified.
2. According to the method and the device for correcting the time difference between the switched capacitor array chips, the communication distances between the pins of each clock signal output channel and the input pins of the corresponding switched capacitor array chip are set to be equal, so that the waveform phases of clock signals entering the switched capacitor array chips are kept consistent, and the correction precision of the time difference is further improved.
3. The method and the device for correcting the time difference between the chips of the switched capacitor array adjust the phase of each clock signal by using the mixed time manager in the FPGA, the jitter of the rising edge of the processed clock signal is less than that of the clock signals generated by most of the signal generators, and the time of the rising edge of the processed clock signal is less than that of the clock signals generated by most of the signal generators, so that the time resolution is improved, and the correction precision of the time difference between the chips can be further improved.
In the invention, the technical schemes can be combined with each other to realize more preferable combination schemes. Additional features and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and drawings.
Drawings
The drawings are only for purposes of illustrating particular embodiments and are not to be construed as limiting the invention, wherein like reference numerals are used to designate like parts throughout.
FIG. 1 is a flowchart of a method for calibrating time difference between switched capacitor array chips according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of pulses respectively entering four switched capacitor array chips according to an embodiment of the present invention;
FIG. 3 is a diagram of a device for correcting time difference between switched capacitor array chips according to an embodiment of the invention.
Detailed Description
The accompanying drawings, which are incorporated in and constitute a part of this application, illustrate preferred embodiments of the invention and together with the description, serve to explain the principles of the invention and not to limit the scope of the invention.
Method embodiment
The invention discloses a method for correcting time difference between switched capacitor array chips. As shown in fig. 1, the method comprises the steps of:
step S110, fanning out a plurality of clock signals with consistent phases simultaneously by using the FPGA, and respectively inputting the plurality of clock signals into corresponding switch capacitor array chips (SCAs). Specifically, the clock signal is input to any one of the input pins of the switched capacitor array chip.
And step S120, performing analog sampling on the received clock signal through each switched capacitor array chip, and performing analog-to-digital conversion to obtain a digital clock signal.
Step S130, the FPGA is used for carrying out on-line calculation on the digital clock signal to correspondingly obtain the timing time of each switched capacitor array chip, so that the correction coefficient of each switched capacitor array is obtained, and the timing time of the corresponding switched capacitor array chip is corrected based on the correction coefficient.
As shown in fig. 2, the pulse time entering each of the switch capacitor array chips is different, and therefore, the pulse time entering each of the switch capacitor array chips after correction is corrected to be completely consistent.
Specifically, the FPGA generates clock signals with the same phase, inputs the clock signals into each switched capacitor array chip, inputs the clock signals into an analog-to-digital conversion circuit after analog sampling, performs analog-to-digital conversion to obtain digital clock signals, inputs the digital clock signals into the FPGA, performs online calculation to obtain the timing time of each switched capacitor array chip, obtains the correction coefficient of each switched capacitor array chip based on the timing time, and corrects the timing time of each switched capacitor array chip based on the correction coefficient. According to the invention, the clock signal generated by the FPGA is utilized to directly carry out time correction on each switched capacitor array chip, an additional signal generator is not needed, and the time correction on a plurality of chips is not needed to be carried out for many times, so that external error factors are reduced, the correction process is simplified, and the correction efficiency is improved.
Preferably, the fanning out a plurality of clock signals with the same phase at the same time by using the FPGA includes:
and generating a clock signal corresponding to the clock signal output channel by using the FPGA. According to the delay difference of different clock signal output channels in the FPGA, a mixing time manager (MMCM) in the FPGA is used for regulating and controlling the phase of a clock signal in each clock signal output channel, so that the phases of the clock signals output by pins of each clock signal output channel are consistent, errors are reduced, and the time correction precision is improved.
Specifically, after the phase of the clock signal is adjusted by the hybrid time manager, the clock signal can be directly fanned out to the input pins of the corresponding switched capacitor array chips, so that fanout equipment or devices with complex design in the prior art are avoided, the device is simplified, and the complexity of time correction is reduced. In addition, the jitter of the clock signal processed by the mixing time manager is about 50ps, which is smaller than the jitter of the signals generated by most signal generators, so that the accuracy of time correction can be further improved. Importantly, the rising edge time of the clock signal processed by the mixing time manager is shorter, about 1ns, and the time is shorter than the rising edge time of the signals generated by most signal generators, so that the time resolution can be improved, and the time correction precision can be improved.
Preferably, taking Xilinx A7 series FPGA as an example, the hybrid time manager has a large adjustable range of output frequency, the maximum output clock frequency is 800MHz, the minimum output frequency is 4.69MHz, and the large frequency adjustable range can meet the requirement of time correction of the switch capacitance array chip under different sampling frequencies. Illustratively, the current sampling rate of the switched capacitor array chip is 5GSPS, then the time interval between adjacent sampling points is 0.2ns, if each channel has 1000 sampling points, a waveform of 200ns can be acquired at a time, although one period of 5MHz can be acquired, the frequency is low, which causes the sampling rate to decrease, and further affects the correction rate, and the sampling frequency is too high, which is also greatly affected by the bandwidth and the timing method (for example, in leading edge timing, if the bandwidth cannot meet the requirement, the clock signal may be distorted, and the timing time is affected), which is not beneficial for time correction, therefore, it is preferable to select the output frequency range of the hybrid time manager as [100MHz,500MHz ] to perform time correction.
Preferably, a pin of each clock signal output channel in the FPGA is in communication connection with an input pin of the corresponding switched capacitor array chip, and communication distances between the pins of the clock signal output channels and the input pins of the corresponding switched capacitor array chip are equal. By setting the communication distances to be equal, the waveform phases of the clock signals entering the corresponding switched capacitor array chips can be ensured to be consistent, so that the accuracy of time correction is improved.
Preferably, the on-line calculation of the digitized clock signal by using the FPGA to obtain the timing time of each switched capacitor array chip correspondingly comprises:
repeating the following steps to obtain the timing time corresponding to the measurement sequence of each switched capacitor array chip: and simultaneously measuring each switched capacitor array chip to obtain a digital clock signal corresponding to each switched capacitor array, and further calculating to obtain the timing time corresponding to the current measurement sequence of each switched capacitor array chip. In other words, each switch capacitor array chip is measured at the same time, and the measurement is performed for multiple times, so as to obtain multiple timing times corresponding to the measurement sequence of each switch capacitor array chip.
Preferably, obtaining a correction factor for each of the switched capacitor arrays comprises:
taking the timing time corresponding to the measurement sequence of any switched capacitor array chip as reference time; i.e. any switched capacitor array chip as a reference.
Aiming at a first switched capacitor array chip, correspondingly differentiating the timing time corresponding to the first switched capacitor array chip with the timing time corresponding to any one of the switched capacitor array chips according to the same measurement sequence, and further obtaining a plurality of time differences corresponding to the first switched capacitor array chip; the first switched capacitor array chip is each of the other switched capacitor array chips except any one of the switched capacitor array chips (i.e., the switched capacitor array chip serving as the reference).
Averaging a plurality of time differences of each first switched capacitor array chip to obtain a correction coefficient of each first switched capacitor array chip. Illustratively, it is specifically represented by the following formula:
wherein, cnA correction coefficient indicating an nth first switched capacitor array chip, where N is 1,2, … N, and N indicates the number of first switched capacitor array chips; t isniRepresents the corresponding timing time T of the ith measurement of the nth first switched capacitor array chip0iThe timing time of the ith measurement of any switched capacitor array chip (i.e. the switched capacitor array chip used as the reference) is shown, and m represents the total measurement times.
Preferably, the method further comprises: and storing the correction coefficient of each switched capacitor array chip in a memory of the FPGA, and automatically correcting the timing time of each switched capacitor array chip according to the stored correction coefficient. Specifically, in practical application, when the corresponding device is started (that is, the FPGA is connected to the plurality of switched capacitor array chips), the timing time of the corresponding switched capacitor array chip can be automatically corrected according to the correction coefficient of each switched capacitor array chip stored in the memory, and the multi-channel timing time correction efficiency of the device in the application process is greatly improved.
Preferably, the FPGA performs online calculation on the digitized clock signal through a leading edge timing algorithm to obtain the timing time of each switched capacitor array chip, or the FPGA performs online calculation on the digitized clock signal through a digital constant ratio timing algorithm to obtain the timing time of each switched capacitor array chip.
Device embodiment
Since the embodiment of the apparatus and the embodiment of the method are based on the same working principle, the method embodiment can be referred to for the repeated points, and will not be described herein again.
The invention further discloses a device for correcting the time difference between the switched capacitor array chips. As shown in fig. 3, the apparatus includes an FPGA and an analog-to-digital conversion circuit (ADC).
Specifically, the FPGA is in communication connection with the plurality of switched capacitor array chips, and is configured to fan out a plurality of clock signals with the same phase at the same time, and input the plurality of clock signals to the corresponding switched capacitor array chips, respectively. Specifically, a clock signal output channel pin of the FPGA is in communication connection with any one pin of each switched capacitor array chip.
Each switched capacitor array chip carries out analog sampling on the received clock signal, inputs the sampled clock signal into an analog-to-digital conversion circuit, and carries out analog-to-digital conversion to obtain a digital clock signal. The analog-to-digital conversion circuit is in communication connection with the FPGA, a digital clock signal is input into the FPGA, the FPGA performs online calculation on the digital clock signal to correspondingly obtain the timing time of each switched capacitor array chip, further obtain the correction coefficient of each switched capacitor array, and the timing time of the corresponding switched capacitor array chip is corrected based on the correction coefficient.
Preferably, a clock signal output channel pin of the FPGA is in communication connection with any one pin of the corresponding switched capacitor array chip, and the communication distances are equal.
In another embodiment of the present invention, a storage medium configured for an FPGA is disclosed, and the storage medium is used for storing a firmware program, and the processor executes the firmware program to implement the aforementioned method for correcting the time difference between the switched capacitor array chips. The storage medium may be Random Access Memory (RAM), memory, Read Only Memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art. In practical application, the FPGA can complete configuration by only reading the curing program configured in the erasable read only memory, thereby implementing the aforementioned method for correcting the time difference between the switched capacitor array chips.
Compared with the prior art, the method and the device for correcting the time difference between the switched capacitor array chips disclosed by the embodiment of the invention have the advantages that firstly, clock signals with consistent phases are generated through the FPGA, and the clock signals are directly input into the corresponding switched capacitor array chips for time correction, no additional signal generator is needed, the process is simplified, the human errors are reduced, the correction precision and the correction efficiency are improved, and meanwhile, the time difference correcting device is simplified. And secondly, setting the communication distances between the pins of each clock signal output channel and the input pins of the corresponding switched capacitor array chip to be equal to ensure that the waveform phases of the clock signals entering the switched capacitor array chip are kept consistent, thereby further improving the correction precision of the time difference. In addition, the method and the device for correcting the time difference between the switched capacitor array chips disclosed by the embodiment of the invention adjust the phase of each clock signal by using the mixed time manager in the FPGA, the jitter of the rising edge of the processed clock signal is less than that of the clock signals generated by most of the signal generators, and the time of the rising edge of the processed clock signal is less than that of the clock signals generated by most of the signal generators, so that the time resolution is improved, and the correction precision of the time difference between the chips can be further improved.
Those skilled in the art will appreciate that all or part of the flow of the method implementing the above embodiments may be implemented by hardware associated with instructions of a firmware program, and the firmware program may be compiled by a computer program and then solidified in a readable storage medium. The readable storage medium is a magnetic disk, an optical disk, an erasable read-only memory, and the like.
The above description is only for the preferred embodiment of the present invention, but the scope of the present invention is not limited thereto, and any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope of the present invention are included in the scope of the present invention.
Claims (10)
1. A method for correcting time difference between switched capacitor array chips is characterized by comprising the following steps:
utilizing an FPGA to fan out a plurality of clock signals with consistent phases at the same time, and respectively inputting the clock signals into corresponding switched capacitor array chips;
carrying out analog sampling on the received clock signal through each switched capacitor array chip, and carrying out analog-to-digital conversion to obtain a digital clock signal;
and utilizing the FPGA to perform online calculation on the digital clock signal to correspondingly obtain the timing time of each switched capacitor array chip, further obtaining the correction coefficient of each switched capacitor array, and correcting the timing time of the corresponding switched capacitor array chip based on the correction coefficient.
2. The method of claim 1, wherein the simultaneously fanning out a plurality of clock signals with the same phase using the FPGA comprises:
generating a clock signal corresponding to a clock signal output channel by using the FPGA;
and regulating and controlling the phase of the clock signal in each clock signal output channel by using a mixing time manager in the FPGA according to the delay difference of different clock signal output channels in the FPGA so as to enable the phase of the clock signal output by each clock signal output channel pin to be consistent.
3. The method according to claim 2, wherein a pin of each clock signal output channel in the FPGA is in communication connection with an input pin of the corresponding switched capacitor array chip, and a communication distance between the pin of each clock signal output channel and the input pin of the corresponding switched capacitor array chip is equal.
4. The method for correcting the time difference between the switched capacitor array chips according to claim 2 or 3, wherein the on-line calculation of the digitized clock signal by the FPGA corresponding to the obtained timing time of each switched capacitor array chip comprises:
repeating the following steps to obtain the timing time corresponding to the measurement sequence of each switched capacitor array chip: and simultaneously measuring each switched capacitor array chip to obtain a digital clock signal corresponding to each switched capacitor array, and further calculating to obtain the timing time corresponding to the current measurement sequence of each switched capacitor array chip.
5. The method of claim 4, wherein the step of obtaining the correction factor for each switched capacitor array comprises:
taking the timing time corresponding to the measurement sequence of any switched capacitor array chip as reference time;
aiming at a first switched capacitor array chip, correspondingly differentiating the timing time corresponding to the first switched capacitor array chip with the timing time corresponding to any one switched capacitor array chip according to the same measurement sequence, and further obtaining a plurality of time differences corresponding to the first switched capacitor array chip; the first switched capacitor array chip is each of the other switched capacitor array chips except any one switched capacitor array chip;
averaging a plurality of time differences of each first switched capacitor array chip to obtain a correction coefficient of each first switched capacitor array chip.
6. The method of claim 1, further comprising:
and storing the correction coefficient of each switched capacitor array chip in a memory of the FPGA, and automatically correcting the timing time of each switched capacitor array chip according to the stored correction coefficient.
7. The method according to claim 4, wherein the FPGA performs on-line calculation on the digital clock signal by using a leading edge timing algorithm to obtain the timing time of each of the switched capacitor array chips, or,
and the FPGA carries out on-line calculation on the digital clock signal through a digital constant ratio timing algorithm to correspondingly obtain the timing time of each switched capacitor array chip.
8. A correction device for time difference between switched capacitor array chips is characterized by comprising an FPGA and an analog-to-digital conversion circuit;
the FPGA is in communication connection with the plurality of switched capacitor array chips and is used for simultaneously fanning out a plurality of clock signals with consistent phases and respectively inputting the clock signals into the corresponding switched capacitor array chips;
each switched capacitor array chip carries out analog sampling on a received clock signal, and the analog-to-digital conversion circuit carries out analog-to-digital conversion on a signal obtained by the analog sampling to obtain a digital clock signal;
and the FPGA carries out on-line calculation on the digital clock signal to correspondingly obtain the timing time of each switched capacitor array chip, so as to obtain the correction coefficient of each switched capacitor array, and corrects the timing time of the corresponding switched capacitor array chip based on the correction coefficient.
9. The device for correcting the time difference between the switched capacitor array chips according to claim 8, wherein a clock signal output channel pin of the FPGA is in communication connection with any one pin of the corresponding switched capacitor array chips, and the communication distances are equal.
10. A storage medium for storing a firmware program, the processor executing the firmware program being capable of implementing the method for correcting a time difference between switched capacitor array chips as claimed in any one of claims 1 to 7.
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