CN113985959B - Method and device for correcting time difference between switch capacitor array chips and storage medium - Google Patents
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Abstract
The invention relates to a method, a device and a storage medium for correcting time difference between switch capacitor array chips, belongs to the technical field of precise time measurement, and solves the problem of low correction efficiency caused by complex correction method in multichannel timing time measurement in the prior art. The method comprises the following steps: simultaneously fanning out a plurality of clock signals with consistent phases by using an FPGA, and respectively inputting the plurality of clock signals into corresponding switch capacitor array chips; analog sampling is carried out on the received clock signals through each switch capacitor array chip, and digital clock signals are obtained after analog-to-digital conversion is carried out; and carrying out on-line calculation on the digital clock signal by using the FPGA to correspondingly obtain the timing time of each switched capacitor array chip, further obtaining the correction coefficient of each switched capacitor array, and correcting the timing time of the corresponding switched capacitor array chip based on the correction coefficient. The method can greatly simplify the correction flow and improve the correction efficiency.
Description
Technical Field
The present invention relates to the field of precision time measurement technologies, and in particular, to a method and apparatus for correcting time difference between switched capacitor array chips, and a storage medium.
Background
Currently, many nuclear physics experiments have applied a "switched capacitor array chip (SCA) analog sampling+low-speed ADC reading" approach to high-speed data acquisition. Due to the influence of SCA chip manufacturing process, electronic board internal wiring length, connectors and the like, waveform timing input to different SCA chips often varies. Therefore, in the nuclear physical experiment with higher time precision requirement, the time difference between the different chips needs to be corrected.
In the prior art, when the number of SCA chips is small, the SCA chips are usually directly connected into a target chip acquisition channel through an external signal generator, and time correction is performed by generating standard pulse waveforms with completely consistent phases. In some multi-channel, high-time resolution large data acquisition systems (e.g., positron beam cluster detection systems sometimes have as many as several hundred or even thousands of data acquisition channels), multiple sets of data acquisition boards are required, each with multiple SCA chips, and conventional methods can be quite cumbersome due to the number of channels of the signal generator.
In the prior art, at least the following defects are existed, firstly, under the condition of a board card with a plurality of SCA chips, the number of channels of a signal generator is often less, and only a few chips can be corrected at a time, so that repeated operation is needed for a plurality of times, a plurality of human error factors are brought, and time and energy are consumed; secondly, the waveform of the signal generator is subjected to multipath fan-out, which requires a special fan-out system to perform time correction, so that the complexity of a correction system is greatly increased, more time uncertainty is introduced, and time correction accuracy is further affected.
Disclosure of Invention
In view of the above analysis, the embodiments of the present invention provide a method, an apparatus and a storage medium for correcting time differences between switch capacitor array chips, which are used for solving the problems of large error, low efficiency and complex correction apparatus in the existing method for correcting time differences between switch capacitor array chips
In one aspect, the present invention provides a method for correcting a time difference between switched capacitor array chips, including:
simultaneously fanning out a plurality of clock signals with consistent phases by using an FPGA, and respectively inputting the plurality of clock signals into corresponding switch capacitor array chips;
analog sampling is carried out on the received clock signals through each switch capacitor array chip, and digital clock signals are obtained after analog-to-digital conversion is carried out;
and carrying out on-line calculation on the digital clock signal by using the FPGA to correspondingly obtain the timing time of each switch capacitor array chip, further obtaining the correction coefficient of each switch capacitor array, and correcting the timing time of the corresponding switch capacitor array chip based on the correction coefficient.
Further, the fanning out a plurality of clock signals with identical phases by using the FPGA simultaneously includes:
generating a clock signal corresponding to a clock signal output channel in the FPGA by utilizing the FPGA;
according to the delay difference of different clock signal output channels in the FPGA, the phase of the clock signal in each clock signal output channel is regulated and controlled by utilizing a mixed time manager in the FPGA, so that the phases of the clock signals output at the pins of each clock signal output channel are consistent.
Further, pins of each clock signal output channel in the FPGA are in communication connection with input pins of the corresponding switched capacitor array chip, and communication distances between the pins of each clock signal output channel and the input pins of the corresponding switched capacitor array chip are equal.
Further, the performing on-line computation on the digitized clock signal by using the FPGA to obtain a timing time of each switched capacitor array chip correspondingly includes:
the following steps are repeated to obtain the timing time of each switch capacitor array chip corresponding to the measurement sequence: simultaneously, each switch capacitor array chip is measured to obtain a digital clock signal corresponding to each switch capacitor array, and then the timing time corresponding to the current measurement sequence of each switch capacitor array chip is calculated.
Further, the obtaining the correction coefficient of each switched capacitor array further includes:
taking the timing time of any switch capacitor array chip corresponding to the measurement sequence as reference time;
aiming at a first switch capacitor array chip, according to the same measurement sequence, the timing time corresponding to the first switch capacitor array chip is correspondingly differenced with the timing time corresponding to any switch capacitor array chip, so as to obtain a plurality of time differences corresponding to the first switch capacitor array chip; the first switched capacitor array chip is each switched capacitor array chip in other switched capacitor array chips except any switched capacitor array chip;
and averaging a plurality of time differences of each first switched capacitor array chip to obtain a correction coefficient of each first switched capacitor array chip.
Further, the method further comprises the following steps:
and storing the correction coefficient of each switch capacitor array chip in a memory of the FPGA, and automatically correcting the timing time of each switch capacitor array chip according to the stored correction coefficient.
Furthermore, the FPGA carries out on-line calculation on the digital clock signal through a front edge timing algorithm to correspondingly obtain the timing time of each switch capacitor array chip, or,
and the FPGA carries out on-line calculation on the digital clock signal through a digital constant ratio timing algorithm to correspondingly obtain the timing time of each switch capacitor array chip.
On the other hand, the invention provides a correction device for time difference between switch capacitor array chips, which comprises an FPGA and an analog-to-digital conversion circuit;
the FPGA is in communication connection with the plurality of switch capacitor array chips, and is used for simultaneously fanning out a plurality of clock signals with consistent phases and respectively inputting the plurality of clock signals into the corresponding switch capacitor array chips;
each switch capacitor array chip performs analog sampling on the received clock signal, and the analog-to-digital conversion circuit performs analog-to-digital conversion on the signal obtained by the analog sampling to obtain a digital clock signal;
and the FPGA carries out on-line calculation on the digital clock signals to correspondingly obtain the timing time of each switch capacitor array chip, so as to obtain the correction coefficient of each switch capacitor array, and corrects the timing time of the corresponding switch capacitor array chip based on the correction coefficient.
Furthermore, the pins of the clock signal output channels of the FPGA are in communication connection with any pin of the corresponding switched capacitor array chip, and the communication distances are equal.
In still another aspect, the present invention provides a storage medium storing a firmware program, where a processor executes the firmware program to implement the foregoing method for correcting a time difference between switched capacitor array chips.
Compared with the prior art, the invention has at least one of the following beneficial effects:
1. the method and the device for correcting the time difference between the switch capacitor array chips generate the clock signals with consistent phases through the FPGA, and simultaneously, the clock signals are directly input into the corresponding switch capacitor array chips for time correction, an additional signal generator is not needed, the flow is simplified, the human error is reduced, the correction precision and the correction efficiency are improved, and meanwhile, the time difference correction device is simplified.
2. According to the method and the device for correcting the time difference between the switch capacitor array chips, the communication distance between the pins of each clock signal output channel and the input pins of the corresponding switch capacitor array chip is equal, so that the waveform phase of the clock signal entering the switch capacitor array chip is ensured to be consistent, and the correction precision of the time difference is further improved.
3. According to the method and the device for correcting the time difference between the switch capacitor array chips, the mixed time manager in the FPGA is utilized to adjust the phase of each clock signal, the jitter of the rising edge of the processed clock signal is smaller than that of the clock signal generated by most signal generators, and the rising edge time of the processed clock signal is smaller than that of the clock signal generated by most signal generators, so that the time resolution is improved, and the time difference correction precision between the chips can be further improved.
In the invention, the technical schemes can be mutually combined to realize more preferable combination schemes. Additional features and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention may be realized and attained by the structure particularly pointed out in the written description and drawings.
Drawings
The drawings are only for purposes of illustrating particular embodiments and are not to be construed as limiting the invention, like reference numerals being used to refer to like parts throughout the several views.
FIG. 1 is a flowchart of a method for correcting time differences between switch capacitor array chips according to an embodiment of the present invention;
FIG. 2 is a schematic pulse diagram of the embodiment of the present invention entering four switched capacitor array chips respectively;
fig. 3 is a schematic diagram of a device for correcting time difference between switched capacitor array chips according to an embodiment of the invention.
Detailed Description
Preferred embodiments of the present invention will now be described in detail with reference to the accompanying drawings, which form a part hereof, and together with the description serve to explain the principles of the invention, and are not intended to limit the scope of the invention.
Method embodiment
In one embodiment of the invention, a method for correcting time difference between switch capacitor array chips is disclosed. As shown in fig. 1, the method comprises the steps of:
step S110, a plurality of clock signals with consistent phases are fanned out simultaneously by utilizing the FPGA, and the plurality of clock signals are respectively input into corresponding switch capacitor array chips (SCA). Specifically, the clock signal is input into the switch capacitor array chip through any one of the input pins.
And step S120, carrying out analog sampling on the received clock signals through each switched capacitor array chip, and carrying out analog-to-digital conversion to obtain digital clock signals.
And step 130, performing on-line calculation on the digital clock signal by using the FPGA to obtain the timing time of each switched capacitor array chip correspondingly, so as to obtain the correction coefficient of each switched capacitor array, and correcting the timing time of the corresponding switched capacitor array chip based on the correction coefficient.
As shown in fig. 2, the pulse time entering each switched capacitor array chip is different, so that the pulse time entering each switched capacitor array chip after correction is completely consistent.
Specifically, the FPGA generates clock signals with the same phase, inputs the clock signals into each switched capacitor array chip, performs analog sampling, inputs the clock signals into the analog-to-digital conversion circuit, performs analog-to-digital conversion to obtain digital clock signals, inputs the digital clock signals into the FPGA, performs online calculation to obtain timing time of each switched capacitor array chip, obtains correction coefficients of each switched capacitor array chip based on the timing time, and corrects the timing time of the switched capacitor array chip based on the correction coefficients. According to the invention, the clock signals generated by the FPGA are utilized to directly carry out time correction on each switched capacitor array chip, an additional signal generator is not needed, and a plurality of chips are not needed to be subjected to time correction for a plurality of times, so that external error factors are reduced, the correction flow is simplified, and the correction efficiency is improved.
Preferably, the fanning out a plurality of clock signals with identical phases simultaneously using the FPGA includes:
the FPGA is used to generate a clock signal corresponding to the clock signal output channel therein. According to the delay difference of different clock signal output channels in the FPGA, the phase of the clock signal in each clock signal output channel is regulated and controlled by utilizing a mixed time manager (MMCM) in the FPGA so as to ensure that the phases of the clock signals output by pins of each clock signal output channel are consistent, thereby reducing errors and improving time correction precision.
Specifically, after the phase of the clock signal is adjusted by the mixed time manager, the clock signal can be directly fanned out to the input pins of the corresponding switch capacitor array chips, so that fan-out equipment or devices with complex designs in the prior art are avoided, the device is simplified, and the complexity of time correction is reduced. In addition, the jitter of the clock signal processed by the mixed time manager is about 50ps and is smaller than that of signals generated by most signal generators, so that the accuracy of time correction can be further improved. Importantly, the rising edge time of the clock signal processed by the mixed time manager is short and is about 1ns, and the rising edge time is smaller than the rising edge time of signals generated by most signal generators, so that the time resolution can be improved, and the time correction precision can be improved.
Preferably, taking an Xilinx A7 series FPGA as an example, the hybrid time manager has a larger output frequency adjustable range, the maximum output clock frequency is 800MHz, the minimum output frequency is 4.69MHz, and the larger frequency adjustable range can meet the requirement of time correction of the switching capacitor array chip under different sampling frequencies. For example, when the current sampling rate of the switched capacitor array chip is 5GSPS, the time interval between adjacent sampling points is 0.2ns, and if each channel has 1000 sampling points, a waveform of 200ns can be obtained at a time, and although a period of 5MHz can be obtained, the frequency is lower, the sampling rate is reduced, so that the correction rate is affected, while the sampling frequency is too fast, the influence of the bandwidth and the timing method is also larger (for example, in the front edge timing, if the bandwidth cannot meet the requirement, the clock signal is distorted, and the timing time is affected), so that the time correction is not facilitated, and therefore, preferably, the output frequency range of the hybrid time manager is [100MHz,500MHz ], so that the time correction is performed.
Preferably, pins of each clock signal output channel in the FPGA are in communication connection with input pins of the corresponding switched capacitor array chip, and communication distances between the pins of each clock signal output channel and the input pins of the corresponding switched capacitor array chip are equal. By setting the communication distances equal, the waveform phases of the clock signals entering the corresponding switched capacitor array chips can be ensured to be consistent, and therefore the accuracy of time correction is improved.
Preferably, the on-line calculation of the digitized clock signal by using the FPGA corresponds to obtaining the timing time of each switched capacitor array chip, including:
the following steps are repeated to obtain the timing time of each switch capacitor array chip corresponding to the measurement sequence: simultaneously, each switch capacitor array chip is measured to obtain a digital clock signal corresponding to each switch capacitor array, and then the timing time corresponding to the current measurement sequence of each switch capacitor array chip is calculated. In other words, each switch capacitor array chip is measured at the same time, and the measurement is performed for a plurality of times, so as to obtain a plurality of timing times corresponding to the measurement sequence of each switch capacitor array chip.
Preferably, obtaining the correction coefficient of each switched capacitor array includes:
taking the timing time of any switch capacitor array chip corresponding to the measurement sequence as reference time; i.e. any switched capacitor array chip is used as a reference standard.
Aiming at the first switch capacitor array chip, according to the same measurement sequence, the corresponding timing time of the first switch capacitor array chip is differed from the corresponding timing time of any switch capacitor array chip, so as to obtain a plurality of time differences corresponding to the first switch capacitor array chip; the first switched capacitor array chip is each of the other switched capacitor array chips except any one of the switched capacitor array chips (i.e., the switched capacitor array chip serving as the reference).
And averaging a plurality of time differences of each first switched capacitor array chip to obtain a correction coefficient of each first switched capacitor array chip. Illustratively, the specific expression is as follows:
wherein c n A correction coefficient indicating the nth first switched capacitor array chip, n=1, 2, … N, N indicating the number of first switched capacitor array chips; t (T) ni Representing the corresponding timing time T of the ith measurement of the nth first switched capacitor array chip 0i The timing time at the ith measurement of any one of the switched capacitor array chips (i.e., the switched capacitor array chip as the reference standard) is represented, and m represents the total number of measurements.
Preferably, the method further comprises: and storing the correction coefficient of each switch capacitor array chip in a memory of the FPGA, and correspondingly automatically correcting the timing time of each switch capacitor array chip according to the stored correction coefficient. Specifically, in practical application, when a corresponding device (that is, the FPGA is connected to a plurality of switched capacitor array chips) is started, the timing time of the corresponding switched capacitor array chip can be automatically corrected according to the correction coefficient of each switched capacitor array chip stored in the memory, so that the efficiency of multi-channel timing time correction of the device in the application process is greatly improved.
Preferably, the FPGA performs on-line computation on the digital clock signal through a front edge timing algorithm to obtain the timing time of each switched capacitor array chip correspondingly, or the FPGA performs on-line computation on the digital clock signal through a digital constant ratio timing algorithm to obtain the timing time of each switched capacitor array chip correspondingly.
Device embodiment
Since the device embodiment and the method embodiment are based on the same working principle, reference may be made to the method embodiment described above for the repetition, and no further description is given here.
Another embodiment of the invention discloses a device for correcting time difference between switch capacitor array chips. As shown in fig. 3, the apparatus includes an FPGA and an analog-to-digital conversion circuit (ADC).
Specifically, the FPGA is in communication connection with the plurality of switched capacitor array chips, and is configured to fan out a plurality of clock signals with identical phases at the same time, and input the plurality of clock signals into the corresponding switched capacitor array chips respectively. Specifically, a clock signal output channel pin of the FPGA is in communication connection with any pin in each switched capacitor array chip.
Each switch capacitor array chip performs analog sampling on the received clock signal, and inputs the sampled clock signal into an analog-to-digital conversion circuit to perform analog-to-digital conversion to obtain a digital clock signal. The analog-to-digital conversion circuit is in communication connection with the FPGA, the digital clock signals are input into the FPGA, the FPGA carries out on-line calculation on the digital clock signals to correspondingly obtain the timing time of each switch capacitor array chip, and then the correction coefficient of each switch capacitor array is obtained, and the timing time of the corresponding switch capacitor array chip is corrected based on the correction coefficient.
Preferably, the pins of the clock signal output channels of the FPGA are in communication connection with any pin of the corresponding switched capacitor array chip, and the communication distances are equal.
In still another embodiment of the present invention, a storage medium configured for an FPGA is disclosed, for storing a firmware program, where a processor executes the firmware program to implement the foregoing method for correcting a time difference between switched capacitor array chips. The storage medium may be Random Access Memory (RAM), memory, read Only Memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art. The firmware program is a curing program generated by compiling a computer program, and can be cured into the erasable read-only memory (i.e. a storage medium), and in practical application, the FPGA can complete configuration only by reading the curing program configured in the erasable read-only memory, thereby implementing the foregoing method for correcting the time difference between the switched capacitor array chips.
Compared with the prior art, the method and the device for correcting the time difference between the switched capacitor array chips disclosed by the embodiment of the invention have the advantages that firstly, clock signals with consistent phases are generated through the FPGA, and meanwhile, the clock signals are directly input into a plurality of corresponding switched capacitor array chips for time correction, an additional signal generator is not needed, the flow is simplified, the human error is reduced, the correction precision and the correction efficiency are improved, and meanwhile, the time difference correction device is simplified. And secondly, by setting the communication distance between the pins of each clock signal output channel and the input pins of the corresponding switch capacitor array chip to be equal, the waveform phase of the clock signal entering the switch capacitor array chip is ensured to be consistent, thereby further improving the correction precision of the time difference. In addition, the method and the device for correcting the time difference between the switch capacitor array chips disclosed by the embodiment of the invention utilize the mixed time manager in the FPGA to adjust the phase of each clock signal, the jitter of the rising edge of the processed clock signal is smaller than that of the clock signal generated by most signal generators, and the rising edge time of the processed clock signal is smaller than that of the clock signal generated by most signal generators, so that the time resolution is improved, and the time difference correction precision between the chips can be further improved.
Those skilled in the art will appreciate that all or part of the above-described embodiment method flow may be implemented by hardware associated with firmware program instructions, where the firmware program may be compiled by a computer program and then cured in a readable storage medium. Wherein the readable storage medium is a magnetic disk, an optical disk, an erasable read-only memory, and the like.
The present invention is not limited to the above-mentioned embodiments, and any changes or substitutions that can be easily understood by those skilled in the art within the technical scope of the present invention are intended to be included in the scope of the present invention.
Claims (8)
1. A method for correcting time differences between switched capacitor array chips, comprising:
simultaneously fanning out a plurality of clock signals with consistent phases by using an FPGA, and respectively inputting the plurality of clock signals into corresponding switch capacitor array chips;
analog sampling is carried out on the received clock signals through each switch capacitor array chip, and digital clock signals are obtained after analog-to-digital conversion is carried out;
performing on-line calculation on the digital clock signal by using the FPGA to correspondingly obtain the timing time of each switched capacitor array chip, further obtaining a correction coefficient of each switched capacitor array, and correcting the timing time of the corresponding switched capacitor array chip based on the correction coefficient; wherein,
the step of performing on-line computation on the digitized clock signal by using the FPGA to obtain timing time of each switched capacitor array chip, includes: the following steps are repeated to obtain the timing time of each switch capacitor array chip corresponding to the measurement sequence: simultaneously measuring each switch capacitor array chip to obtain a digital clock signal corresponding to each switch capacitor array, and further calculating and obtaining timing time corresponding to the current measurement sequence of each switch capacitor array chip;
said further obtaining a correction factor for each of said switched capacitor arrays comprises:
taking the timing time of any switch capacitor array chip corresponding to the measurement sequence as reference time;
aiming at a first switch capacitor array chip, according to the same measurement sequence, the timing time corresponding to the first switch capacitor array chip is correspondingly differenced with the timing time corresponding to any switch capacitor array chip, so as to obtain a plurality of time differences corresponding to the first switch capacitor array chip; the first switched capacitor array chip is each switched capacitor array chip in other switched capacitor array chips except any switched capacitor array chip;
and averaging a plurality of time differences of each first switched capacitor array chip to obtain a correction coefficient of each first switched capacitor array chip.
2. The method for correcting time difference between switch capacitor array chips according to claim 1, wherein said simultaneously fanning out a plurality of clock signals with identical phases by using an FPGA comprises:
generating a clock signal corresponding to a clock signal output channel in the FPGA by utilizing the FPGA;
according to the delay difference of different clock signal output channels in the FPGA, the phase of the clock signal in each clock signal output channel is regulated and controlled by utilizing a mixed time manager in the FPGA, so that the phases of the clock signals output at the pins of each clock signal output channel are consistent.
3. The method according to claim 2, wherein pins of each clock signal output channel in the FPGA are communicatively connected to input pins of the corresponding switched capacitor array chip, and communication distances between pins of each clock signal output channel and input pins of the corresponding switched capacitor array chip are equal.
4. The method for correcting time difference between switched capacitor array chips as claimed in claim 1, further comprising:
and storing the correction coefficient of each switch capacitor array chip in a memory of the FPGA, and automatically correcting the timing time of each switch capacitor array chip according to the stored correction coefficient.
5. The method for correcting time difference between switch capacitor array chips according to claim 1, wherein said FPGA performs on-line computation on said digitized clock signal by a front-edge timing algorithm to obtain timing time of each of said switch capacitor array chips, or,
and the FPGA carries out on-line calculation on the digital clock signal through a digital constant ratio timing algorithm to correspondingly obtain the timing time of each switch capacitor array chip.
6. The device for correcting the time difference between the switch capacitor array chips is characterized by comprising an FPGA and an analog-to-digital conversion circuit;
the FPGA is in communication connection with the plurality of switch capacitor array chips, and is used for simultaneously fanning out a plurality of clock signals with consistent phases and respectively inputting the plurality of clock signals into the corresponding switch capacitor array chips;
each switch capacitor array chip performs analog sampling on the received clock signal, and the analog-to-digital conversion circuit performs analog-to-digital conversion on the signal obtained by the analog sampling to obtain a digital clock signal;
the FPGA carries out on-line calculation on the digital clock signals to correspondingly obtain the timing time of each switch capacitor array chip, so as to obtain the correction coefficient of each switch capacitor array, and corrects the timing time of the corresponding switch capacitor array chip based on the correction coefficient; wherein,
the FPGA performs on-line calculation on the digital clock signal to correspondingly obtain the timing time of each switched capacitor array chip, and the method comprises the following steps: the following steps are repeated to obtain the timing time of each switch capacitor array chip corresponding to the measurement sequence: simultaneously measuring each switch capacitor array chip to obtain a digital clock signal corresponding to each switch capacitor array, and further calculating and obtaining timing time corresponding to the current measurement sequence of each switch capacitor array chip;
said further obtaining a correction factor for each of said switched capacitor arrays comprises:
taking the timing time of any switch capacitor array chip corresponding to the measurement sequence as reference time;
aiming at a first switch capacitor array chip, according to the same measurement sequence, the timing time corresponding to the first switch capacitor array chip is correspondingly differenced with the timing time corresponding to any switch capacitor array chip, so as to obtain a plurality of time differences corresponding to the first switch capacitor array chip; the first switched capacitor array chip is each switched capacitor array chip in other switched capacitor array chips except any switched capacitor array chip;
and averaging a plurality of time differences of each first switched capacitor array chip to obtain a correction coefficient of each first switched capacitor array chip.
7. The device for correcting time difference between switch capacitor array chips according to claim 6, wherein the clock signal output channel pins of the FPGA are in communication connection with any one of the pins of the corresponding switch capacitor array chip, and the communication distances are equal.
8. A storage medium storing a firmware program, execution of which by a processor enables the correction method of the time difference between switched capacitor array chips of any one of claims 1 to 5.
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Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5043596A (en) * | 1988-09-14 | 1991-08-27 | Hitachi, Ltd. | Clock signal supplying device having a phase compensation circuit |
| US5734685A (en) * | 1996-01-03 | 1998-03-31 | Credence Systems Corporation | Clock signal deskewing system |
| CN101820261A (en) * | 2010-04-21 | 2010-09-01 | 广州市广晟微电子有限公司 | Device and method for correcting cut-off frequency of filter |
| CN102203597A (en) * | 2008-06-26 | 2011-09-28 | 生命技术公司 | Methods and apparatus for detecting molecular interactions using fet arrays |
| CN103762975A (en) * | 2014-01-17 | 2014-04-30 | 中国科学院上海技术物理研究所 | Time frequency synchronization calibration method of SCA-based multi-channel high-speed acquisition system |
| KR102106337B1 (en) * | 2018-12-28 | 2020-05-13 | 주식회사 엑시콘 | High-speed clock synchronization circuit for testing semiconductor device |
-
2021
- 2021-10-27 CN CN202111255715.8A patent/CN113985959B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5043596A (en) * | 1988-09-14 | 1991-08-27 | Hitachi, Ltd. | Clock signal supplying device having a phase compensation circuit |
| US5734685A (en) * | 1996-01-03 | 1998-03-31 | Credence Systems Corporation | Clock signal deskewing system |
| CN102203597A (en) * | 2008-06-26 | 2011-09-28 | 生命技术公司 | Methods and apparatus for detecting molecular interactions using fet arrays |
| CN101820261A (en) * | 2010-04-21 | 2010-09-01 | 广州市广晟微电子有限公司 | Device and method for correcting cut-off frequency of filter |
| CN103762975A (en) * | 2014-01-17 | 2014-04-30 | 中国科学院上海技术物理研究所 | Time frequency synchronization calibration method of SCA-based multi-channel high-speed acquisition system |
| KR102106337B1 (en) * | 2018-12-28 | 2020-05-13 | 주식회사 엑시콘 | High-speed clock synchronization circuit for testing semiconductor device |
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