KR102106337B1 - High-speed clock synchronization circuit for testing semiconductor device - Google Patents

Abstract

The present invention relates to a high-speed clock synchronization circuit for testing a semiconductor device using a MUX and a delay buffer and generating high-speed test signals synchronized with an FPGA so that the test time is reduced and a reliable test result can be obtained.

Description

High-speed clock synchronization circuit for testing semiconductor devices

This document relates to a test circuit of a semiconductor device, and particularly relates to a circuit that generates and accelerates a synchronous clock signal in a test device of a semiconductor device to transmit and receive test signals to and from the semiconductor device.

Generally, semiconductor devices are tested several times during the manufacturing process. In order to successfully test a semiconductor device, the test equipment must generate and measure the signal as it is in the device's operating environment. Semiconductor integrated circuit test equipment typically connects instrument boards mounted on a high-fix frame to a semiconductor device to transmit and receive test signals, using a divider (divider) or fanout buffer (FPGA) (Field Programmable Gate Array) and clock synchronization. However, the operating speed of a memory device of DDR4 or higher is usually about 1.6 Gbps to 4.0 Gbps, and in some cases, it can operate at a higher speed. Therefore, it is necessary for the test equipment to transmit signals at this speed and to receive test results. To this end, an expensive high-speed clock generator must be used, but the cost problem and the asynchronism problem become larger. In order to do this, it is necessary to design additional circuits that can achieve high-speed and precise synchronization within the instrument board.

Korean Patent Publication (Registration No .: 10-1794139, “Clock Synchronization Circuit System for Semiconductor Test”) is mounted on each of a plurality of instrument boards to receive signals output through the fan-out buffer and convert them to a synchronized frequency. A clock synchronization circuit using a plurality of frequency converters is disclosed, but a technique for generating test signals by synchronizing and simultaneously synchronizing test signals is not disclosed.

This document provides a synchronized high-speed clock signal that generates and transmits a synchronized high-speed clock signal for testing a device under test (DUT) such as a semiconductor device. It relates to a high-speed clock synchronous circuit, which aims to reduce test time, obtain reliable test results, and reduce costs.

A high-speed clock synchronization circuit for testing the semiconductor device 2000 according to an aspect for achieving this object,

In the high-speed clock synchronization circuit 1000 for testing the semiconductor device 2000,

Clock signal generator 100 for generating a digital clock signal,

A first fanout buffer 110 that receives a clock signal from the clock signal generator and forms and outputs a plurality of clock signals having the same frequency,

A first divider 120 that receives the clock signal from the first fan-out buffer and converts it to a lower frequency for output.

A second divider (130) that receives the clock signal from the first fan-out buffer and converts it to a lower frequency for output.

A first FPGA 140 that receives a clock signal from a first divider to control the execution operation of the second divider 130 and executes to generate an MSC address (Micro Sequencing Command Address) signal,

A second fanout buffer 150 that receives and outputs a clock signal from the first fanout buffer to form and output a plurality of clock signals having the same frequency,

A second FPGA 160 that receives the clock signal from the second divider and receives the MSC address signal from the first FPGA to generate a test pattern signal and a MUX reset signal.

A first delay buffer 170 that receives a clock signal from a second fanout buffer to generate a delayed MUX clock signal,

A test pattern signal multiplied at a higher frequency is generated by receiving a test pattern signal from the second FPGA, but the MUX clock signal of the first delay buffer and the MUX reset signal of the second FPGA ( MUX Reset (MUX, Multiplexer) 180 that executes to generate and output a test pattern signal synchronized with the second FPGA by receiving a signal, and

Driver 190 for receiving a test pattern signal from the MUX (MUX) and generating an analog test data signal to the semiconductor device,

It comprises.

The present invention generates a high-speed test pattern signal synchronized with an FPGA in a semiconductor device test device, provides it to a driver, and tests a semiconductor device to generate a synchronized high-speed signal pattern to shorten test time and obtain reliable test results. In addition, there is no need to use an expensive high-speed clock generator, thereby reducing costs.

1 is a diagram illustrating a high-speed clock synchronization circuit according to an embodiment.
2 is a diagram illustrating a timing signal waveform of a high-speed clock synchronization circuit according to an embodiment.

Hereinafter, the present invention will be described in detail so that those skilled in the art can easily understand and reproduce it through preferred embodiments described with reference to the accompanying drawings. In the description of the present invention, when it is determined that detailed descriptions of related known functions or configurations may unnecessarily obscure the subject matter of embodiments of the present invention, detailed descriptions thereof will be omitted. Terms used throughout the specification of the present invention are terms defined in consideration of functions in the embodiments of the present invention, and can be sufficiently modified according to the intention or custom of a user or operator, so the definition of these terms is general It should be made on the basis of the contents.

Also, the above-described and additional aspects of the invention will be apparent through the embodiments described below. It is to be understood that the features of the selectively described aspects or the selectively described embodiments in the present specification can be freely combined with each other, unless it is apparent that it is not technically contradictory to those skilled in the art, unless otherwise indicated in the drawings as a single integrated configuration. I understand.

Therefore, the configuration shown in the embodiments and drawings described in this specification is only one of the most preferred embodiments of the present invention and does not represent all of the technical spirit of the present invention, and thus can replace them at the time of application. It should be understood that there may be equivalents and variations.

1 is a diagram illustrating a high-speed clock synchronization circuit according to an embodiment. As shown, the high-speed clock synchronization circuit 1000 for testing the semiconductor device 2000, the clock signal generation unit 100, the first fan-out buffer (Fanout buffer) 110 for transmitting the test data signal , A first divider (120), a second divider (130), a first FPGA (140), a second fanout buffer (Fanout buffer) 150, a second FPGA ( 160), the first delay buffer (Delay buffer) 170, MUX (MUX) 180, and may include a driver (Driver) 190.

The semiconductor element 2000 may include both a memory element and a non-memory element as a device under test.

The clock signal generator 100 may generate a digital clock signal. A PLL (Phase Locked Loop) method may be applied to the clock signal generator. The clock signal generator 100 may receive a signal from an oscillator (not shown) outside the high-speed clock synchronization circuit 1000 to generate the clock signal.

The first fan-out buffer 110 may receive a clock signal from the clock signal generator and execute it to form and output a plurality of clock signals having the same frequency.

The first divider 120 may receive the clock signal from the first fan-out buffer, convert it to a lower frequency, and execute the output signal. 'Converting to a lower frequency' may mean frequency division by 1/2 or 1/4 or less.

The second divider 130 may receive the clock signal from the first fan-out buffer, convert it to a lower frequency, and execute the output signal. By 'converting to a lower frequency' may mean, for example, dispensing to 1/2 or 1/4 or less.

The first FPGA 140 may receive a clock signal from the first divider to control the execution operation of the second divider 130 and execute to generate an MSC address (Micro Sequencing Command Address) signal. FPGA (Field Programmable Gate Array) is a kind of programmable semiconductor device and can be programmed to perform various functions.

The second fan-out buffer 150 may receive a clock signal from the first fan-out buffer to form and output a plurality of clock signals having the same frequency.

The second FPGA 160 may receive a clock signal from a second divider and receive an MSC address signal from the first FPGA to generate a test pattern signal and a MUX reset signal. .

The first delay buffer 170 may receive a clock signal from the second fanout buffer to generate a delayed mux clock signal. There may be delays of several tens of nanoseconds. A plurality of first delay buffers 170 may be provided.

Mux (180, Multiplexer) receives a test pattern signal from a second FPGA to generate a test pattern signal multiplied by a higher frequency (Multiplication), the first delay buffer (Delay buffer) of the mux clock (MUX Clock) The signal and the MUX Reset signal of the second FPGA may be received to generate and output a test pattern signal synchronized with the second FPGA. The term 'multiplied by a higher frequency' may mean an increase in frequency by 2 times or 4 times or more. A plurality of mux 180 may be made of ASIC.

The driver 190 may receive a test pattern signal from MUX, generate an analog test data signal, and transmit it to a semiconductor device. The driver 190 may generate a data signal for testing a semiconductor device (DUT) and convert a digital signal into an analog signal. The driver 190 may be a plurality.

The high speed clock synchronization circuit 1000 for testing the semiconductor device 2000 according to an embodiment may include a comparator 200 and a second delay buffer (as shown in FIG. 1) for receiving a test result signal. Delay buffer (210), a third delay buffer (Delay buffer) 220, a third FPGA 230, may be configured to further include a demux (DEMUX, Demultiplexer) 240.

The comparator 200 may be executed to receive an analog test result signal of a semiconductor device, compare the signal size with a reference voltage, and convert it to a digital signal to output the signal. The comparator can output a combination signal of digital logic “0” and “1”. For example, a logic of “1” when the voltage is greater than the reference voltage and “0” when the voltage is smaller than the reference voltage may be output. The comparator 200 may be a plurality.

The second delay buffer 210 may be executed to generate a delayed clock signal by receiving a clock signal from the second divider. For example, the clock signal may be delayed by several tens of nanoseconds.

The third delay buffer 220 may be executed to receive a clock signal from the second fanout buffer and generate a delayed demux clock signal. The clock signal may be delayed by several to several tens of nanoseconds. The third delay buffer 220 may be a plurality. The third FPGA 230 receives the clock signal from the second delay buffer and receives the MSC address signal from the first FPGA 130 to generate a demux reset signal. Can be.

The demux (DEMUX) 240 receives a test result signal including phase difference information from a comparator to generate a test result signal divided at a lower frequency, but a demux clock (DEMUX) of a third delay buffer Clock) signal and the MUX Reset signal of the third FPGA may be received to form and output a test result signal synchronized with the third FPGA. In order to synchronize the signal of the comparator 200 and the demux clock signal, a demux reset signal may be applied to the third FPGA 230. The demux 240 may be plural and may be made of ASIC.

Here, the third FPGA 230 compares the predicted pattern data result signal generated by receiving the test result signal of Demux (DEMUX) and the MSC address signal of the first FPGA to pass or fail the semiconductor device. (Defective products) can be further implemented to store information. Therefore, the user can access the information stored in the third FPGA 230 using the Main PC. The third FPGA 230 may be composed of a random access memory (RAM) and a hard disk, but is not limited thereto.

2 is a diagram illustrating a timing signal waveform of a high-speed clock synchronization circuit according to an embodiment. As shown, the output signal waveform of each component of FIG. 1 can be illustrated over time. The MUX outputs a high-speed signal synchronized with the first fan-out buffer output, and the demux (DEMUX) also A low-speed signal synchronized with MUX was output.

2000: semiconductor device
1000: high-speed clock synchronization circuit
100: clock signal generator
110: first fanout buffer (Fanout buffer)
120: first divider
130: second divider
140: first FPGA
150: second fanout buffer
160: second FPGA
170: first delay buffer (Delay buffer)
180: MUX
190: Driver
200: Comparator
210: second delay buffer (Delay buffer)
220: third delay buffer (Delay buffer)
230: Third FPGA
240: Demux

Claims (2)

In the high-speed clock synchronization circuit for testing a semiconductor device,
A clock signal generator for generating a digital clock signal;
A first fanout buffer configured to receive and output a clock signal from the clock signal generator to form and output a plurality of clock signals having the same frequency;
A first divider configured to receive the clock signal from the first fan-out buffer and convert it to a lower frequency for output;
A second divider configured to receive the clock signal from the first fan-out buffer and convert it to a lower frequency for output;
A first FPGA that receives a clock signal from a first divider to control execution of the second divider and executes to generate an MSC address (Micro Sequencing Command Address) signal;
A second fanout buffer configured to receive and output a clock signal from the first fanout buffer to form and output a plurality of clock signals having the same frequency;
A second FPGA that receives the clock signal from the second divider and receives the MSC address signal from the first FPGA to generate a plurality of test pattern signals and a MUX reset signal;
A first delay buffer configured to receive the clock signal from the second fanout buffer and generate a delayed MUX clock signal;
It is composed of a plurality of, and receives a test pattern signal from the second FPGA to generate a high-speed test pattern signal multiplied by a higher frequency, but the MUX Clock signal and the first Delay buffer (Delay buffer) A MUX for receiving a MUX Reset signal of the FPGA of 2 and generating and outputting a test pattern signal synchronized with the second FPGA; And
A driver that receives a test pattern signal from MUX and generates an analog test data signal and transmits it to a semiconductor device;
High-speed clock synchronization circuit comprising a. According to claim 1,
A comparator that receives a signal from an analog test result of a semiconductor device, compares the signal size with a reference voltage, converts it into a digital signal, and outputs the converted signal;
A second delay buffer configured to receive the clock signal from the second divider and generate a delayed clock signal;
A third delay buffer configured to receive the clock signal from the second fanout buffer and generate a delayed demux clock signal;
A third FPGA configured to receive the clock signal from the second delay and receive the MSC address signal from the first FPGA to generate a demux reset signal; And
A plurality of low-speed test result signals divided into lower frequencies are generated by receiving a test result signal including phase difference information from a comparator, and the demux of a third delay buffer is generated. It further includes a demux (DEMUX) that receives a clock (DEMUX Clock) signal and a MUX Reset signal of a third FPGA to form and output a test result signal synchronized with the third FPGA.
The third FPGA is a high speed that executes further to store Pass or Fail information of a semiconductor device by comparing the test result signal of Demux with the expected pattern data result signal generated by receiving the MSC address signal of the first FPGA. Clock synchronization circuit.

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