JPH0530770U - Digital oscilloscope - Google Patents

Abstract

(57) [Summary] (Modified) [Purpose] Realization of a digital oscilloscope equipped with a signal generation circuit that generates sampling pulses that are not dependent on the internal clock. A clock generation circuit 1, a switching means 2 for selecting and outputting a signal from the outside or a signal from the clock generation circuit 1, and a frequency of an output from the switching means 2 are counted,
A frequency detection circuit 32 that outputs the result as a signal,
From the control type oscillation circuit 31, the first frequency division circuit 33 which divides the frequency of the signal from the control type oscillation circuit 31 by the signal from the control signal, the signal from the switching means and the first frequency division circuit 33. A phase comparator 34 that inputs the signal of FIG. 2 and outputs the phase difference between them as a signal, and a control type oscillation circuit 31 that inputs the signal from the phase comparator 34 and outputs a signal of a frequency corresponding to this A digital oscilloscope provided with a signal generation circuit including a frequency divider circuit 4 for dividing and outputting a signal from an oscillation circuit 31.

Description

[Detailed description of the device]

[0001]

[Industrial applications]

 The present invention relates to a digital oscilloscope, and more particularly, to a digital oscilloscope provided with a signal generation circuit that generates a sampling pulse that determines a timing when sampling is performed at an arbitrary frequency.

[0002]

[Prior Art]

 Conventionally, when sampling with a digital oscilloscope, the clock output from the internal oscillator was divided or the timing of the signal from the outside was used. For example, when sampling one cycle of a repetitive sine wave having a certain frequency at the timing of 1/500 of the period, the timing of dividing the clock output from the built-in oscillator is It is not always synchronized with the input signal. In addition, when sampling is performed at the timing of an external signal, that is, when sampling is performed at the timing of the trigger signal, the trigger signal is generated once per cycle. It is difficult to perform sampling at a timing of 1/500 of.

[0003]

[Problems to be solved by the device]

 Therefore, the digital oscilloscope with this configuration cannot perform sampling at an arbitrary frequency. The present invention is intended to solve the above problems, and to realize a signal generation circuit necessary to realize a digital oscilloscope capable of performing sampling at an arbitrary frequency. is there.

[0004]

[Means for Solving the Problems]

 In order to solve such problems, the present invention samples the signal to be measured with a sampling pulse, sets the frequency division ratio, etc. in the digital oscilloscope that observes the electrical signal as a waveform, and Control means for controlling, a clock generation circuit for generating a clock, a switching means for selecting and outputting an external clock or a clock from the clock generation circuit by a signal from the control means, and an output from the switching means. Frequency detection circuit that counts the frequency and outputs the result as a frequency value signal, and divides and outputs the input clock. The frequency division ratio is the first frequency division determined by the setting from the control means. A circuit, a phase comparator for inputting a signal from the switching means and a signal from the first frequency dividing circuit, and outputting a phase difference between them as a phase difference signal; A phase difference signal from a comparator is input, an oscillation pulse signal having a frequency corresponding to this is output, and this oscillation pulse signal is output to a first frequency dividing circuit. The frequency division ratio changes depending on the setting from, and it has a second frequency divider circuit that divides and outputs the signal from the controlled oscillation circuit. The frequency value signal from the frequency detection circuit and the control from the control means The digital oscilloscope is characterized by being provided with a signal generation circuit that generates a sampling pulse for sampling at an arbitrary frequency synchronized with a desired cycle.

[0005]

[Action]

 Since a synthesizer that uses a frequency divider circuit is built in to generate the sampling pulse, it is possible to generate a sampling pulse for sampling at any frequency, and a sampling pulse for sampling at any frequency. Can occur.

[0006]

【Example】

 The present invention will be described in detail below with reference to the drawings. FIG. 1 shows the configuration of the digital oscilloscope of the present invention. In the figure, 11 is an attenuator for inputting an observation signal. An amplifier 12 receives the signal from the attenuator 11 and outputs a signal obtained by normalizing the amplitude of the observed signal. A sample and hold circuit 13 is a signal from the signal generating circuit 19, which samples the amplitude value of the signal input from the amplifier 12. Reference numeral 14 is an A / D converter, which inputs the amplitude value of the analog signal sampled by the sample hold circuit 13 and performs A / D conversion. This timing is determined by the signal from the signal generating circuit 19. Reference numeral 15 is a waveform memory which stores the digital value output from the A / D converter 14. A data processor 16 converts the data to be displayed among the digital values stored in the waveform memory 15 into display data. A display 17 displays the output from the data processor 16. The trigger circuit 18 detects the reference timing of the observed waveform to be displayed and outputs it to the control means 20. The signal generation circuit 19 corresponds to the main part of the present invention, and generates an arbitrary sampling pulse by setting from the control means 20. The control means 20 controls the attenuation rate of the attenuator 11, the amplification rate of the amplifier 12, the input / output of the address and data of the memory 15, the data processor 16, and sets the trigger circuit 18 and the signal generation circuit 19. It also controls the entire measuring instrument.

In the digital oscilloscope having such a configuration, the input observation signal is input to the sample hold circuit 13 after its amplitude is normalized via the attenuator 11 and the amplifier 12. At this time, the signal generating circuit 19 outputs the timing signal S. This signal S means a sampling pulse and is output to the sample hold circuit 13, the A / D converter 14 and the control means 20. At this timing, the observation signal is converted into a digital value as data for waveform display, It is stored in the memory 15. At this time, the control means 20 selects whether the sampling pulse generated by the signal generation circuit 19 is synchronized with the clock generated in the digital oscilloscope or is synchronized with the external clock, and is selected appropriately. Sampling is performed at any frequency by setting a different multiplication rate or frequency division rate.

FIG. 2 is a diagram showing the configuration of the signal generating circuit 19 which is the main part of the present invention. In the figure, 1 is a clock generation circuit, which is simply realized by an oscillator or the like to generate a clock. Reference numeral 2 denotes a switching means, such as a switch, which selects and outputs the signal from the external clock (E) or the clock generation circuit 1 by the signal from the control means 20. A synthesizer 3 is composed of a control type oscillation circuit 31, a frequency detection circuit 32, a frequency dividing circuit 33 (the frequency dividing ratio is D1), and a phase comparator 34. The frequency dividing circuit is a signal from the control means 20. A pulse signal having a period D2 times as long as the sampling pulse output from 4 (divided frequency is D2) is generated. The frequency dividing circuit 4 (frequency dividing rate D2) divides the pulse signal from the synthesizer 3 by setting the control means 20 and outputs it as a sampling pulse. The control means 20 sets the frequency and controls the operation. The control means 20 is specifically realized by a CPU or the like. The frequency detection circuit 32 inputs the signal from the switching means 2, counts this frequency and outputs it to the control means 20. The frequency dividing circuit 33 determines the frequency dividing rate according to the setting from the control means 20, divides the pulse signal from the control type oscillation circuit 31 by this frequency dividing rate (D1 times), and outputs it to the phase comparator 34. The phase comparator 34 inputs the output from the frequency dividing circuit 33 and the signal from the switching means 2, compares the phase differences between them, and outputs them as a signal. The controlled oscillation circuit 31 outputs a pulse signal having a frequency determined by the setting from the control means 20 to the frequency dividing circuit 4 as an output from the synthesizer 3. Further, in this control type oscillation circuit 31, the signal from the phase comparator 34 is input and the phase of the output of the pulse signal is controlled.

The operation of the signal generating circuit having such a configuration will be specifically described. At this time, the controlled oscillation circuit 31 is realized by a VCO (voltage controlled oscillator), and the frequency detection circuit 32 is realized by an F / V converter. Further, it is assumed that the control type oscillation circuit 31 can output a clock of 100 MHz to 10 MHz, and a repetitive signal having a frequency of about 1 KHz is input to the input signal. At this time, the switching means 2 is selected to input the external clock (E), and it is desired to perform sampling at 500 points in one cycle of the input signal. In this embodiment, a PLL (phase locked loop) is composed of the controlled oscillator circuit 31, the frequency divider circuit 33, and the phase comparator 34, and the operation is based on the PLL operation. When the frequency dividing ratio D1 of the frequency dividing circuit 33 is 1 / 50,000 times, the oscillation circuit 31 oscillates at 50,000 times the input frequency, that is, 50 MHz. Further, if the frequency dividing ratio of the frequency dividing circuit 4 is 100 times, a sampling clock of 500 times the input frequency (equal to the frequency of the external clock (E)) can be obtained accurately. The above can be expressed in the following formula when the sampling clock frequency is fs and the frequency of the input signal (external clock (E)) is fi. fs = D1 × fi / D2 (however, 10 MHz <D1 × fi <100 MHz) That is, it is understood that fs can be obtained as an arbitrary sampling clock frequency by changing the frequency division ratios D1 and D2. Further, fi is the same as the frequency of the input signal (external clock (E)) or the clock from the clock generation circuit 1 only by switching the switching means 2.

[0010]

[Effect of the device]

 As described above in detail, according to the present invention, a synthesizer is built in, and by setting the internal frequency dividing circuit and the external frequency dividing circuit, sampling pulses for sampling at arbitrary timing can be obtained. It is possible to realize a signal generation circuit that generates the signal.

[Brief description of drawings]

FIG. 1 is a configuration diagram of a first main part of the present invention.

FIG. 2 is a block diagram of the present invention.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 clock generation circuit 2 switching means 3 synthesizer 4, 33 frequency dividing circuit 20 control means 31 controlled oscillation circuit 32 frequency detection circuit 34 phase comparator 35 frequency multiplication circuit

Claims (1)

[Scope of utility model registration request] 1. A digital oscilloscope for sampling a signal to be measured with a sampling pulse and observing the electric signal as a waveform, setting a frequency division ratio and the like, and generating a clock and a control means for controlling the operation. A clock generating circuit, a switching means for selecting and outputting an external clock or a clock from the clock generating circuit by a signal from the control means, and counting the frequency of the output from the switching means, and the result is the frequency value. A frequency detection circuit for outputting as a signal, an input clock is frequency-divided and output, and a frequency division ratio thereof is determined by a setting from the control means, a first frequency division circuit, a signal from the switching means and a first frequency division circuit. A phase comparator that inputs the signal from the frequency divider circuit and outputs the phase difference between them as a phase difference signal, and the phase difference signal from the phase comparator is input. , An oscillation pulse signal having a frequency corresponding to this is output, and the oscillation pulse signal is controlled by the control type oscillation circuit output to the first frequency dividing circuit, and the frequency division ratio is changed by the setting from the control means. It has a second frequency dividing circuit for frequency-dividing and outputting a signal from the control type oscillation circuit, and sampling at an arbitrary frequency synchronized with a desired cycle by the frequency value signal from the frequency detecting circuit and control by the control means. A digital oscilloscope provided with a signal generation circuit for generating a sampling pulse for performing.