JPH06187166A - Interruption control system for transmitter - Google Patents

Abstract

PURPOSE:To provide an interruption control system of a transmitter made possible accurately recognizing by a CPU the time when each interruption is generated when plural numbers of the interruption are simultaneously generated. CONSTITUTION:In the interruption control system of the transmitter provided with an interruption control part 500 and the CPU 120, plural clock circuits (900-1-900-n) provided for the number corresponding at least to the input of plural interruption signals for normally operating as regular clocks, stopping an operation as the corresponding clocks when the plural interruption signals are inputted and restarting the operation as the clocks by control signals from the CPU 120 based on the time of completion when a prescribed processing for the interruption signals is completed at the CPU 120 are added to the interruption control part 500 and the generation time of the respective interruption signals is recognized at the CPU 120 by the time when the clock circuits 900-1-900-n are stopped.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to improvement of an interrupt control system for a transmission device.

[0002]

2. Description of the Related Art FIG. 6 is a circuit diagram of a conventional interrupt controller. FIG. 7 is a time chart for explaining the operation of the conventional example.

In FIG. 6, the interrupt request register 1 has, for example, eight input terminals, and three interrupt signals (1) (IRQ ₁ ) to (3) (IRQ ₃ ) are simultaneously input to the input terminals. The case where it is performed will be described. The priority order determination unit 2 recognizes this, and the priority order is determined by the interrupt signal data to be masked stored in the interrupt mask register 3. For example, the priority is interrupt signal (1)
> Interrupt signal (2)> Interrupt signal (3), the priority determination unit 2 first determines that an interrupt has occurred for the interrupt signal (1) (INT) via the control unit 5 by the CPU.
Notify (not shown) and interrupt signal (1)
Data is transferred to the in-service register 4 and temporarily stored.

A read control signal from the read / write control unit 6 reads the data of the interrupt signal (1) stored in the in-service register 4, and a CPU (not shown) via the internal bus and data bus interface unit 7
Transfer to. Interrupt signal in CPU (not shown)
In addition to recognizing (1), the time of occurrence of the interrupt signal (1) is recognized as the recognized time T ₁ . And CPU
(Not shown) processes the data of the interrupt signal (1), and when completed, notifies the control unit 5 of the completion of the interrupt signal (1) (INTA), and the control unit 5 controls the interrupt mask register 3 The interrupt signal (1) is cleared (see Fig. 7).

Next, the priority order determining section 2 issues an interrupt signal.
Notify the occurrence of (2) to the CPU (not shown),
The CPU (not shown) recognizes the interrupt signal (2) and also recognizes the generation time of the interrupt signal (2) as the recognized time T ₂ . Then, when the CPU (not shown) completes the processing of the data of the interrupt signal (2), the interrupt signal is generated by the interrupt mask register 3.
Clear (2).

Similarly for the interrupt signal (3), C
When the PU (not shown) recognizes the interrupt signal (3)
Also, when the occurrence time of the interrupt signal (3) is recognized
Tick T₃ Recognize as. And CPU (not shown)
When the processing for the interrupt signal (3) is completed with
Clear the interrupt signal (3) by using the mask mask register 3.
(See FIG. 7).

When the occurrence of an interrupt in the CPU is recorded as a log, the interrupt signal (1)
The time of occurrence of the interrupt signal is recorded as a time T ₁ which is almost equal to the time of the actual interrupt, but the time of occurrence of the interrupt signal (2) or (3) is the time T when the CPU recognizes them.
_It is recorded as ₂ or T ₃ . As a result,
When a plurality of interrupts are generated at the same time, there is a drawback that the CPU cannot accurately recognize the generation time of the interrupt having a low priority.

[0008]

As described above, conventionally, when a plurality of interrupts occur at the same time, there is a problem that the CPU cannot accurately recognize the time of occurrence of an interrupt having a low priority.

Therefore, it is an object of the present invention to provide an interrupt control system for a transmission apparatus in which the CPU can accurately recognize the time when each interrupt occurs when a plurality of interrupts occur simultaneously.

[0010]

The above problems can be solved by the circuit configuration shown in FIG. 1 or 2. In FIG. 1, a priority order of a plurality of interrupt signal inputs is determined and an interrupt control unit 500 that transfers the interrupt signals to the CPU in accordance with the priority order, and an occurrence time of the interrupt signal transferred from the interrupt control unit are recognized and predetermined. CP that processes
In the interrupt control method of the transmission device having U120, at least the number corresponding to the plurality of interrupt signal inputs is provided, and normally operates as a regular clock, and when the plurality of interrupt signals are input, the corresponding clock is used. When the operation is stopped and the CPU completes a predetermined process for the interrupt signal, the C
A plurality of clock circuits 900-1 to 900-n which resume the operation as a clock by a control signal from the PU are added to the interrupt control unit.

The CPU 120 recognizes the generation time of each interrupt signal based on the time when the clock circuit stops. In FIG. 2, an interrupt control unit 500 that determines the priority order of a plurality of interrupt signal inputs and transfers the interrupt signals to the CPU in accordance with the priority order, and recognizes the generation time of the interrupt signal transferred from the interrupt control unit and determines a predetermined value. In the interrupt control system of the transmission device having the CPU 120 for performing the processing of 1, the standard clock circuit 100 that operates as a regular clock and the number corresponding to at least the plurality of interrupt signal inputs are provided, and normally operate as a regular clock. However, when the plurality of interrupt signals are input, the operation of the corresponding timepiece is stopped, and when the CPU completes a predetermined process for the interrupt signal, the control signal from the CPU is used to determine the time based on the time of the standard clock circuit. Clock circuits 900-1 to 900-n that resume operation as a clock
To the interrupt control unit.

Then, the CPU 120 recognizes the generation time of each interrupt signal according to the stop time of the clock circuit.

[0013]

In FIG. 1, when the plurality of interrupt signals are input, the operation of the corresponding clock circuit among the plurality of clock circuits 900-1 to 900-n is stopped. And C
When the PU 120 sequentially performs a predetermined process on each interrupt signal, the generation time of the corresponding interrupt signal is recognized from the time when the clock circuit stops.

As a result, when a plurality of interrupts occur simultaneously, the CPU can accurately recognize the time when each interrupt occurs. The case of FIG. 2 is similar to the case of FIG. 1 described above.

[0015]

FIG. 3 is a circuit diagram of an interrupt controller according to the first embodiment of the present invention. FIG. 4 is a time chart for explaining the operation of the embodiment.

FIG. 5 is a circuit diagram of an interrupt controller according to the second and third embodiments of the present invention. In FIG.
As in the case of the conventional example, the interrupt request register 1 has, for example, eight input terminals to, and three interrupt signals (1) (IRQ ₁ ) to (3) (IRQ ₃ ) are simultaneously input to the input terminals. The case of input will be described. Priority decision unit 2
This is recognized and the priority order is determined by the interrupt signal data to be masked stored in the interrupt mask register 3. For example, if the priority order is interrupt signal (1)> interrupt signal (2)> interrupt signal (3), the priority determination unit 2 first informs the control unit 5 that an interrupt has occurred for the interrupt signal (1) (INT). The CPU (not shown) is notified via this, and the data of the interrupt signal (1) is transferred to the processing service register 4 and temporarily stored.

At the same time, the interrupt request register 1 notifies the newly provided clock control unit 8 that a plurality of interrupt signals (1) to (3) have been simultaneously input. The clock control unit 8 recognizes this and newly provided clock circuit for IRQ ₁
The clocking operations of 9-1, IRQ ₂ clock circuit 9-2, and IRQ ₃ clock circuit 9-3 are stopped at the same time. Clock circuit for IRQ ₁ 9-1 ~ IR
When the clock circuit for Q ₈ 9-8 is composed of, for example, a counter, the counting operation of the counters corresponding to 9-1 to 9-3 is stopped. As a result, IRQ ₁ clock circuit 9-1 to IRQ ₃ clock circuit 9-
3 stops at this time T ₁ (see FIG. 4).

On the other hand, the CPU (not shown) recognizes the data of the interrupt signal (1) read from the in-process register 4 by the read / write control unit 6 and generates the interrupt signal (1) at the time T _1. Is recognized by the IRQ ₁ clock circuit 9-1 described above. Then, the CPU (not shown) processes the data of the interrupt signal (1) and, when completed, notifies the control unit 5 of the completion of the interrupt signal (1) (INTA), and the control unit 5 sets the interrupt mask register 3 Control and clear the interrupt signal (1). At the same time C
PU to set the time at which clears the interrupt signal by the clock circuit having in (not shown) (1) to IRQ ₁ timepiece circuit 9-1, restarts the timing operations for IRQ ₁ clock circuit 9-1.

Next, the priority order determining unit 2 causes an interrupt signal.
The occurrence of (2) is notified to the CPU (not shown) via the control unit 5, and the CPU (not shown) recognizes the interrupt signal (2), and the generation time of the interrupt signal (2) is described above. It is recognized as T ₁ by the IRQ ₂ clock circuit 9-2. Then, an interrupt signal (2) is generated by the CPU (not shown).
When the processing for the data of 1 is completed, the interrupt signal (2) is cleared by the interrupt mask register 3. At the same time the CPU sets the time in which to clear the interrupt signal (2) by the clock circuit having in (not shown) to the IRQ ₂ for clock circuit 9-2, restarts the timing operations for IRQ ₂ clock circuit 9-2.

Similarly for the interrupt signal (3), the CPU
The interrupt signal (3) is recognized (not shown), and the time at which the interrupt signal (3) is generated is recognized as T ₁ by the IRQ ₃ clock circuit 9-3 described above. Then, when the CPU (not shown) completes the processing for the data of the interrupt signal (3), the interrupt mask (3) is cleared by the interrupt mask register 3. At the same time, the time when the interrupt signal (3) is cleared by the clock circuit in the CPU (not shown) is set in the IRQ ₃ clock circuit 9-3, and the IRQ ₃ clock circuit is set.
Restart the timing operation of 9-3. The above operation is shown in a time chart in FIG. The above-mentioned operation is 3 interrupt signals
It is needless to say that the present invention is not limited to (1) to (3), and holds for n interrupt signals (1) to (n).

As a result, when a plurality of interrupts occur at the same time, the CPU can accurately recognize the time at which each interrupt occurred. Next, a second embodiment of the present invention will be described. The difference from the above-described first embodiment is that FIG.
As shown in FIG. 7, a standard clock circuit 10 is added to the configuration of the first embodiment, and when the CPU completes the interrupt processing and clears the interrupt signal, the corresponding IRQ that was stopped at the same time as the interrupt The time of the clock circuit for use is reset to the time of the standard clock circuit 10 according to an instruction from the CPU.

That is, when a plurality of interrupt signals (1) to (3) are simultaneously input to the priority order determining unit 2, the timepiece control unit 8 outputs I.
The clock operation of the RQ ₁ clock circuit 9-1 to IRQ ₃ clock circuit 9-3 is stopped at the same time, and these clock circuits stop at this time T ₁ . Next, in the priority order determining unit 2, first, the interrupt signal (1)
To the CPU (not shown) that the
At U (not shown), the interrupt signal (1) is recognized, and the generation time of the interrupt signal (1) is recognized as T ₁ by the IRQ ₁ clock circuit 9-1 described above. Then, when the CPU (not shown) completes the processing of the data of the interrupt signal (1), it notifies the control unit 5, and the control unit 5 controls the interrupt mask register 3 to interrupt the signal (1).
To clear.

At the same time, when a signal for instructing the restart of the IRQ ₁ timepiece circuit 9-1 is sent from the CPU (not shown) to the timepiece control section 8, the timepiece control section 8 uses the current time of the standard timepiece circuit 10 for IRQ ₁ . Set the clock circuit 9-1 to the IRQ ₁ clock circuit 9-1.
Restarts the timing operation of. The interrupt signal (2) and interrupt signal (3) are generated in the same way.

Next, a third embodiment of the present invention will be described. In the third embodiment, a restart instruction section 11 (hardware) is additionally provided in the control section 5 as shown by the dotted line in FIG. When the CPU (not shown) notifies the control unit 5 when processing of the data of the interrupt signal (1) is completed, the control unit 5 controls the interrupt mask register 3 to clear the interrupt signal (1) and The restart instruction section 11 is driven to output a signal for instructing the restart of the IRQ ₁ timepiece circuit 9-1 to the timepiece control section 8. In the clock control unit 8, the current time of the standard clock circuit 10 is set to the clock circuit for IRQ ₁ .
Set it to 9-1 and restart the clock operation of IRQ ₁ clock circuit 9-1. The same applies to the interrupt signal (2) and interrupt signal (3).

As a result, the procedure of sending the restart instruction signal from the CPU to the timepiece control unit 8 as in the second embodiment can be omitted.

[0026]

As described above, according to the present invention, when a plurality of interrupt signals are input, the operation of the corresponding clock circuit as a clock is stopped, and each interrupt is generated at the time when this clock circuit is stopped. The CPU can accurately recognize the time.

[Brief description of drawings]

FIG. 1 is a principle diagram of the invention of claim 1,

2 is a principle diagram of the invention of claim 2, FIG.

FIG. 3 is a circuit configuration diagram of an interrupt controller according to a first embodiment of the present invention,

FIG. 4 is a time chart for explaining the operation of the embodiment,

FIG. 5 is a circuit configuration diagram of an interrupt controller according to a second / third embodiment of the present invention,

FIG. 6 is a circuit configuration diagram of a conventional interrupt controller,

FIG. 7 is a time chart for explaining the operation of the conventional example.

[Explanation of symbols]

Reference numeral 100 is a standard clock circuit, 120 is a CPU, 500 is an interrupt control unit, and 900-1 to 900-n are a plurality of clock circuits.

Claims (2)

[Claims] 1. A priority order of a plurality of interrupt signal inputs is determined and the interrupt signals are sent to a CPU according to the priority order.
In the interrupt control method of the transmission device, the interrupt control unit (500) for transferring to the device and the CPU (120) for recognizing the generation time of the interrupt signal transferred from the interrupt control unit and performing a predetermined process, A plurality of interrupt signal inputs are provided, which normally operate as a regular clock. When the plurality of interrupt signals are input, the corresponding clock operation is stopped, and the CPU responds to the interrupt signals. When a predetermined process is completed, a plurality of clock circuits (900-1 to 900-n) for restarting the operation as the clock by the control signal from the CPU based on the completed time are added to the interrupt control unit. An interrupt control system for a transmission device, wherein the CPU recognizes the time of occurrence of each interrupt signal based on the time when the clock circuit stops. 2. A priority order of a plurality of interrupt signal inputs is determined, and the interrupt signals are sent to the CPU according to the priority order.
In the interrupt control method of the transmission device, which includes an interrupt control unit (500) for transferring to the CPU and a CPU (120) for recognizing the generation time of the interrupt signal transferred from the interrupt control unit and performing a predetermined process, A standard clock circuit (100) that operates as a clock, and at least a number corresponding to the plurality of interrupt signal inputs are provided, normally operate as a regular clock, and when the plurality of interrupt signals are input, the corresponding clock A plurality of clock circuits that stop the operation of the clock and resume the operation as the clock based on the time of the standard clock circuit by the control signal from the CPU when the CPU completes a predetermined process for the interrupt signal. (900-1 to 900-n) is added to the interrupt control unit, and the CPU recognizes the generation time of each interrupt signal based on the stop time of the clock circuit. Interrupt control method of a transmission apparatus according to claim.