KR100856259B1 - Apparatus and method for providing redundancy in the processor board using programmable logic device with interrupt - Google Patents

Abstract

end. FIELD OF THE INVENTION The present invention relates to an apparatus and method for implementing processor board redundancy.

I. The present invention provides an apparatus and method for implementing redundancy by providing an PLD that delivers an interrupt source to not only the first processor board but also the second processor board using interrupts.

All. Summary of the Invention The present invention provides a method for implementing redundancy of a processor board using interrupts, the process in which two boards are mounted and ready for redundancy, a process in which a board mounted first starts an active operation, Passing the generated event to the standby second processor board through the backplane, passing the IRQ of the generated event to the processor after the active operation, and the processor reads a register value in the PLD. It is characterized in that it consists of a process of detecting what happened, and after the determination process, the processor performs the ISR for each bit and is redundantly switched to operate the active board in a standby state.

la. Important use of the invention: Applied to redundancy of processor boards using interrupts.

Interrupts, processors, PLDs, PLD registers, ISRs, backplanes, power resets,

Description

 Programmable logic devices that perform interrupts and processor board redundancy devices and methods using the same {APPARATUS AND METHOD FOR PROVIDING REDUNDANCY IN THE PROCESSOR BOARD USING PROGRAMMABLE LOGIC DEVICE WITH INTERRUPT}             

 1 is a block diagram of a conventional interrupt control scheme for an interrupt processor.

 2 is a block diagram of a processor board redundancy implementation for performing an interrupt according to an embodiment of the present invention.

 3 is an internal logic diagram of the programmable logic device shown in FIG.

 4 is an example diagram of a register address bit inside the PLD shown in FIG.

5 is a redundant implementation process flow diagram according to an embodiment of the present invention.

 The present invention relates to a redundant implementation of a processor board, and more particularly, to an apparatus and method for a processor to read and duplicate a register value in a programmable logic device (hereinafter referred to as "PLD") using one interrupt. will be.

 Typical interrupt usage uses an interrupt request controller, which has the ability to deliver an interrupt source to one processor. To implement this functionality, the processor is connected to the interrupt controller via a local bus using separate processor interface logic.

 Referring to FIG. 1, in the conventional interrupt control apparatus, the interrupt request controller 120 temporarily stores an interrupt request signal 140 that is externally input, and an interrupt control register (which allows a processor to perform a read and write function). 121). The interrupt request controller 120 notifies the processor 100 of an interrupt signal external to the processor, and is connected to the processor interface 110 through the local bus 141. The interrupt request controller 120 includes an interrupt control register 121 to control driving and withdrawal of the interrupt signal, and the interrupt control register includes information related to interrupt control. The processor interface 110 is a control circuit that serves as an interface between the processor and the interrupt request controller. The processor interface 110 is connected to the processor 100 through the processor external bus 142 and to the interrupt request controller through the local bus 141. It is. Hereinafter, the processing flow will be described.

 The interrupt control register includes a request bit stream (not shown) for storing the interrupt request signal 140 input externally for each bit according to an event (not shown), and a bit stream transmitted to the processor as bits set in the request bit stream. (Not shown). Next, the processor determines whether a request bit string is set in the interrupt control register. If the request bit string is set as a result of the determination, the driving bit string of the interrupt control register is set, and the interrupt request controller sends an interrupt request signal to the processor. The interrupt request controller transmits the type of interrupt requested by the processor to the interrupt response controller 130. When the interrupt response complete signal 131 is received from the interrupt response controller, the process returns to the start step of determining whether to set the request bit string in the interrupt control register.

As described above, the conventional interrupt control method is impossible to implement redundancy since the interrupt controller transmits the interrupt signal to only one processor, and the processor is connected to the interrupt controller through the local bus using a separate processor interface, thereby improving system performance. There was a problem of decreasing efficiency.

 Accordingly, an object of the present invention is to solve the problems of the prior art, the processor accesses the interrupt signal directly through the processor bus to read and write the register, there is logic to transfer the interrupt signal to the second processor board as well as the first processor board. To provide a redundant implementation.

To this end, the present invention consists of two boards having the same configuration, each of which comprises a PLD, a processor for reading and writing a register in the PLD, a power reset circuit for initializing the processor, It consists of an AND gate which is connected to forcibly rebooting the processor of the partner board when an abnormal state occurs during the redundancy implementation, and the two boards are connected by a back plane which transfers the generated interrupt signal. do.

 Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. First, in adding reference numerals to the components of each drawing, it should be noted that the same reference numerals have the same reference numerals as much as possible even if displayed on different drawings. In the following description of the present invention, if it is determined that a detailed description of a related known function or configuration may unnecessarily obscure the subject matter of the present invention, the detailed description thereof will be omitted.

 Figure 2 illustrates a processor board redundancy implementation for performing interrupts in accordance with one embodiment of the present invention. Referring to FIG. 2, a processor board redundancy apparatus according to an embodiment of the present invention includes a first processor board (hereinafter, referred to as a "first processor board") and a second processor board (standby operating state). The boards of the present invention are hereinafter referred to as "second processor boards", each of which includes a processor and a PLD, and a backplane 220 for redundancy for system stability and service continuity. It is mounted side by side in succession. Backplane here is a part of a system, such as a computer's motherboard, or itself. In other words, it serves as a connector for transmitting the interrupt signal 221 between the two board PLD. Hereinafter, for convenience, the board 200 will be described with the first processor board and the board 210 as the second processor board.

 The PLDs 202 and 212 refer to program logic devices embedded in the first processor board 200 and the second processor board 210 to implement register implementation, interrupt control logic, and glitch elimination logic. The power reset circuits 203 and 213 are in a low state for a predetermined time after power is turned on, and are the devices capable of initializing and driving the processors 201 and 211. The AND gates 204 and 214 have one output at two or more inputs, and are circuits for performing the AND function with the result that the output is also only when both inputs are one. In this case, the power reset signal 207 of the first processor board 200 and the signal 206 connected to the second processor board 210 are connected to the AND gate 204 of the first processor board 200 together. have. When an abnormal state occurs during the redundancy implementation and the first processor board is not in a normal state, the processor 211 of the second processor board is connected to the first processor board through the end gate 204 of the first processor board. The signal 206 can be made to operate a low value for some time. As a result, the endgate 204 obtains the same output in hardware as the power reset of the processor of the first processor board, so the endgate 204 eventually returns the processor power of the first processor board from the second processor board. Set is possible. Push switches 205 and 215 refer to button switches generally used.                     

 3 illustrates an internal logic configuration of the PLD 202 of the first processor board. The PLD 202 used in the processor board includes an interrupt control logic 301 inside the PLD and a register 302 capable of reading and writing the processor. And glitch rejection logic 303 that removes noise or glitch of the signal 305 transmitted from the second processor board during redundancy. Hereinafter, each configuration will be described with reference to performing interrupts according to an exemplary embodiment.

 The interrupt control logic 301 sends an interrupt request (hereinafter referred to as "IRQ") to the processor when the corresponding bit of the register already set is changed from 1 to 0 by the interrupt source. The register 302 inside the PLD represents an interrupt source and is implemented with 8 bits, and the interrupt assignment is already set in the register. The interrupt signal 304 generated by the first processor board is directly transmitted to the register 302 inside the PLD, and the interrupt signal 305 transmitted from the second processor board is passed through the glitch elimination logic 303 to register within the PLD. Is passed to 304. In this case, when the interrupt signal 304 generated from the first processor board is sent to the second processor board, the signal is directly transmitted 306 without the glitch elimination logic, and the interrupt signal 305 transmitted from the second processor board is the glitch elimination logic 303. ). In the glitch removal logic 303, the glitch means a logic circuit malfunctioning due to noise or the like. The glitch elimination logic is configured to deliver the original interrupt signal to the register by avoiding the glitch that occurs during unmounting using logic implemented as a counter. By using this, a stable main source can be delivered to a register avoiding an abnormal signal that may occur when unmounting. A register address bit in the PLD will be described in detail with reference to FIG. 4 as follows.

 The processor initializes the board to enable the interrupt register. In normal operation, each bit of the set register is 1 and becomes 0 when an event occurs. The register does not operate when the masking bit is a high value of 1, and the register operates only when the masking bit is a low value of zero. Bit 6 goes from 1 to 0 when a hernia event occurs in the first processor board 200, and the processor requests an IRQ from the interrupt control logic. The processor then enters the Interrupt Service Routine (hereinafter referred to as "ISR") processing and writes the corresponding bit 6 from 0 to 1 at the end of the ISR. Bit 5 goes from 1 to 0 when a hernia event of the second processor board 210 occurs, and the interrupt control logic delivers an IRQ to the processor. The processor performs an ISR and writes the corresponding bit 5 from 0 to 1 at the end of the ISR. Man Machine Interface (hereinafter referred to as "MMI") Reset refers to a software forced reset. When an MMI Reset event occurs in a first processor board by a software instruction, the first processor board knows that an event has occurred, and therefore, only the second processor board needs to transfer the corresponding bit. Thus, the corresponding bit 4 representing the MMI Reset of the second processor board goes from 1 to 0, and the processor requests an IRQ from the interrupt control logic and performs an ISR for the corresponding bit when an IRQ signal is transmitted. At the end of the ISR, the processor writes bit 4 from 0 to 1. The second processor board also performs the same operation with the interrupt signal transmitted 306. When an event occurs by the push switch 205 of the first processor board, bit 3 becomes 1 to 0, an IRQ signal is transmitted to the processor by interrupt control logic, and the processor performs ISR. At the end of the ISR, the processor writes the corresponding bit 3 from 0 to 1. The interrupt signal generated by the push switch 205 of the first processor board is passed 306 to the second processor board, and the processor recognizes the push switch reset of the second processor board to make bit 2 from 1 to 0. . When the IRQ signal is transmitted to the processor by the interrupt control logic, the processor performs the ISR. At the end of the ISR, the processor writes the corresponding bit 2 from 0 to 1. The remaining bits 1 and 0 can be left separate to deliver other sources.

 5 is a flowchart illustrating a redundancy implementation process according to an embodiment of the present invention. Referring to FIG. 5, when both the first processor board 200 and the second processor board 210 of the present invention are mounted, both boards transmit and receive data required by software through internal processor communication channels to prepare for redundancy. Enter step 500. The board mounted first is activated 510, and the board mounted later operates in the standby state 520. The activated first processor board performs the normal operation of the system. The processor reads the address at board initialization and sets the mask bit to a low value to enable the interrupt register. Each bit is 1 in normal operation and 0 in the event occurrence step 511. Each event is communicated to the second processor board via a line 221 connected to the backplane. Hereinafter, the active first processor board will be described.

When a generated event is detected, the corresponding event bit of the register already set by the interrupt source is changed from 1, which is a high value, to 0, which is a low value. Interrupt control logic 301 then passes to step 513 of delivering an IRQ to the processor. When the IRQ is transmitted, the processor reads the corresponding addresses of both the first processor board and the second processor board to determine 514 which bit of the redundant source has caused the event. After the determination, the processor enters an ISR execution step 515 for each bit. In this case, the software has different ISRs to be processed by the redundant source allocated to the system configuration, and the ISR operates differently for each bit. After performing the ISR, the processor inverts the IRQ by writing the corresponding interrupt bit of the PLD register address back to 1 at the end of the ISR (516). The processor then prepares for the next event and withdraws the IRQ (517). In this case, a redundancy transfer is performed at the end of the ISR, and when the transfer is performed, the active board operates in a standby state after booting except for hernia (518), and the standby board operates as an active board (528). In addition, the step 501 is not performed when the hernia is changed.

 As described above, the present invention simplifies the software structure because only the ISR needs to be implemented for each redundant source required for the system using an interrupt through a hardware configuration.

 As another effect of the present invention, it is possible to reboot the initialization of the first processor board without dismounting in the state due to the inability of the redundant board, in particular, the effect of redundancy of the system to provide service continuity and stability of remote or unmanned nations There is an advantage in bringing it.

Claims (8)

In the PLD for processor board redundancy implementation, An interrupt is assigned bit by bit, each bit having a register indicating an interrupt source transmitted from the first processor board and the second processor board; An interrupt control logic that transmits an IRQ to the processor when the corresponding event bit value of the register set by the delivered interrupt source is changed, Programmable logic characterized by removing the noise or glitches of the signal transmitted from the second processor board of the two boards, passing only the original interrupt signal of the second processor board to the register of the first processor board Logic devices. A processor board redundancy implementation, The processor board redundancy implementing apparatus includes a first processor board and a second processor board having the same configuration, and each of the two boards includes: PLD as described in claim 1, A processor that reads and writes corresponding event bits recorded in registers in the PLD to indicate which event occurred on which of the two boards; A power reset circuit for initializing and driving the processor before the processor reads and writes the registers; The signal of the power reset circuit and the signal connected to the second processor board are connected so that when an abnormal state occurs during the redundancy implementation, the power reset signal of the first processor board and the processor of the second processor board are forcibly performed. It consists of an end gate that outputs a signal to reboot the processor of the processor board. And the first and second processor boards are respectively connected to backplanes that transmit interrupt signals between embedded PLDs. The apparatus of claim 2, wherein the processor is capable of accessing and reading a register by directly accessing the PLD through a processor bus. The method according to claim 2, wherein the replacement is necessary even during normal operation due to board replacement or board operation. Processor board redundancy implementation capable of forcing interrupt generation redundancy switching by the processor driving register MMI bit to low value in PLD. In the processor board redundancy implementation method, The two boards send and receive data required by software through the communication channel between internal processors and prepare for redundancy; The first processor board mounted first enters into active operation, Delivering an IRQ of an event occurring after the active operation to a processor; The processor reads the register value in the PLD to determine which bit has caused an event; Performing, by the processor, an ISR for each bit after the determination process; And performing a redundancy transfer after performing the ISR, wherein the first processor board is operated in a standby state. 6. The method of claim 5, further comprising, after the first processor board enters an active operation, the generated event is transferred to a standby second processor board through a backplane. 6. The method of claim 5, wherein the processor further comprises the step of withdrawing IRQs by writing corresponding event bits of the PLD register address as initial values again in the final process of ISR after performing ISR for each bit, and performing redundant switching. How to implement processor board redundancy. The processor of claim 5, wherein when the second processor board detects that the first processor board is incapable of communication, the power reset circuit of the second processor board is connected to the first processor board processor at the second processor board through an end gate of the first processor board. And a process of rebooting by forcibly resetting the power of the processor board.

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