JPH08289014A - Sequence fault detector - Google Patents

Abstract

PURPOSE: To easily detect the occurrence of a fault without imposing a load onto a CPU by providing an overflow signal to the CPU as an interrupt signal when a timer circuit overflows. CONSTITUTION: A timer circuit 10 is constituted such that it is set by a request signal and reset by a reply signal. That is, the time count is started by the request signal and stopped by the reply signal. A CPU 20 controlling the entire detector is connected to the timer circuit 10. When the timer circuit 10 overflows, an overflow signal 10 is given to a CPU 20 as an interrupt signal. When the occurrence of a fault is easily detected, the request signal is a signal denoting a data transfer request and the reply signal is a data transmission timing signal to allow a sequence fault in the data transfer sequence to be easily detected.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a sequence abnormality detecting device.

[0002]

2. Description of the Related Art Currently, a PIF (Peripheral Interfac) is used for exchanging signals between a call processing control process and a subscriber unit in a broadband ISDN switch.
It uses an interface called e). FIG. 5 is a conceptual diagram of a network system. In the figure, 1
Is a main processor (MPR), 2 is a call processing processor (CPR) connected to the main processor 1, and 3 is a switch connected to the call processing processor 2 for performing line switching control. Reference numeral 4 is a plurality of subscriber devices connected to the call processor 2, and 5 is a subscriber terminal connected to the subscriber device 4. 4a is a P provided in the subscriber device 4.
It is an IF interface. N subscriber devices 4 are provided. An arbitrary number of subscriber terminals 5 are provided in each subscriber device 5.

In the system thus constructed,
For example, when a subscriber terminal A connected to the # 1 subscriber device 4 makes a call to a subscriber terminal B connected to the # 2 subscriber device 4, this call is sent to the call processor 2 via the interface 4a. Enter and connect to switch 3. The switch 3 connects to the subscriber terminal B, and the call processor 2 to connect to the subscriber terminal B # 2. After the path is set, data is exchanged by the protocol shown in FIG. Specifically, a sequence is exchanged between the PIF interface 4a in the subscriber device 4 and the call processor 2. FIG. 6 shows the case of the normal sequence. When data is transferred from the call processor 2 side to the subscriber unit 4 side, the request signal (R
EQ) is issued and the subscriber device is notified. Upon receiving this request signal, the subscriber unit returns a response signal (ACK) indicating that data may be accepted to the call processor side. The call processor that receives the response signal starts the transfer of data (DATA). The case of data transfer from the call processor side to the subscriber device side has been described above as an example, but the same applies to the data transfer from the subscriber device side to the call processor side. That is, the subscriber unit side issues a data transfer request (REQ) to the call processor side. The call processor side receiving the data transfer request returns a response signal (ACK) indicating that the preparation is completed to the subscriber unit side. Upon receiving the response signal, the subscriber unit transfers the data (DATA) to the call processor.

In the above, the case of normal sequence operation has been taken as an example, but a sequence abnormality may occur. FIG. 7 is a diagram showing an example of an abnormal sequence. For example, consider a case where data is transferred from the call processor 2 to the subscriber device 4 side. The call processor 2 receives a response signal (ACK) indicating that the preparation is completed from the subscriber device 4 which has received the request signal (REQ).
I returned it to the side, but this A
It is assumed that the CK signal does not reach the call processor 2 side.

The call processor 2 has a built-in timer by software, starts the timer operation when the request signal (REQ) is issued, and waits for a response signal (ACK) to be returned. During this time, the software timer continues counting. Here, when the response signal (ACK) is returned within the predetermined time, the data is transferred and the counting operation of the software timer is stopped. As a result, the software timer does not overflow,
It will end normally. This software timer
It is reset to 0 in preparation for the next operation.

On the other hand, as shown in the figure, the response signal (AC
It is assumed that K) has not reached the call processor 2 due to stacking (indicated by X in the figure). The software timer continues to count during this time, and overflows into it. CPU that received this overflow
Recognizes that a sequence abnormality has occurred. that's all,
Although the operation on the call processor side has been described, the subscriber unit side also incorporates a similar software timer, and when transferring data from the subscriber unit 4 side to the call processor 2 side, similar abnormal sequence monitoring is performed. ing. In other words, the subscriber device 4 side also has a built-in software timer,
Sequence abnormality is recognized by the overflow of the software timer.

[0007]

In the above-mentioned conventional network system, since the monitoring of the sequence abnormality is monitored by the software timer, the CPU concentrates on the operation of the software timer during that period, and other processing operations cannot be performed. There is. Moreover, since the conventional sequence abnormality monitoring uses a software timer, when such a sequence abnormality occurs in the case of hardware debugging, a great deal of distinction is made as to whether the fault is on the software side or the hardware side. It took man hours.

The present invention has been made in view of the above problems, and an object of the present invention is to provide a sequence abnormality detecting device which can easily detect the occurrence of a failure without imposing a burden on the CPU. There is.

[0009]

FIG. 1 is a block diagram showing the principle of the present invention. The circuit shown in the figure is a circuit applicable to either the subscriber unit 4 or the call processor 2 side.
In the figure, 10 is at least one hardware timer circuit that counts clocks. The timer circuit 10 may be provided for each subscriber device 4 (see FIG. 5), for example, and is also provided for the call processor 2. In the figure,
An example in which n pieces of # 1 to #n are provided is shown. These timer circuits are set by a request signal and reset by a response signal. That is, counting is started by the request signal and the counting operation is stopped or reset by the response signal. Reference numeral 20 is a CPU that performs overall control operation, and is connected to the timer circuit 10. When the timer circuit 10 overflows, the overflow signal is given to the CPU 20 as an interrupt signal.

In this case, it is preferable that the request signal is a request signal indicating a data transfer request and the response signal is a data transmission timing signal in order to easily detect a sequence abnormality in the data transfer sequence.

The timer circuit includes a first timer which is set by an acknowledge signal and is reset at a data transmission timing, a second timer which is set by a request signal and is reset by an acknowledge signal, and the first timer. And a fault display register for storing fault outputs of the second timer and C for receiving the outputs of the first and second timers.
It is preferable that the CPU is configured to generate an interrupt signal to the PU and notify the CPU of the contents of the fault display register in order to recognize at which stage of the data transfer sequence the abnormality occurs. Also, it is preferable in reducing the load on software and firmware.

Further, it is composed of a plurality of timer circuits which generate the interrupt signals and a CPU which receives the outputs of these timer circuits as interrupt signals, and the interrupt signals of the timer circuits are assigned to the respective CPUs in the respective interrupt priorities. It is preferable that the CPU perform the subroutine processing according to the interrupt order in order to speed up the failure detection processing according to the content of the sequence abnormality.

[0013]

A hardware timer circuit 10 which is set by a request signal in a data transfer sequence and reset by a response signal (including the case of stopping the counting operation) is provided, and an overflow signal of the hardware timer circuit 10 is interrupted to the CPU 20. I gave it as a signal.
According to the present invention, since a hardware timer is used, C
The load on the PU 20 can be reduced. Further, the timer circuit 10 only needs to count the clocks, and in this case the failure occurrence can be easily detected.
Since the request signal is a request signal indicating a data transfer request and the response signal is a data transmission timing signal, a sequence abnormality in the data transfer sequence can be easily detected.

The timer circuit includes a first timer which is set by an acknowledge signal and is reset at a data transmission timing, a second timer which is set by a request signal and is reset by an acknowledge signal, and the first timer. And a fault display register for storing fault outputs of the second timer and C for receiving the outputs of the first and second timers.
It is possible to recognize at which stage of the data transfer sequence the abnormality occurs by being constituted by a CPU interface unit that generates an interrupt signal to the PU and notifies the CPU of the contents of the fault display register. Also, the burden of software and firmware can be reduced.

Further, it comprises a plurality of timer circuits which generate the interrupt signals and a CPU which receives the outputs of these timer circuits as interrupt signals, and the interrupt signals of the timer circuits are assigned to the respective CPUs in the respective interrupt priorities. Based on the input, the CPU performs a subroutine process according to the interrupt order, thereby speeding up the failure detection process according to the contents of the sequence abnormality.

[0016]

Embodiments of the present invention will be described below in detail with reference to the drawings. FIG. 2 is a configuration block diagram showing an embodiment of the present invention. The circuit shown in the figure is a timer circuit 1 shown in FIG.
It shows the contents of 0. CK shown in the figure is a clock, AC
K indicates an acknowledge signal (data receivable signal) which is a response signal, and REQ indicates a request signal (data transfer request signal) which is a request signal. P using these signals
The operation sequence of the IF interface is as shown in FIG. First, the request signal REQ is output, then the acknowledge signal ACK is returned, and then the data DAT
A is transferred.

In FIG. 2, all G are buffer gates. Reference numeral 11 is a pulse generation circuit for generating a pulse at the falling edge of the ACK signal after receiving the acknowledge signal ACK in the buffer G, and 12 is a clock input terminal CK for the clock CK and an output for the pulse generation circuit 11 is a load input terminal. A flip-flop 13 that receives LOAD is a first timer (hereinafter, abbreviated as timer 1) that receives the output of the flip-flop 12 as an enable signal and the clock CK as a count signal. The reset input terminal of the timer 1 contains a signal synchronized with the data transfer from the CPU.

14 receives the request signal REQ and R
A pulse generation circuit for generating a pulse at the falling edge of the EQ signal, 15 is a clock CK for a clock input terminal CK
The output of the pulse generating circuit 14 to the load input terminal L
A flip-flop 16 which receives the OAD receives a clock CK using the output of the flip-flop 15 as an enable signal.
Is a second timer (hereinafter abbreviated as timer 2) that receives as a count signal. An ACK signal is input to the reset input terminal of the timer 2.

Reference numeral 17 is a fault display register for storing the outputs of the timer 1 and the timer 2, the output of which is the CPU 20 (see FIG.
(See) is notified. 18 is the timer circuit 10 and the CPU 2
It is a CPU interface that connects 0s. A bus 19 is connected to the CPU interface 18. C
When the PU interface 18 detects the occurrence of the sequence abnormality from the outputs of the timer 1 and the timer 2, the CPU 2
0 is notified as an interrupt signal via the buffer G. The output of the fault display register 17 is sent to the CP via the bus 19 via the CPU interface 18.
It will be notified to U20. The operation of the circuit thus configured will be described below.

When transferring data to the partner device (call processor 2 or subscriber device 4), the device shown in the figure outputs a request signal REQ to the partner device. When the request signal REQ is output, the pulse generation circuit 14 generates a pulse as shown in the figure in synchronization with the fall. When the output of the pulse generating circuit 14 is given to the flip-flop 15 as a load signal, the flip-flop 15 outputs an active signal in synchronization with the request signal REQ from its Q output and gives it to the enable terminal of the timer 2. As a result, timer 2
Is enabled and starts counting clocks.

Here, if there is no abnormality in the interface, an acknowledge signal ACK is returned from the partner device (see FIG. 6). The acknowledge signal ACK enters the reset input of the timer 2 via the buffer G. As a result, the timer 2 is reset or the counting operation is stopped. When reset, its output will be 0,
When the operation is stopped, the count value at that time is held. In normal operation, the time from the issuance of the request signal REQ to the return of the acknowledge signal ACK is short (see FIG. 3). Therefore, the timer 2 does not count up and overflow during this period. The CPU interface 18 does not generate an interrupt signal because the output of the timer 2 is not an overflow signal.

On the other hand, when the acknowledge signal from the other device is not returned, the timer 2 continues the counting operation and finally overflows. This overflow signal is stored in the fault display register 17 and the CP
It is input as an interrupt signal to the CPU 20 via the U interface 18. Although the CPU 20 has been performing other operations until then, when it receives this sequence abnormality interrupt, it calls a coping process subroutine corresponding to the type of interrupt and starts a predetermined process. As described above, according to the present invention, the CPU 20 can perform other processing unless an interrupt occurs, so that the load on the CPU 20 is significantly reduced.

Next, the operation of the timer 1 will be described.
As described above, the acknowledge signal ACK is sent from the partner device.
Is returned, the pulse generating circuit 11 generates a pulse as shown in the figure in synchronization with the falling edge of the signal. When the output of the pulse generating circuit 11 is given to the flip-flop 12 as a load signal, the flip-flop 12 outputs an active signal in synchronization with the acknowledge signal ACK from its Q output and gives it to the enable terminal of the timer 1. As a result, the timer 1 is enabled and starts counting clocks.

Here, when there is no abnormality in the interface, the device which has received the acknowledge signal ACK from the partner device starts data transfer (see FIG. 6). Then, the CPU 20 gives a signal indicating that the data transfer is started to the CPU interface 18 via the bus 19. When a signal synchronized with this data transfer is given as a reset signal from the CPU interface 18 to the timer 1, its output is set to 0 or its operation is stopped. When reset, the output becomes 0, and when the operation is stopped, the count value at that time is held. In the case of normal operation, the time from the receipt of the acknowledge signal ACK to the data transfer is short (see FIG. 3). Therefore, the timer 1 does not count up and overflow during this period. The CPU interface 18 does not generate an interrupt signal because the output of the timer 1 is not an overflow signal.

On the other hand, when a signal synchronized with the data transfer signal is not generated due to some interface abnormality, the timer 1 continues the counting operation and finally overflows. This overflow signal is stored in the failure display register 17 and the CPU interface 18 as well.
And is input to the CPU 20 as an interrupt signal. C
Although the PU 20 has been performing other operations until then, when it receives this sequence abnormal interrupt, it calls a coping process subroutine corresponding to the type of interrupt and starts a predetermined process. As described above, according to the present invention, the CPU 20 can perform other processing unless an interrupt occurs, so that the load on the CPU 20 is significantly reduced.

In the above operation, timer 1 and timer 2
When the overflow occurs, the fault display register 17
The fault content is stored, but the content of the fault display register 17 is notified from the bus 19 to the CPU 20 via the CPU interface 18. As a result, the CPU 20 can recognize the details of the failure and reduce the load on the software and firmware.

In the above embodiment, the request signal REQ
The case of counting from the issuance of the acknowledge signal to the return of the acknowledge signal and the case of counting the time from the acceptance of the acknowledge signal ACK to the data transfer have been described. This makes it possible to determine which sequence has an abnormality depending on which counter overflows. However, the present invention is not limited to this. Data transfer request signal REQ
If it is only necessary to detect the sequence error from the issuance of data to the transfer of data, even if one timer is provided which starts the count operation with the request signal REQ and is reset with the data transfer signal The purpose can be achieved. However, in this case, it is only known that there is an abnormality in the data transfer sequence, and which sequence has an abnormality cannot be known. However, the number of timers is only one, which has the effect of simplifying the circuit.

FIG. 4 is an operation explanatory diagram of the embodiment of the present invention. The same parts as those in FIG. 1 are designated by the same reference numerals. Three
Reference numeral 0 is a subroutine that is activated each time an interrupt is received by the CPU 20, and subroutines 1 to n are provided according to the interrupt input. In this embodiment, the output of each timer circuit 10 is input to different interrupt input terminals INT of the CPU 20. For example, when the interrupt signal is input from the timer circuit 1 to the interrupt input terminal INT1, the CPU 20 activates the subroutine 1 corresponding to the interrupt input 1 and executes a predetermined process. When a plurality of interrupt signals are input at the same time, the CPU 20 executes a subroutine process according to a predetermined priority order. For example, interrupt 1
If the interrupt 1 and the interrupt n occur at the same time, and the interrupt 1 has a high priority, the CPU 20 executes the subroutine 1 and then the subroutine n. As described above, according to the present invention, by providing only the interrupt type for the interrupt input, it is possible to execute the process according to the type of interrupt, and to speed up the failure detection process according to the content of the sequence abnormality. Can be achieved. Moreover, since each interrupt signal is generated by the hardware timer, it does not burden the CPU 20.

In the above-mentioned embodiment, the case of using it in the network system has been described as an example, but the present invention is not limited to this, and can be applied to all kinds of systems for transferring data according to a certain protocol.

[0030]

As described above in detail, according to the present invention, a hardware timer circuit which is set by a request signal in a data transfer sequence and reset by a response signal (including the case of stopping the count operation) is provided. An overflow signal of the hardware timer circuit is provided to the CPU as an interrupt signal. According to the present invention,
Since the hardware timer is used, the load on the CPU can be reduced. Further, the timer circuit only has to count the clocks and can easily detect the occurrence of a failure. In this case, the request signal is a request signal indicating a data transfer request, and the response signal is a data transmission timing signal. Therefore, it is possible to easily detect a sequence abnormality in the data transfer sequence.

The timer circuit includes a first timer which is set by an acknowledge signal and is reset at a data transmission timing, a second timer which is set by a request signal and is reset by an acknowledge signal, and the first timer. And a fault display register for storing fault outputs of the second timer and C for receiving the outputs of the first and second timers.
It is possible to recognize at which stage of the data transfer sequence the abnormality occurs by being constituted by a CPU interface unit that generates an interrupt signal to the PU and notifies the CPU of the contents of the fault display register. Also, the burden of software and firmware can be reduced.

Further, it comprises a plurality of timer circuits which generate the interrupt signals and a CPU which receives the outputs of these timer circuits as interrupt signals, and the interrupt signals of the timer circuits are given to the respective CPUs in the respective interrupt priorities. Based on the input, the CPU performs a subroutine process according to the interrupt order, thereby speeding up the failure detection process according to the contents of the sequence abnormality.

[Brief description of drawings]

FIG. 1 is a principle block diagram of the present invention.

FIG. 2 is a circuit diagram showing an embodiment of the present invention.

FIG. 3 is a diagram showing an operation sequence of an interface.

FIG. 4 is an operation explanatory diagram of the embodiment of the present invention.

FIG. 5 is a conceptual diagram of a network system.

FIG. 6 is a diagram showing an example of a normal sequence.

FIG. 7 is a diagram showing an example of an abnormal sequence.

[Explanation of symbols]

 10 timer circuit 20 CPU

Claims (4)

[Claims] 1. A configuration comprising at least one hardware timer circuit that counts a clock, and a CPU that performs overall control operation, wherein the timer circuit is set by a request signal and reset by a response signal. A sequence abnormality detecting device configured to give an overflow signal to the CPU as an interrupt signal when the timer circuit overflows. 2. The sequence abnormality detecting apparatus according to claim 1, wherein the request signal is a request signal indicating a data transfer request, and the response signal is a data transmission timing signal. 3. The timer circuit includes: a first timer which is set by an acknowledge signal and reset by a data transmission timing; a second timer which is set by a request signal and reset by an acknowledge signal; And a fault display register for storing fault outputs of the second timer, and a CPU for receiving the outputs of the first and second timers, generating an interrupt signal to the CPU, and notifying the CPU of the contents of the fault display register. The sequence abnormality detecting device according to claim 1, wherein the sequence abnormality detecting device comprises an interface unit. 4. A plurality of timer circuits which generate the interrupt signals, and a C which receives outputs of these timer circuits as interrupt signals.
2. The sequence according to claim 1, further comprising a PU, the interrupt signal of the timer circuit being input to the CPU based on respective interrupt priorities, and the CPU performing a subroutine process according to the interrupt priority. Anomaly detection device.