JPH01250161A - Data transfer processing system - Google Patents

Abstract

PURPOSE:To realize the effective application of data buffers set at both sides in a data transfer processing system by allowing an input controller to receive data or reject the transmission of data and performing the interruption/restart of transfer of data, the suppression of data reception and the overrun detection via a peripheral controller. CONSTITUTION:A means 8 which produces a rejecting signal to reject the transfer of data when a data buffer 5 of an input/output controller 1 is filled or empty is provided. Further, means 11, 12 which discontinue the transmission of data in reply to the generation of said rejecting signal and to discontinue the reception of data at the side of a peripheral controller 2 and a means 13 which detects an overrun state when a data buffer 7 is filled or empty are provided. In such a constitution, the effective application is ensured for both buffers together with reduction of the overrun occurring frequency. Thus it is possible to prevent the deterioration of the data transfer processing ability due to the occurrence of the overrun states at both buffers.

Description

[Detailed description of the invention] Kugomame! The present invention relates to a data transfer processing system, and more particularly to a data transfer processing system between an input/output control unit (IOC) and a peripheral control unit (PCU).

The IOC and PCU are installed between a higher-level device and a lower-level device that have different data transfer speeds, and in order to match the data transfer between these two devices, both the IOC and PCU have data buffers. are doing.

Then, in the input data sequence, data from the lower device is sent to the data buffer of the PCU, and this data is transferred to the I
The data is stored in the OC data buffer and sent to the host device. In the output data sequence, conversely, the IO is sent from the host device to the data buffer of the IOC.
Data is transferred from the data buffer of C to the data buffer of PCU, and from the data buffer of PCU to lower-order devices.

As a data transfer protocol at the input/output interface between the IOC and the PCU, there is a data streaming method in which both the input and output data sequences are initiated by the PCU. In this method, both the input and output data sequences are a data streaming method having a protocol in which the rising edge of the PCU sending strobe precedes the rising edge of the IOC sending strobe.

The relationship between the PCU sending strobe and the IOC sending strobe is that when input/output data transfer is started, a PCU sending strobe is generated from the PCU side at a certain period and sent to the IOC side, and the IOC side generates a PCU sending strobe. When this is received, an IOC sending strobe is sent back to the PCU in response, and data is exchanged in synchronization with the strobe.

Therefore, the number of generated PCU sending strobes and the number of generated IOC sending strobes always match, and the number of generated strobes represents the number of times data is exchanged.

A conventional method for detecting an overrun in a data transfer processing system having a Plutonyl input/output interface as described above will be explained with reference to FIG.

Figure 4 (A) is a time chart showing overrun detection during input transfer.
and PCU are upper and lower devices with different data transfer speeds (
In order to coordinate the data transfer with the data transfer terminals (both not shown), each of them is assumed to have a data buffer of several to several tens of bytes.

Data sequence input and output sequence valve to PCU
In the data transfer method that starts with , during the data sequence, when the PCU strobe becomes "1" in the input sequence due to the relationship between the transfer processing time and the system load, the I
When the data buffer of the OC becomes a groove (16 bytes in this example), the IOC side cannot receive data and an overrun is detected at the IOC.

Similarly, overrun detection during output transfer is shown in Figure 4 (B
), the output sequence is as shown in the time chart.
When the U sending strobe becomes '1', the data buffer of the IOC becomes empty and the IOC side is unable to send data, and only then is an overrun detected on the IOC side.

When such an overrun is detected, the abnormal end of the data sequence is notified to the higher-level device and the lower-level device, respectively.

In such a conventional overrun detection method, a data sequence is started unilaterally on PCU ff1, and when it becomes impossible to receive or send data on the 10C side in this data sequence, the IO
Since C is a method to detect overrun, I
This means that both the OC and PCU data buffers are not effectively utilized.

In other words, in the input data sequence, the IOC data buffer is empty, but even though there is space in the PCU data buffer, an overrun is detected.Also, in the output data sequence, the IOC data Although the buffer is empty, there is a drawback that an overrun is detected even though there is valid data in the data buffer of the PCU.

Therefore, the present invention was made to solve the drawbacks of the conventional ones, and its purpose is to
It is an object of the present invention to provide a data transfer processing system that reduces the frequency of occurrence of overruns by effectively utilizing data buffers of both an OC and a PCU, and prevents a decline in data transfer processing capacity due to the occurrence of overruns.

According to the present invention, when data is transferred between a lower-level device and a higher-level device, the lower-level device 0 peripheral control device.

Arranging the input/output control device and the host device in this order,
1. A data transfer processing system that transfers data via data buffers provided in the peripheral control device and the input/output control device. The input/output control device side is provided with means for generating a rejection signal for refusing data transfer when the data buffer of the input/output control device becomes full or empty, and the peripheral control device side means for stopping data transmission and data reception in response to generation of the rejection signal; and means for detecting overrun when the data buffer of the peripheral control device becomes full or empty. A data transfer processing system is obtained, which is characterized in that it is provided with the following.

E1 father-in-law Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a system block diagram of an embodiment of the present invention.
In the figure, l0C (input/output control device) 1 and PCU
(Peripheral control devices) 2 are interconnected via an input/output interface bus 3. Input/output interface bus 3
includes a PCU sending strobe 13-1, an IOC sending strobe 3-2, data 3-3, and a dialogue rejection signal 3-4 indicating a refusal to receive data or a refusal to send data.

l0CI is an input/output interface control circuit 4, a data buffer 5 of, for example, 16 bytes, and a dialogue rejection signal 3-4 which indicates a refusal to receive data or a refusal to send data, respectively, when this data buffer becomes empty or empty. and a dialogue rejection signal generation circuit 8 that generates a dialogue rejection signal.

The PCU 2 includes an input/output interface 6, a data buffer 7 of, for example, 16 bytes, a counter 9 for counting PCU sending strobes, and a counter 10 for counting IOC sending strobes returned from the IOC in response to the PcU sending strobes. It includes a counter correction instruction circuit 11 that instructs correction of the count value of the counter 9, a counter update suppression instruction circuit 12 that instructs counter update suppression (count suppression) of the counter 1°, and an overrun detection circuit 13. .

Figure 2 shows the input data sequence of the system in Figure 1 (
12 is a time chart of a sequence in which data is transferred from a lower-level device (not shown) to a higher-level device (not shown) sequentially via a PCU and an IOC.

Even if the 10C data buffer 5 becomes full and the PCU sending strobe reaches 1, it does not cause an overrun as in the conventional case, but the 10CI generates a dialog rejection signal in the dialog rejection signal generation circuit 8 indicating a refusal to receive data. Set signal 3-4 to “1”
and returns the IOC sending strobe 3-2 to the PCU 2.

Upon receiving this interaction rejection signal 3-4, the PCU 2 temporarily suspends data transfer and also issues a counter update suppression instruction circuit 12.
As a result, the count update of the IOC sending strobe counter 10 is suppressed, and at the same time, the counter correction instruction circuit 1
1 instructs to correct the PCU sending strobe counter 9. In this case, as shown in FIG. This value is the groove value of the data buffer, and indicates that data reception after 16j is rejected.

In this state, when the data exit to the host device progresses at l0CI (1!I) and a space becomes available in the data buffer 5, the dialogue rejection signal 3-4 becomes "0" and the corrected PCU strobe counter 9 indicates The data transfer from the rejected data "16" is restarted.

Overrun detection is performed when the data buffer 7 of the PCU 2 becomes a groove during the period when l0CI refuses to accept data.
When there is a data transfer request from a lower-level device of U2,
This is first performed by the overrun detection circuit 13 of the PCU 2.

FIG. 3 is a time chart during an output data sequence (a sequence in which data is transferred from a higher-level device to a lower-level device via the IOC and PCU in this order). The data buffer 5 of l0CI becomes empty, and the PCU sending strobe 3-
1 is "1", instead of overrun as in the conventional case, the l0CI generates a dialogue rejection signal 3-4 indicating data transmission rejection by the dialogue rejection signal generation circuit 8, and outputs the IOC transmission strobe 3-1. Returned to PCU2 side, at this time IOC
The sent data becomes invalid data.

While receiving this conversation rejection signal 3-4, the PCU 2 inhibits data reception and also inhibits updating of the IOC transmission/output counter 10. In addition, since it is necessary to correct the PCU sending strobe counter 9 accordingly, the counter correction instruction circuit 11 causes the PCU sending strobe counter 9 to be corrected.
is subtracted, and correction processing is performed so as to match the contents of the IOC sending strobe counter 9.

When the data transfer from the host device progresses and the data buffer 5 of the IOC is no longer empty, the dialogue rejection signal 3-4 becomes “0”.
Then, data reception is restarted by sending valid data from 1001.

Overrun detection is performed by the PCU only when the data buffer 7 of the PCU becomes empty and there is a data transfer request from a lower device of the PCU during the IOC's data transmission refusal period.

At the end of the data sequence, the data length of the transferred data can be known by confirming that the PCU sending strobe counter 9 and the IOC sending stroke counter 10 match.

As explained above, according to the present invention, the IOC is allowed to refuse data reception or transmission, and when the PCU receives this rejection signal, it interrupts and resumes data transfer in the input sequence, and inhibits data reception in the output sequence. and P
By performing overrun detection in CUIII, I
Effectively utilizes the data buffers of both OC and PCU,
This has the effect of reducing the frequency of overrun occurrences and reducing the reduction in the data transfer processing capacity of the present data transfer processing system due to the occurrence of overruns.

[Brief explanation of the drawing]

Fig. 1 is a block diagram of an embodiment of the present invention, Fig. 2 is a time chart during input transfer of the block shown in Fig. 1, Fig. 3 is a time chart during output transfer of the block shown in Fig. 1, and Fig. 4 (A) and (B) are time charts during input/output transfer in the conventional method. Explanation of symbols of main parts 1...l0C (input control device) 2...
PCU (peripheral control unit) 3... Data bus 5.7... Data buffer 8... Dialogue rejection signal generation circuit

Claims (1)

[Claims] (1) When transferring data between a lower-level device and a higher-level device, the lower-level device, peripheral control device, input/output control device, and the above-mentioned higher-level device are arranged in this order, and the peripheral control device and the above-mentioned input/output control device are arranged in this order. A data transfer processing system configured to transfer data via a data buffer provided in a device, wherein the input/output control device side detects whether the data buffer of the input/output control device is full or empty. means for generating a rejection signal to refuse data transmission and reception when the rejection signal is generated; , means for detecting an overrun when the data buffer of the peripheral control device becomes full or empty.