JPH03212754A - Memory request control system - Google Patents

Abstract

PURPOSE:To execute a memory request without reducing a memory request processing speed even if the request competes with another request by suppressing a memory request from an arithmetic processor during the processing of a request. CONSTITUTION:When a memory request is sent from an I/O control device 3, a comparator 42 detects discrepancy between the contents of I/O replay number counters 40, 41, turns on a request processing signal 202 to turn on a request suppressing signal 301 to be inputted to the arithmetic processor 2. A replay signal 250 receiving the request processing signals 201, 202 is returned to a main storage device 4 and a replay circuit 13 receives the replay signal 250 and sends a replay signal 400 or 401 to the processor 2 or the device 3. The contents of an operation replay number counter 31 or the I/O replay number counter 41 are counted up and the comparators 32, 42 respectively detect coincidence between respective inputs to suppress the sending of the memory request from the processor 2.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a memory request control method, and particularly to a priority control method for memory requests from an input/output control device.

[Conventional technology]

Conventionally, in memory request control of an input/output control device that transfers data between an arithmetic processing device and an external storage device, as shown in FIG. 2, a buffer 10 for storing memory requests is provided in the system control device 1a. Memory requests from the input/output control device 3a or arithmetic processing device 2a to which the external storage device 5 is connected are received and sent to the buffer 1 in order.
It was stored at 0. Then, the buffer 10 is F U L
When the L state is reached and further memory requests cannot be accepted, a memo IJ quest suppression signal is sent to each of the arithmetic processing unit 2a and input/output control unit 3a, and any further memory requests are stopped by the arithmetic processing unit. 2
a and the input/output control device 3a.

For example, when the extended storage device 6 is connected to the system control device 1a and data is being transferred in blocks between the main storage device 4 and the extended storage device 6, a memory request from the arithmetic processing device 2a or the input/output control device 3a Processing is performed only between blocks, and if the processing unit 2a continuously issues memo IJ/IJ quests to execute instructions, the memory requests from the processing unit 2a are continuously sent to the buffer 10. stored and buffer 10 is full
When the state is reached, a memory request suppression signal is sent to each of the arithmetic processing unit 2a and the input/output control unit 3a. Therefore, memory requests from the input/output control device 3a could no longer be sent.

[Problem to be solved by the invention]

In the conventional memory request control method described above, when a memory request from an input/output control device competes with a memory request from an arithmetic processing unit or a data transfer between an expanded storage device and memory, the processing speed decreases significantly. Therefore, if the transfer speed becomes lower than the transfer speed with the external storage device, the data cannot be guaranteed and the transfer must be redone.

It is also possible to provide a request buffer for each of the arithmetic processing unit and the input/output control unit within the system control unit, but this has the disadvantage that the amount of hardware increases.

[Means to solve the problem]

The memory request control method of the present invention is set in advance to turn on and off at regular intervals in an information processing device to which an input/output control device that transfers data between an arithmetic processing unit, an external storage device, and a main storage device is connected. pulse generating means for generating a pulse signal that repeats OFF; input/output request display means for displaying that a memory request from the input/output control device is being processed; and a memo IJ from the arithmetic processing device.
A calculation request display means for displaying that the IJ Quest is being processed, and a memo IJ from the input/output control device.
memory request inhibiting means for instructing the arithmetic processing unit to inhibit sending of memory requests when QUEST processing is in progress or when the pulse signal is ON.

Furthermore, the memory request control method of the present invention includes a reply circuit that discriminates replies from the main storage device and sends out signals for counting the number of calculation replies and the number of input/output replies.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention. In the figure, the memory request control method includes a system control device 1, an arithmetic processing device 2, an input/output control device 3 to which an external storage device 5 is connected, and a main storage device 4.

The system control device 1 includes a buffer 10 that stores a plurality of memory requests from the arithmetic processing device 2 or the input/output control device 3, a request number counter 20 that counts the number of requests stored in the buffer 10, and a buffer 10.
The request processing number counter 21 counts the number of requests sent to the main storage device 4 among the memory requests stored in the memory, and the request processing number counter 20 and the request processing number counter 21 are compared to determine the number of requests stored in the buffer 10. Check the number of requests and buffer 10
a comparator 22 that sends out a buffer FULL signal 200 when the buffer is in the FULL state, and a calculation request number counter 3 that counts the number of memory requests from the calculation processing unit 2.
0 and the reply 250 from the main storage device 4 is received, and in the case of a reply to the request 101 from the arithmetic processing unit 2, it sends the reply 401 to the arithmetic processing unit 2 and also sends a count up signal to the arithmetic reply number counter 31. 251 and request 10 from input/output device 3.
In the case of a reply to 0, a reply 400 is sent to the input/output device 3 and an input/output reply number counter 41 is sent.
Reply circuit 1 that sends out a count-up signal 252 to
3, a calculation reply number counter 31 that sends replies 250 from the main storage device 4 to the processing unit 2 and counts the number of memory requests for which processing has been completed, and a calculation request number counter 30 and a calculation reply number counter 31. If there is a memory request from the arithmetic processing unit 2 that is being processed by the system control device 1, the processing signal 20 is sent.
1, and an input/output request counter 40 that counts the number of memory requests from the input/output control device 3. The input/output calliply number counter 41 that counts the number of completed memory requests is compared with the input/output request number counter 40 and the input/output calliply number counter 41 to determine whether there is a memory request from the input/output control device 3 that is being processed by the system control device 1. In this case, a comparator 42 that sends out a processing signal 202, and a pulse generation circuit 12 that generates a pulse signal 203 that repeats the operation of turning on for a clock period set by software and then turning off for one clock period. , the above comparators 22, 32, 42 . and pulse generation circuit 12
A request suppression circuit 1 that sends a memory request suppression signal 300.301 to the arithmetic processing device 2 or input/output control device 3 using signals 200, 201, 202.203 from the
1.

FIG. 2 is a circuit diagram showing an example of the request suppression circuit 11 described above. In the same figure, the request suppression circuit 11 is
D50, 0R51 and 52.

FIG. 3 is a time chart showing the operation of the above memory request control method.

For example, if the pulse generation circuit 12 is set to be ON for one clock period by software, the pulse signal 203 is repeatedly turned ON and OFF every one clock period, and the request suppression circuit 11 calculates the pulse signal 203. A request suppression signal 301 to the processing device 2 is always sent out every clock cycle, and a memory request from the arithmetic processing device 2 is sent out every other clock cycle.

When the arithmetic processing unit 2 sends the memory request (2) at the timing when the request suppression signal 301 is OFF, the request is stored in the buffer 10 and at the same time, the request number counter 20 and the arithmetic request number counter 30 are each incremented by 1. When the calculation request number counter 30 is incremented by 1, the comparator 32 detects a discrepancy with the calculation reply number counter 31 and turns ON the memory request processing 201 from the calculation processing unit 2.

Next, when the input/output control device 3 sends out the memo IJ IJ quest ■, it stores the request in the buffer 10 and at the same time increments the request number counter 20 and the input/output request number counter 40 by 1, respectively. When the input/output request number counter 40 is incremented by 1, the comparator 42 detects a mismatch with the input/output request number counter 41 and turns on the request processing 202 from the input/output control device 3.

When the request processing signals 201 and 202 are both turned ON, AND50.0R51 of the request suppression circuit 11,
Each of the 52 circuits operates to turn on the request suppression signal 301 to the arithmetic processing unit 3.

After that, the request processing signal 201 or 202 is sent to the main memory 4 as a reply 250 of the accepted memory request.
The reply circuit 13 receives it and sends a reply 400 or 401 to the arithmetic processing unit 2 or input/output control unit 3.

Then, the calculation reply number counter 31 or the input/output reply number counter 41 is counted up, and the comparator 32.4
2 detects a match.

At this time, the output signal of AND50 remains ON until there is no longer a memory request being processed, so the arithmetic processing unit 2
The request suppression signal 301 remains ON, and the sending of memory requests from the arithmetic processing unit 2 is suppressed. Furthermore, request suppression signal 3 to input/output control device 3
00 remains OFF, the memory request from the input/output control device 3 causes the buffer 10 to go into the FULL state, the comparator 22 turns on the buffer FULL signal 200, and the request suppression circuit 11 suppresses the request to the input/output control device 3. The signal can be transmitted continuously until the signal 300 is turned ON.

〔Effect of the invention〕

As explained above, the present invention suppresses memory requests from the arithmetic processing unit while requests from the arithmetic processing unit and the input/output control unit are being processed, thereby allowing memory requests from the input/output control unit and the arithmetic processing unit to compete. Even in such a case, there is an effect that memory requests from the input/output control device can be processed without slowing down in processing speed.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a block diagram of a request suppression circuit, FIG. 3 is a time chart showing the operation of the present invention, and FIG. 4 is a block diagram showing a conventional example. be. 1... System control device, 2... Arithmetic processing device, 3
... input/output control device, 4... main storage device, 5...
External storage device, 10...Request buffer, 11.
...Request suppression circuit, 12...Pulse generation circuit,
13...Reply circuit.

Claims (1)

[Claims] 1. In an information processing device to which an input/output control device that transfers data between an arithmetic processing unit, an external storage device, and a main storage device is connected,
, a pulse generating means for generating a pulse signal that repeats OFF, an input/output request display means for displaying that a memory request from the input/output control device is being processed, and an operation request displaying for displaying that a memory request from the arithmetic processing device is being processed. a display means, and when a memory request from the input/output control device is being processed and a memory request from the arithmetic processing device is being processed, or when the pulse signal is ON, inhibiting sending of a memory request to the arithmetic processing device; A memory request control method comprising: memory request suppression means for instructing a memory request control method. 2. The memory request control method according to claim 1, further comprising a reply circuit for discriminating replies from the main storage device and sending out signals for counting the number of calculation replies and the number of input/output replies. control method.