KR970002814B1 - Control unit of physical layer management part - Google Patents

Abstract

The present invention relates to a physical layer hierarchical administrator control system that detects the layered condition of the physical layer and processes a change in hierarchical administrator state. The system includes an interrupt processing part (11) that controls interrupt and informs information as to the interrupt processing to a system administrating part; an LCD processing part (13) outputting a loss of cell delineation (LCD) signal and informs the part (11) of the same; an LCD timer (12) connected to the LCD processing part (13); a failure processing part (15) informing the part (11) of the LCD failure signal; a failure timer (14) connected to the failure processing part (15) and the LCD timer (12) and producing predetermined signals (3S, 10S) for hierarchical administration; and a hierarchical administration state register (16) producing hierarchical administration state information in response to an input/output control signal (R/W) from an external system part.

Description

Physical Layer Hierarchy Control Unit

1 is a block diagram of a physical layer layer management unit control apparatus according to the present invention;

2 is a signal timing diagram according to the operation of the present invention.

* Explanation of symbols for main parts of the drawings

11: interrupt processing unit 12: LCD timer

13: LCD processor 14: FAIL timer

15: Hierarchy Management Status Register.

The present invention relates to a transmission apparatus using a non-registered transmission mode (ATM) (hereinafter referred to as ATM), which is a transmission method of a broadband integrated information communication network (hereinafter, referred to as B-ISDN), to search for a hierarchical state of a physical layer. It relates to a physical layer layer management unit control device for processing the presence or absence of a change in the status management.

In general, in the B-1SDN, a 53-octet ATM cell in the form of a packet generated in an upper layer ATM layer is used to provide various services. The ATM cell transmitted to the physical layer is transmitted by adding a header error check code (hereinafter referred to as HEC) to protect the header, and the receiver checks the header of the ATM cell received through the HEC. Only valid cells are sent to the upper layer ATM layer.

However, the system manager cannot determine whether the operation state of the physical layer is normal by only transmitting and receiving normal cells. The reason for this is that when a physical layer link state is not normal, a loss of cell delineation (hereinafter referred to as LOS) occurs at the physical layer receiving unit. Accordingly, an error of HEC occurs sequentially, but the link state is normal. In this case, it can be seen that the ATM cell generation failure transmitted from the counterpart transmitting side is detected even though the LOS does not occur.

As a result, when an abnormal state occurs in the physical layer link and the receiving HEC processing unit, the physical layer may not transmit any cell to the ATM layer for several hours in a few msec without recovery of the link and the receiving unit.

Therefore, the present invention devised to solve the above problems, by notifying the physical layer management unit whether there is an abnormal state of the link and the receiving HEC processing unit, the physical layer layer to provide a smooth maintenance function of the system including the same through the management of the physical layer The purpose is to provide a management unit control device.

In order to achieve the above object, the present invention, when an error of the HEC signal from the external physical layer processing unit interrupts it to generate an OCD (Out Of Cell Delineation) signal (hereinafter referred to as OCD) signal and to control it when the continuous interrupt occurs, Interrupt processing means for notifying the system management unit of information about the interrupt processing; LCD processing means for generating an LCD signal in accordance with the OCD signal and notifying the interrupt processing means; and a predetermined period of time connected to the LCD processing means. LCD timer means for repeatedly counting, fault processing means for notifying the interrupt processing means of the LCD fault signal according to the LCD signal, and connected to the fault processing means and the LCD timer means for generating a predetermined signal for hierarchical management. A failure timer means and a signal provided from the interrupt processing unit to an external system And hierarchical management status register means for outputting hierarchical management status information according to the input / output control signal provided by the management unit.

The present invention is a device for processing the maintenance of each physical layer connecting the ATM network, the 1-bit error is corrected through the HEC processing for the cells transmitted in connection with the counterpart physical layer link, multi-bit By discarding the corresponding cell, only valid cells are transmitted to the ATM. However, the OCD signal is notified to the physical layer processor through an interrupt for successive 7-cell HEC errors. If this state persists for 4 msec, the LCD signal is notified to the physical layer processor through an interrupt. If the status of the LCD persists for 3 seconds, the LCD failure signal is notified to the physical layer management through the interrupt, and the system error is informed about the link failure of the ATM layer and the counterpart device and the reception HEC processing error. By notifying the cause and form of the system, smooth system maintenance management is possible.

Hereinafter, with reference to the accompanying drawings will be described an embodiment of the present invention;

1 is a block diagram of an apparatus for controlling a physical layer management unit according to the present invention, in which 11 is an interrupt processor, 12 is an LCD timer, 13 is an LCD processor, 14 is a FAIL timer, 15 is an FAlL processor, and l6 is a layer management status register. Respectively.

As shown in the figure, the present invention generates an OCD signal when a change in HEC signal for cell boundary identification occurs from another link of an ATM network or an external physical layer processing unit, and outputs layer management status information by an interrupt. 4mS according to the interrupt processor 11, the LCD processor 13 connected to the interrupt processor 11 to generate an LCD signal after 4mS when receiving the OCD signal, and the 4MS-CLR signal output from the LCD processor 13; LCD timer 12 for counting and notifying the LCD processor 13 to the LCD processor 13, a fault processor 15 for transmitting an LCD fault signal after 3S to the interrupt processor 11 when receiving the LCD signal, and the LCD timer. The fault timer 14 for notifying the fault processor 15 of the counted time driven and driven by (12) and the hierarchical management status information provided from the interrupt processor 11 are input / output control signals (R / W *). And a hierarchical management state register 16 output to the external system manager.

2 is a signal timing diagram according to the operation of the control device of the physical layer management unit of the present invention. The contents of each signal shown in the drawing are as follows.

The system clock 201 of the system management unit having a speed of 19.44MHZ and a signal indicating the header error occurrence state of 7 consecutive cells from the external physical layer processing unit. The logical value '0' indicates a steady state and the logical value '1'. HEC signal 202 indicating a header error occurrence state, and when the HEC signal 202 is generated from a logic value '0' to '1', is synchronized to the system clock 201 to physical layer link and cell boundary identification. An OCD signal 203 indicating the state of the signal, a TIMER-CLR signal 204 for resetting the LCD timer 12 whenever the OCD signal 203 changes, and the OCD signal 203 at a logical value '0'. 4MS-CLR signal 206 generated after '1' and repeatedly generated every 4mS period, 4MS-CLR signal 206 to reset after the LCD timer 12 becomes 4mS, and the OCD signal ( Provides the LCD signal 207 generated by the 4MS signal 205 and the 4MS signal 205 while 203 holds the logic value '1'. After the failure timer 14 receives the 3S signal 208 repeatedly generated from the logic value '0' to '1' every 3S cycles and the 4MS signal 205, the logic timer '0' is 10S. The 10S signal 209 generated by '1' and the LCD signal 207 are generated from logic '0' to '1' and the logic value is '0' to '1' in synchronization with the 3S signal 208. And the LCD signal 207 is released from '1' to '0', the LCD failure signal 210 is registered with the l0S signal 209 and the logic value is generated from '1' to '0'. When the LCD failure signal 210 changes, the FAIL-CLR signal 211 for resetting the FAlL timer 14 and the OCD, LCD and LCD failure signals 203, 207 and 210 are notified of an error in the system management unit. An input / output control (R / W *) signal that resets the interrupt register of the interrupt processing section 11 as an INT signal 212 and a signal provided from the system management section, and reads the layer management status register 16. A 213.

Referring to the operation of the physical layer management unit as described above, the interrupt processing unit 11, when the HEC signal provided from the physical layer processing unit in synchronization with the system clock of the system management unit transitions from '0' to '1' The OCD signal transitions from '0' to '1' in consideration of a continuous HEC error, and simultaneously stores the OCD signal in the layer management state register 16.

The LCD processor 13 receiving the OCD signal outputs and drives a 4MS-CLR signal to the LCD timer 12 so that the LCD timer 12 transmits a 4MS signal every 4mS to the LCD processor 13 and the fault. Output to the timer 14. Therefore, after receiving the OCD signal, the LCD processor 13 outputs the LCD signal to the interrupt processor 11 and the failure processor 15 at the time when 4mS is delayed.

On the other hand, the failure processing unit 15 receiving the LCD signal outputs the LCD failure signal to the interrupt processing unit 11 in accordance with the 3S signal output by the failure timer 14 driven by the 4MS signal after 3S, When the LCD signal input from the LCD processor 13 returns to normal, the FAlL-CLR signal is output to the failure timer 14 to release the LCD failure signal in accordance with the 10S signal output by the failure timer 14 after 10S.

Therefore, the interrupt processing unit 11 is an OCD signal and an LCD signal inputted, and stores the interrupt of the LCD failure signal in the layer management state register 16 and according to the input / output control (R / W *) signal provided from the system manager. The layer management status information of the layer management status register 16 is outputted, and a TlMER-CLR signal is generated whenever the interrupt level is changed.

Referring to the operation according to the configuration block of the present invention, the interrupt processor 11, when the HEC signal provided from the physical layer processor transitions from '0' to '1' in synchronization with the system clock of the system manager, The OCD signal is interrupted from '0' to '1' and is stored in the layer management state register 16 in consideration of a continuous HEC error. In response to the input / output control (R / W *) signal provided from the system manager, the layer management status information of the layer management status register 16 is outputted, and a TIMER-CLR signal is generated whenever the interrupt level is changed.

In addition, the FAIL processing unit 15, which processes the LCD signal of the LCD processing unit 13, interrupts the change of the LCD signal when the external signal is notified to the CPU of the system management unit. 16) and stores the layer management information through the input / output control (R / W *) signal of the system manager.

The LCD timer 12 synchronized with the external system clock is driven by the 4MS-CLR signal of the LCD processing unit 13 or the TIMER-CLR signal of the interrupt processing unit 11 to start counting, and the count time interval becomes 4mS. The value of the 4MS signal is generated from the logic value '0' to '1' and the value is provided to the LCD processor 13.

When the LCD processing unit 13 synchronized with the external system clock receives the OCD signal from the interrupt processing unit 11, the LCD signal is generated from '0' to '4' when the 4MS signal provided from the LCD timer 12 is generated as '1'. 1 'is transmitted to the interrupt processing unit 11 and stored in the layer management state register 16. On the contrary, when the HEC signal is restored to normal in the physical layer processing unit, the LCD processing unit 13 is notified from the interrupt processing unit 11 that the OCD signal transitions from '1' to '0' and is provided from the LCD timer 12. The LCD signal transitions from '1' to '0' according to the 4MS signal to notify the interrupt processor 11 that the abnormal state has been recovered.

The FAIL timer 14 is driven when the 4MS signal is received from the LCD timer 12, and is set for the hierarchical management (here, it is set as follows but may be changed, the occurrence of LCD failure: 3S, LCD failure termination: 10S). According to the present invention, a count value is generated to generate the necessary 3S and 10S signals, and the count value is provided to the fault processor 15 and reset according to the FAIL-CLR signal provided from the fault processor 15.

The fault processor 15 drives the LCD processor 13 by receiving the LCD signal and the count value from the FAIL timer 14, and the LCD signal provided by the LCD processor 13 transitions from '0' to '1'. When the time period of the counter provided by the FAlL timer 14 becomes 3S, the 3S signal is generated as '1' and the LCD failure signal provided by the LCD processor 13 is set to '0' according to the 3S signal. Raised from 'to' 1. When the LCD failure signal is generated, it is transmitted to the interrupt processing unit 11 and the layer management status register 16 to notify the system management unit. On the contrary, if the LCD signal is normally recovered from '1' to '0' in the LCD processing unit 13, the FAIL processing unit 15 transitions from the LCD processing unit 13 to '0' to '0' and is normal. In response to the 10S signal provided from the FAlL timer 14, the LCD signal is transitioned from '1' to '0' and the abnormal state is returned. Notify.

The layer management state register 16 now stores the OCD signal of the interrupt processor 11, the LCD signal of the LCD processor 13, and the signal provided from the FAIL processor 15 to provide input / output control (R / W *) provides layer management status information according to the signal.

Therefore, the present invention constructed and operated as described above may cause a malfunction of a physical layer or a poor link state of a network, and an abnormal inflow of cells or transmission or reception of a cell for a predetermined time or a considerable time in a call connection setting with a counterpart. Since the error of the generated system can be occupied in a hierarchical unit, it is effective to manage the system efficiently through the hierarchical management function of the physical layer for the abnormal state in each system and link.

Claims (2)

Interrupts the HEC (Header Error Check) signal from an external physical layer processor to generate an Out Of Cell Delineation (OCD) signal and controls it when a continuous interrupt occurs. An interrupt processing means 11 for notifying, an LCD processing means 13 for generating a Loss of Cell Delineation (LCD) signal according to the OCD signal and notifying the interrupt processing means 11, and the LCD processing means 13 LCD timer means 12 for repeatedly counting a predetermined period of time, fault handling means 15 for notifying the interrupt processing means 11 of an LCD failure signal according to the LCD signal; A fault timer means 14 connected to the fault handler means 15 and the LCD timer means 12 for generating predetermined signals 3S and 10S for hierarchical management, and provided from the interrupt processor 1l. The physical layer layer management control device for a signal, characterized in that it comprises a layer management state register means (16) for outputting a layer management status information in accordance with the output control signal (R / W *) provided by the external system management. The control layer of claim 1, wherein the LCD processing means (13) is configured to generate an LCD signal and notify the interrupt processing means (11) while the OCD signal is continuously generated. Device.