JPH0329046A - Bus switching device for control system - Google Patents

Abstract

PURPOSE:To suppress the adverse influence due to occurrence of the abnormality to other members by measuring the time intervals for transmission of signals under process which are outputted in a fixed cycle from a control part which is executing a control process to a control subject and switching forcibly a bus switch circuit when the measured time interval exceeds the limit time. CONSTITUTION:When some abnormality occurs at a control part 11a which is carrying out a control process to a part 13 which is presently under control and a runaway state is produced and the runaway state lasts over a prescribed limit time TM, the part 11a is physically separated from the part 13 and another normal part 11b. As a result, the adverse influence given to the part 13 due to the runaway or the damage of the part 13 can be minimized. At the same time, the component members of a monitor timer circuit 16 are easily obtained with combinations of digital logic circuits. Thus it is possible to obtain a miniaturized and useful bus switching device with no extreme increase of the manufacturing cost.

Description

[Detailed Description of the Invention] [Object of the Invention] (Industrial Application Field) The present invention relates to a control system in which one controlled object is shared by a plurality of control units via a bus. The present invention relates to a bus switching device for a control system that uses a bus switching circuit to switch and connect to a designated control unit.

(Prior Art) In a control system using a computer or the like in which a plurality of control units share one controlled object, as shown in FIG. ), etc., are connected to a plurality of 11 lm units (bus masters) 2 and a controlled unit (pass slave) 3 as one controlled object.

In such a control system, when each control unit 2 controls the controlled unit 3 via the shared bus 1, bus access rights are exchanged between the control units 2 and the shared bus 1
The control unit 2 to use is determined. Therefore, only the control section 2 that has acquired the bus access right can control the controlled section 3.

Further, as shown in FIG. 5, instead of the shared bus 1, each control section 2 is provided with its own dedicated bus 4, and each dedicated bus 4 is connected to the controlled section 3 via a bus switching circuit 5. A central control system has also been proposed.

In such a control system, when one control section 2 controls the controlled section 3, the controlling section 2 i1'J
A switching signal a is applied to the bus switching circuit 5 from an external control device (not shown) that arbitrates requests for bus access rights from the controller 2 or each controller 2. The bus switching circuit 5 to which the switching signal a is inputted controls the control unit 2 to which the switching signal a designates the controlled unit 3.
Switch connection to dedicated bus 4 of Therefore, the switch-connected control section 2 can control the wave control section 3.

Using such a bus switching circuit 5! In the IJ control system, one control unit 2 receives data via its own dedicated bus 4! i While the control processing for the Ia unit 3 is being executed, the dedicated bus 4 of the other control unit 2 is physically separated from the controlled unit 3 and the dedicated bus 4 of the control unit 2 that is executing the control. Even if another control section 2 malfunctions and the control of the program 1 goes out of control, the control section 2 and the controlled section 3 that are currently undergoing control processing can continue the control processing normally.

Therefore, the control system of this method is employed in standby redundant systems and the like that require high reliability.

However, even in the bus switching device of the control system configured as shown in FIG. 5, the following problems still exist that need to be improved.

In other words, even if one control unit 2 goes out of control while another control unit 2 is performing control processing for the controlled unit 3 using its own dedicated bus 4, the controlled unit 3 There are no negative effects from running wild. However, if the control unit 2 connected via the bus switching circuit 5 and currently executing the control process malfunctions and goes out of control, the control unit 2 itself, for example, sends the switching signal a to the bus switching circuit 5. If the switching signal a is being sent, the switching signal a is not released, so the controlled section 3 maintains the state connected to the control section 2 in the runaway state. Therefore, not only will the driver control section 3 be adversely affected by the d-running, but if the control section 2 continues to run out of control for a long time, there is a concern that the driver control section 3 will be damaged.

(Problem to be Solved by the Invention) As described above, in the conventional bus switching device of the control system, when an abnormality such as runaway occurs in the control unit 2 currently connected to the controlled unit 3, the controlled unit 3 If the abnormal situation continues for a long time due to the adverse effects of the abnormal situation, there is a risk of damage.

Therefore, there is a problem that the reliability of the entire control system is reduced.

The present invention was made in view of these circumstances, and
By detecting the signal sending time interval of the processing signal outputted at a constant cycle from the control unit executing 'II1l processing on the controlled object, it is possible to detect when an abnormality occurs in the control unit.
The bus switching circuit can be switched immediately, the abnormality control section can be physically separated from the controlled object and other normal control sections, and the adverse effects of the abnormality on other components can be minimized, and the system An object of the present invention is to provide a bus switching device for a control system that can improve overall reliability.

[Configuration 1 of the Invention (1,000 steps to solve the problem) In order to solve the above problem, in the bus switching device of the control system of the present invention, one $ controlled object is connected to a plurality of control units via a bus. In a control system that is shared by The elapsed time elapses from the input time of the processing signal that is output at a fixed period from the control unit that controls the processing signal to the input time of the next processing signal, and the elapsed time is a limit time that is set longer than the specified period. A monitoring timer circuit is provided which sends a forced switching signal to the bus switching circuit when the bus switching circuit exceeds the threshold.

(Function) According to the bus switching device of the control system configured as described above, the control unit connected to the controlled object via the bus switching circuit executes predetermined control processing on the controlled object. ing. And while executing the control process,
Outputs a processing signal at regular intervals. The processing signal is input to the monitoring timer circuit. The monitoring timer circuit starts counting the elapsed time when one processing signal is input, and when the next processing signal is input, it clears the previous elapsed time and calculates the elapsed time from the newly input processing signal. Start timing. That is, as long as the processing signal is inputted at a constant cycle, the elapsed time will not exceed the limit time. Therefore, no forced switching signal is sent from the supervisory timer circuit to the bus switching circuit.

On the other hand, if an abnormality occurs in the control section that is executing predetermined control processing on the controlled object, the processing-in-progress signal is no longer output at each fixed period. Therefore, the elapsed time counted by the supervisory timer circuit exceeds the limit time, and a forced switching signal is sent from the supervisory timer circuit to the bus switching circuit. As a result, the control section in which the abnormality has occurred is forcibly separated from the controlled object and other normal control sections.

(Example) An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a schematic diagram showing a control system incorporating a bus switching device according to an embodiment. In this embodiment, there are two control units (bus masters) lla, 1. 1b, the controlled unit as one controlled object is connected via the bus switching circuit 12 (
(pass slave) 13. That is, each control unit 1
1a and 1.1b are respectively dedicated buses 14a. 14b is connected to the bus switching circuit 12, and the bus switching circuit 12
is connected to the controlled section 13 via a controlled section bus 15.

The bus switching circuit 12 is normally switched and controlled by a switching signal a output from each control section 11a, 11b. For example, when the switching signal a is in a low (L) level state, the controlled unit bus 15
and the dedicated bus 14a of the control unit 11a are connected, and the high (
H) In the level state, the controlled unit bus 15 and the dedicated bus 14b of the control unit 1lb are connected. Further, the bus switching circuit 12 forcibly switches and connects the currently connected dedicated buses 14a, 14b to the other dedicated buses 14b, 14a using the forced switching signal b outputted from the monitoring timer circuit 16.

Control unit 1. 1a, the own dedicated bus 14a is connected to the controlled unit 1 via the bus switching circuit 12 and the controlled unit bus 15.
3 and in the process of controlling the controlled unit 13, it outputs a pulse-like processing signal C at a constant cycle To to indicate that it is currently occupying the controlled unit 13. do. This processing signal C is then applied to the monitoring timer circuit 16. Similarly, the other control unit 1lb also operates the controlled unit 13 at a constant period T during the control processing period. The processing signal d is sent to the monitoring timer circuit 16.

FIG. 2 is a detailed circuit block diagram of the bus switching circuit 12 and the monitoring timer circuit 16.

The bus switching circuit 12 has the same configuration as the output signal selector 12.
A and an input signal selector 12b, dedicated buses 14g and 14b are connected to the signal terminals A and B of each signal selector 12a and 12b, respectively, and a controlled unit bus 15 is connected to the common terminal C. has been done. In addition, control terminal G
The switching signal a is input to the terminal G2, and the forced switching signal b is input to the control terminal G2. And each control terminal G,,G2
The common terminal C is switched and connected to the signal terminal AI when the switching signal a and the forced switching signal b applied to the terminal are at the L level, and the common terminal C is switched and connected to the signal terminal B when the switching signal a and the forced switching signal b applied to the terminal are at the H level.

Also, one control unit 1 inputted to the monitoring timer circuit 16
The processing center signal C from 1a is applied to the reset terminal R of the counter 18 via an AND gate 17a and an OR gate 17b in the signal selection circuit 17. Further, the processing center number d from the other control section 1lb is transmitted to the AND gate 17c in the signal selection circuit 17 and the OR gate 1. 7b to the reset terminal R of the counter 18.

A clock oscillator 1 is connected to the clock terminal CP of the counter 18.
A clock signal e is applied from 9. Then, the counter 18 counts the number of clocks of the input clock signal e. When the clock number reaches a count value corresponding to a limit time TM set longer than the cycle T0 of each processing signal c, d, an 11-level count-up signal f is sent from the output terminal Q to the next flip-flop 20. Trigger terminal T
Send to. In addition, if an H level reset signal is input to the reset terminal R during counting, the counted value is cleared and
Counting of the clock signal e is started from the beginning of kk.

When the H-level count-up signal f is input to the trigger terminal, the flip-flop 20 forcibly inverts the signal level of the output signal at the output terminal Q. Therefore, the output signal of this output terminal Q is sent to the bus switching circuit 12 as the forced switching signal b.
sent to.

Further, the output signal at the output terminal Q of the flip-flop 20 is directly inputted to the other input terminal of the AND gate 17b, and is also inputted to the other input terminal of the AND gate l7a via the inverter i7d.

Next, the operation of the bus switching device of the control system configured as described above will be explained.

When the control section 11a executes control processing on the controlled section 13, first, the switching signal a is set to L level and the control terminal G of each signal selector 12a, 12b in the bus switching circuit 12 is set to L level.
, to L level. Then, the common terminal TC becomes the signal terminal A.
connected to. At the same time, the other control terminal G2 also changes to L level.

Therefore, the control unit 1 1. 3 is connected to the controlled unit 13, the control unit 11a starts control processing for the controlled unit 13 and outputs the processing signal C at a constant period T0. The output processing signal C is sent to the monitoring timer circuit 1.
6 is input to the AND gate 17a. Note that since the L level signal of the control terminal G2 is inverted by the inverter 17d and applied as an H level signal to the other input terminal of the AND gate 117a, the processing signal C is applied to the AND gate 17.
a, applied to the reset terminal R of the counter 18 via the OR gate 17b. As a result, the count value of the counter 18 is cleared and counting of the number of clocks of the clock signal e is started again.

Then, since the next processing signal C is input before the limit time TM is reached, the count value is cleared again. Therefore, the count-up signal f is never output from the counter 18. As a result, the bus switching circuit 12 receives the switching signal a.
The switching state specified by is maintained.

When the control unit 11a has reached the control processing power for the controlled unit 13, it switches the switching signal a to H level and disconnects its own dedicated bus 14a from the controlled unit 13.

At the same time, the processing signal C, which has been output at regular intervals, is stopped. As a result, the switching circuit 12 switches to the other control section 1lb side, and the signal level of the control terminal G2 also changes to H level. Therefore, this time, the control unit 1lb sends a female to the controlled unit 13.
1 control processing becomes possible. Then, the processing signal d is sent from the control unit 1lb to the monitoring timer circuit 16. The counter 18 has an AND gate 17c and an OR gate 17.
It is reset by the processing signal d input via b.

In this way, when the control units 11a and llb are operating normally, the forced switching signal b is not output from the monitoring timer circuit 16, so the bus switching circuit 12
Switching is controlled only by switching signal a output from llb.

Next, for example, if some abnormality occurs in the control unit 11a and the control unit 11a goes into a runaway state while the control unit 11a is performing control processing on the controlled unit l3, the control processing is executed from the control unit 11a. The switching signal a for switching the controlled section 13 to another control section 1lb upon completion of the control is never output. Further, the output of the processing signal C is stopped.

When the processing signal C is interrupted, the counter 18 is no longer reset, and at the point where the elapsed time from the output time of the processing signal C output during normal operation exceeds the limit time TM, the output terminal Q of the counter 18 becomes H. A level count-up signal f is output.

Therefore, the flip-flop 20 operates to strongly invert the signal level at the output terminal Q of the flip-flop 20 from the L level to the H level.

Therefore, the forced switching signal b changing from the L level to the H level is sent from the monitoring timer circuit 16 to the bus switching circuit 12, and the signal level of the control terminal G2 is forced to change to the H level. As a result, the common terminal C is switched and connected to the signal terminal B side. At the same time, the signal level of the control terminal G changes to H level.

Therefore, since the controlled unit 13 is connected to the normal control unit 1lb, the control unit 1lb can start normal control processing for the controlled unit 13.

Note that if the control section 1lb goes out of control during control processing for the controlled section 13, the bus switching circuit 12 is forcibly switched and the control section 1. 1. b is physically separated from the control section 13 and the other control section 11a.

In this way, if some abnormality occurs in the control section 11a that is currently executing control processing for the controlled section 13 and the control section 11a enters a runaway state, the duration of the runaway state exceeds the predetermined limit time TM. Then, the corresponding control section 11a is physically separated from the controlled section 13 and other normal control sections 11l).

Therefore, it is possible to minimize the possibility that the controlled section 13 is adversely affected or damaged due to runaway. As a result, the reliability of the entire control system can be significantly improved.

Further, as shown in the figure, each component constituting the monitoring timer circuit 16 is constructed using a simple combination of digital logic circuits.
t, it is possible to provide a small and useful bus switching device without significantly increasing manufacturing costs.

Furthermore, due to the nature of the timer circuit, each control section 11a, 1lb
Even if the supervisory timer circuit 16 is affected by pulse noise, which is the main cause of abnormalities in the be. And the other normal waiting! Since the lj control units 1lb and lla can control the controlled unit 13, it is possible to prevent malfunctions caused by the pulse noise from having a fatal effect on the operation of the control system.

FIG. 3 is a schematic diagram showing a bus switching device incorporated in a control system in which three or more control units 21 share one controlled unit 13 via the bus switching circuit 22. Each control section 21
Each dedicated bus 23 is connected to each switching terminal of the bus switching circuit 22, and the controlled unit bus 15 is connected to the common terminal. Normally, the bus switching circuit 22 switches and connects the controlled unit 13 to the control unit 21 specified by the switching signal h output from each control unit 21, but the monitoring timer circuit 24 switches the controlled unit 13 to the control unit 21 specified by the switching signal h output from each control unit 21.
When the signal g is input, the common end f is connected to the empty switching end f.

The monitoring timer circuit 24 receives a constant period T. A processing signal i is input. Then, when the processing signal i is interrupted, the forced switching signal g is sent to the bus switching circuit 22.

Even if the bus switching device is configured in this way,
When the control section 21 that is undergoing control processing becomes out of control, the bus switching circuit 22 operates to switch the control section 21 that is out of control to the controlled section 1.
3 and other normal control units 21, it is possible to obtain almost the same effect as in the previous embodiment.

In this case, if an abnormality occurs in the control section 21, the control section 13 enters a standby state in which it is not connected to any control section 21, so the switching signal h is sent again from the normal control section 21. It is necessary to switch and connect the controlled section 13 to the control section 21 to be controlled. In other words, the control section 21 that is running out of control may cause the switching signal h to connect the controlled section 13 to the wrong control section 21.
Even if the controlled unit 13 is outputted, the controlled unit 13 is prevented from being connected to the wrong control unit 21. [Effect of the Invention] As explained above, the bus switching of the control system of the present invention According to the device, the signal escape time interval of the processing signal outputted at a constant cycle from the control unit that executes control processing on the controlled object is measured, and when the time interval exceeds a limit time, the bus The switching circuit is being forced to switch. Therefore, if an abnormality occurs in the control unit that executes control processing by sending a statement to the controlled object, the bus switching circuit will immediately perform a switching operation.
The abnormality occurrence control section can be physically separated from the controlled object and other normal control sections, and the adverse effects on other members caused by the occurrence of the abnormality can be minimized, and the reliability of the entire control system can be improved.

[Brief explanation of drawings]

FIG. 1 is a schematic diagram showing the general configuration of a control system incorporating a bus switching device according to an embodiment of the present invention, FIG. 2 is a block diagram showing the main parts of the same embodiment, and FIG. 3 is a diagram showing the invention. FIG. 4 is a block diagram showing a general control system, and FIG. 5 is a schematic diagram showing a conventional bus switching device. It is a diagram. 11a, llb, 21-...control unit, 12.22...
Bus switching circuit, 13... control unit, 14a514b.
... Dedicated bus, 16.24 ... Monitoring timer circuit, 17
...Signal selection circuit, 18...Counter, 19...
Clock oscillator, 20... flip-flop, a, h
...Switching signal, b, g...Forced switching signal, c, d,
i...Processing signal.

Claims (1)

[Claims] In a control system in which one controlled object is shared by a plurality of control units via a bus, the controlled object is selectively connected to a control unit inserted in the bus and designated by an input switching signal. The bus switching circuit and the elapsed time from the input time of the processing signal that is output at regular intervals from the control unit currently controlling the controlled object via the bus switching circuit to the input time of the next processing signal. A bus switching device for a control system, comprising: a monitoring timer circuit that sends a forced switching signal to the bus switching circuit when the elapsed time exceeds a set limit time longer than the certain period.