JPH04133162A - Operation monitor for processor - Google Patents

Abstract

PURPOSE:To surely stop the operation at the time of abnormality by informing the abnormality by applying an interruption to a processor of the subordinate side by an output of a watch dog timer of the superordinate side, at the time or monitoring the operation of two processors, and also, resetting both the processors in the case an abnormality time counting time becomes a prescribed time. CONSTITUTION:A first and a second processors 10, 20 operate cooperatively through an interface 30. A watch dog timer (WD) 11 applies an interruption to a second processor 20 at the time of abnormality, informs generation of the abnormality, and also, resets a first processor 10. Also, by this abnormality signal, a counter 12 is allowed to start time counting. In the case of abnormality by which the processor 10 cannot be reactuated, the WD 11 is not reset, and the counter 12 continues to count. When the counter 12 reaches a prescribed value, a latch circuit 14 is set, and the processors 10, 20 are reset, both reach an operation stop.

Description

Detailed Description of the Invention [Field of Industrial Application] The present invention relates to a device that monitors the operation of two processors. The present invention relates to an operation monitoring device for stopping the operation of a machine.

[Conventional technology]

Figure 3 shows a conventional operation monitoring device of this type (for example,
116739), and is shown together with two processors to be monitored. The first and second processors 10.20 exchange data via the interface 30 and operate cooperatively.
is positioned at the upper level, and the second processor 20 is positioned at the lower level. 1st. Each of the second processors 10.20 is provided with a watchdog timer 11.21. When the second processors 10 and 20 each receive a pulse signal emitted at a predetermined period at the reset terminal R, the time measurement contents are reset, whereas the pulse signal from the first processor 10.20 is reset. When the second processor 10.20 interrupts due to an abnormality, the watchdog timer 11.21 issues a signal indicating completion of time measurement set in each watchdog timer 11.21, and this signal is transmitted to the first. second processor 1
0.20 is applied to the reset terminal R, and the first . The second processor 10.20 is thereby reset.

The time completion signal or abnormality notification signal of the watchdog timer 21 is also applied to the interrupt terminal INT of the first processor 10 to interrupt it. As a result, the first processor 1
0 can know the abnormality of the second processor 20.

Furthermore, the first processor 10 is configured to be able to reset the watchdog timer 21 and the first processor 20 via OR circuits 22 and 23.

[Problem to be solved by the invention]

In such a conventional operation monitoring device, the second processor 20
The abnormality that occurs in the
If an abnormality occurs in the processor 0, the operation can be stopped, but the second processor 20 continues to operate, and there is a problem in that the second processor 20 continues to perform an incomplete operation.

The present invention has been made to solve these problems, and has a structure in which when an abnormality occurs in a higher-level processor, this is notified to a lower-level processor. It is an object of the present invention to provide an operation monitoring device which eliminates the inconvenience of only the lower processor operating by making it possible to reset both processors if the problem is not resolved.

[Means to solve the problem]

The operation monitoring device according to the present invention interrupts the processor on the lower side by the output of the watchdog timer on the upper side, and also includes means for measuring the time of the abnormality notification signal outputted by the watchdog timer. , and means for resetting both processors when the measured time reaches a predetermined time.

[Effect]

When an abnormality occurs in the upper processor, a signal output from the watchdog timer interrupts the lower processor, and the lower processor is notified of the abnormality in the higher processor. In addition, the time during which the above signal is output is measured, and when this reaches a predetermined time, both processors are reset.
stop working together.

〔Example〕

FIG. 1 is a detailed diagram of the operation monitoring device of the present invention, and shows the first . Shown together with a second processor 10.20. 1st. The second processors 10 and 20 transmit and receive data via the interface 30 and operate cooperatively, with the first processor IO being positioned at the upper level and the second processor 20 at the lower level. First (second) processor 1
The pulse signal periodically generated by the watchdog timer IH21) is applied directly (via the OR circuit 22) to the reset terminal R of the watchdog timer IH21).

The timing completion signal or abnormality notification signal of the watchdog timer IH21) is given to the reset terminal R of the first (second) processor 10 (20)' via the OR circuit 15 (23), and Processor 20 (10)
is directly applied to the interrupt terminal rNT of the interrupt terminal rNT. 1st processor 1
0 issues a forced reset signal, and this signal is sent to the OR circuit 16.
22 to the reset terminal R of the watchdog timer 21, and via the OR circuit 16.23 to the reset terminal R of the second processor 20.

The abnormality notification signal generated by the watchdog timer 11 is input to the counter 12 for measuring the time of the signal, and while the signal is being input, the counter 12 is inputted to the clock circuit 1.
3. Measure the clock issued by 3. The counter 12 is a recent counter that is set to a value corresponding to a time longer than the time limit of the watchdog timer 11, and when the counted value reaches this value, that is, when the time measurement content reaches the time corresponding to this value, Issues a timing completion signal. This signal is given to the launch circuit I4, and the latch circuit I4 holds it and gives it to the reset terminal R of the 110th processor 10, and also sends it to the second processor 20 via the OR circuit 16.23.
is applied to the reset terminal R of.

Next, the operation of the apparatus of the present invention having the above configuration will be explained.

FIG. 2 is a flowchart showing the operation of this device,
The left side shows the operation of the first processor 10, and the right side shows the operation of the second processor 20.

In the flowchart on the right, when the second processor 20 is operating normally (S15), the watchdog timer 21 is periodically reset (YES), but when it is not reset (NO), the watchdog timer 2
1 outputs an abnormal signal (S17). Then, an interrupt is made to the first processor 10 (518) to notify it of the occurrence of an abnormality, and the second processor 20 is reset and restarted (519).

On the other hand, on the first processor 10 side, if it is operating normally (Sl), the watchdog timer II is periodically reset (YES), but if it is not reset (No), the watchdog timer 11 is An abnormal signal is output (S3). Then, an interrupt is issued to the second processor (S4) to notify it of the occurrence of an abnormality, and the first processor 10 is reset and restarted (S5). On the other hand, an abnormal signal causes the counter 12 to start counting. When the operation of the first processor IO returns to normal due to restart, the watchdog timer 11 is reset (S7.YE).
S) The abnormal signal of the watchdog timer 11 disappears, and the counter 12 stops counting and is reset (S8).

If the first processor 10 is abnormal and cannot be restarted, the watchdog timer 11 will not be reset. In this case (S7.No), steps S91 to S93 similar to 33 to S5 are performed. This process is repeated until the count of the counter 12 reaches a predetermined value, and when it reaches the predetermined value (S1
0), the counter 12 issues a timing completion signal (Sll)
. This sets the latch circuit 14 (S12).
, 1st. The second processor 10.20 is reset and together come to a standstill.

In the above-described embodiment, the case where two processors are to be monitored has been described, but the same configuration can be applied when there are a plurality of upper and/or lower processors.

〔Effect of the invention〕

According to the present invention as described above, even if an abnormality occurs in any of the processor sensors, it is possible to interrupt the other processor to notify the other processor of the abnormality, and it is possible to perform processing corresponding to the abnormality in the other sensor.

For example, if an abnormality occurs in the upper processor that cannot be recovered by resetting or restarting, both processors can be reset and stopped.

This eliminates the inconvenience of one processor continuing to operate despite an abnormality in another processor.
Highly reliable devices and systems can be realized.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an operation monitoring apparatus according to the present invention, FIG. 2 is a flowchart showing its operation, and FIG. 3 is a block diagram of a conventional operation monitoring apparatus. 10...First processor 11.21...Watchdog timer 12...Counter 14...Launch circuit 20...Second processor Note that in the drawings, the same reference numerals indicate the same or equivalent parts. Agent Masuo Oiwa

Claims (1)

[Claims] (1) A watchdog timer is provided for each of the two processors, and the watchdog timer for one processor interrupts the other processor with a signal issued when the one processor is abnormal. In the processor operation monitoring device, the watchdog timer for the other processor interrupts the one processor with a signal generated when the other processor has an abnormality, and when the signal is generated, the watchdog timer interrupts the one processor. 1. A processor operation monitoring device comprising: means for measuring a predetermined time; and means for resetting both processors when the means measures a predetermined time.