JPH06295291A - Multiprocessor semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To suppress the increase of the chip area and to realize the cooperative operation between plural CPUs by providing the device with a means which detects the abnormality of execution of control programs in CPUs to send an abnormality signal to CPUs. CONSTITUTION:Plural CPUs 14 and 22 and the means which detects the abnormality of execution of control programs in CPUs to send the abnormality signal to CPUs are provided. That is, counters 15 and 23 make signals and in the case of which are sent to latches 16 and 24, different in the case of normalcy abnormality of execution of control programs in CPUs, and a fail counter 18 sends the abnormality signal if one of CPUs 14 and 22 is abnormally operated. Since one fail counter 18 is provided for two CPUs 14 and 22, the increase of the chip area is suppressed. Further, latches 16 and 24 are provided and signals stored there are supplied to CPUs 14 and 22 to recognize the abnormally operating CPU.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multiprocessor semiconductor integrated circuit device having, for example, two central processing units (hereinafter referred to as CPUs).

[0002]

2. Description of the Related Art Conventionally, a one-chip microcomputer provided with, for example, two CPUs has a separate circuit configuration for each of CPU1 and CPU2, as shown in FIG. That is, if the control program of the CPU 1 runs out of control on the output side of the CPU 1,
The fail counter 2 for controlling the runaway of the control program 1 is connected to the output side of the CPU 2, and the fail counter 5 for controlling the runaway of the control program of the CPU 2 is connected to the output side of the CPU 2. Yes, each CPU independently controlled the runaway. The output side of each fail counter 2, 5 is fed back to each CPU 1, 4.

In the conventional one-chip microcomputer having two CPUs, each CPU is
Since a fail counter is provided for each, there is a problem that the chip area increases due to an increase in the number of fail counters, and even if one CPU is in a runaway state, the other CPU cannot recognize it. However, there is also a problem that the other CPU cannot perform, for example, acting on behalf of a CPU in a runaway state, and cooperative operation between the two CPUs cannot be performed. The present invention has been made to solve such a problem, and an object of the present invention is to provide a multiprocessor CPU that suppresses an increase in chip area and enables cooperative operation among a plurality of CPUs.

[0004]

According to the present invention, a plurality of central processing units and an execution of a control program in at least one of the central processing units connected to the output side of the central processing unit are connected. Detection means for detecting an abnormality and sending an abnormality signal to each of the central processing units.

[0005]

With this structure, the detecting means is provided for each of the plurality of CPUs, and therefore acts to suppress the increase in the chip area.

The detecting means are connected to the output sides of the respective central processing units, and when the central processing units are operating normally, a plurality of first signals are sent out in synchronization with each other at predetermined time intervals. No. 1 signal sending means and all of the output sides of the respective first signal sending means are connected, and the second signal sends out the clear signal only when a constant signal is supplied from all of the first signal sending means. A transmitting means and an output side of the second signal transmitting means,
When the clear signal is supplied because the control program is normally executed in each of the central processing units, the count value by the counting operation is cleared and no abnormal signal is sent, while the central processing unit When the clear signal is not supplied because the control program is abnormally executed in at least one of them, the counting operation is continued, and when the count value by the counting operation reaches the set count value, the abnormality signal is output to each of the central portions. Third signal sending means for sending to the arithmetic processing unit, and is connected between the output side of the first signal sending means and the input side of the second signal sending means,
A storage means for storing the signal transmitted by the first signal transmission means and transmitting the stored signal to each of the central processing units may be provided.

With this arrangement, the first signal sending means makes the signals sent to the storing means different depending on whether the execution of the control program in the CPU is normal or abnormal. Therefore, by sending a storage signal from the storage means to each CPU, each CPU can recognize in which CPU the execution of the control program is abnormal.

[0008]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a multiprocessor semiconductor integrated circuit device of the present invention will be described below with reference to the drawings. Figure 1
Shows a multiprocessor semiconductor integrated circuit device provided with two CPUs. The WACLR signal output terminal of the CPU 14 is connected to the input terminal D of the counter 15, which corresponds to the first signal sending means, and the CK signal output terminal of the CPU 14 is connected to the input terminal CK of the counter 15. Similarly, the WBCLR signal output terminal of the CPU 22 is
The CK signal output terminal of the CPU 22 is connected to the input terminal D of the counter 23, which corresponds to the first signal transmitting means, and the CK signal output terminal of the CPU 22 is connected to the input terminal CK of the counter 23. These counters 15 and 23 count the clock signals supplied from the CPUs 14 and 22, and the count value obtained by the counting operation is counted by the CPU.
When the WACLR signal and the WBCLR signal are supplied from 14 and 22, the above-mentioned count value is cleared, and by clearing the count value, for example, a high (H) level signal is transmitted. In addition, CPU
The clock signals sent from 14 and 22 are synchronized with each other.

The WACLR signal and the WBCLR signal are used when the control program is executed in the CPUs 14 and 22 at a rate of, for example, 1 msec / 1 (hereinafter,
Such a case is referred to as "normal operation", and is sent at a predetermined time interval, for example, every 1 msec, while one execution is not completed within the above 1 msec (hereinafter, such a case is referred to as " Called "abnormal operation" or "runaway"). Therefore, the CPU 14, 2
2 is operating normally, the counters 15 and 23
An H or low (L) signal is sent from the output terminal Q of the CPU at a predetermined time interval.
When U14 and 22 are operating abnormally, H or L signals are continuously output from the output terminals Q of the counters 15 and 23. The count values of the counters 15 and 23 are
It is forcibly cleared by the output signal of the AND circuit 17 described later.

The output terminal Q of the counter 15 is connected to the latch 16
2-input AND corresponding to the second signal transmitting means via
The output terminal Q of the counter 23 is connected to one input terminal of the circuit 17, and the other input terminal of the two-input AND circuit 17 corresponding to the second signal transmitting means is connected via the latch 24. Therefore, the latch 16 stores the output signal sent from the counter 15, and the latch 24 stores the counter 23.
The output signal sent by is stored. The output terminal of the stored signal in the latch 16 is connected to the WASTA input terminal of the CPU 14 and the WASTA input terminal of the CPU 22, and the output terminal of the stored signal in the latch 24 is the WB of the CPU 14.
It is connected to the STA input terminal and the WBSTA input terminal of the CPU 22.

As described above, since the clock signals sent from the CPUs 14 and 22 are synchronized, the latches 16 and 24 send the CPUs 14 and 22 to each other when the CPUs 14 and 22 are operating normally. Although the same synchronized signals are sent out, when the CPUs 14 and 22 are operating abnormally, the signal levels sent from the latches 16 and 24 to the respective CPUs are different. or,
Since the latches 16 and 24 are provided so that the stored signals are supplied to the respective CPUs, the CPUs 14 and 22 can recognize the stored signals of both the latches 16 and 24, and the CPUs 14 and 22 will not recognize each other. CP
It is possible to recognize whether U is performing an abnormal operation.

In the AND circuit 17, as described above, the C
Latch 1 when the PUs 14 and 22 are operating normally
Since the signals of 6 and 24 are supplied in synchronism and at the same level, the AND circuit 17 causes the CPU 14,
An H level clear signal is sent only when 22 is operating normally.

The output side of the AND circuit 17 has an input terminal D1 of a fail counter 18 corresponding to the third signal sending means.
Connected to. The fail counter 18 has the configuration shown in FIG. That is, the fail counter 18 corresponds to a counting unit that performs a counting operation of the clock signal supplied from the connected timer circuit 33 and clears the count value obtained by the counting operation by the output signal of the AND circuit 17. Through the counter 30 and the selection circuit 25
4, the counter 32 can set the count value, and corresponds to the set count value storage means, and the counter 30 and the output side of the compare 32 are connected to each other and compare with the count value supplied from the counter 30. 32 is compared with the set count value supplied from 32, and when the count value supplied from the counter 30 exceeds the set count value,
It is provided with a comparator 31 which sends out an abnormal signal indicating that the CPU 14 or 22 or the CPUs 14 and 22 are operating abnormally.

In such a fail counter 18, as described above, the AND circuit 17 includes the CPUs 14 and 22.
Since a clear signal of H level is transmitted only when both are normally operating, the count value of the counter 30 is cleared every predetermined time, and the count value of the counter 30 is compared with the compare 3 value.
The fail counter 18 does not send an abnormal signal when the set count value of 2 is exceeded. On the other hand, since the count value of the counter 30 is not cleared when the CPUs 14 and 22 are abnormally operating, the count value is counted up, and the count value may exceed the set count value. Therefore C
When the PU 14 or 22 or the CPUs 14 and 22 are operating abnormally, the fail counter 18 sends an abnormal signal.

The selection circuit 25 has the configuration shown in FIG. 3, and when the CPU 14 sets the set count value to the compare 32, for example, an H level CPA signal is sent from the CPU 14 and the CPU 22 outputs an L level signal. When the CPB signal is transmitted, an H level signal is transmitted from the AND circuit 34 to the AND circuit 35, and the AND is performed corresponding to the CPADATE signal supplied from the CPU 14 to the AND circuit 35.
A signal is supplied from the circuit 35 to the compare 32. CPU
The case of setting the set count value at 22 is similar to the above case.

The output side of the fail counter 18 is a CPU
It is connected to each of the CPUs 14 and 22 through a mask means 26 that masks the supply of the abnormal signal to the CPUs 14 and 22. The mask means 26 has the circuit configuration shown in the figure. That is, the abnormal signal is supplied from the fail counter 18 to one input terminal of the 2-input AND circuit 11, and the CPU connected to the latch 16 to the other input terminal of the AND circuit 11.
A signal is supplied from 14 WASTA terminals. The fail counter 18 is connected to the input terminal of the 3-input AND circuit 12.
The above-mentioned abnormality signal is supplied from the WAMSK of the CPU 14
The WAMSK signal is supplied from the signal output terminal, and the output signal of the AND circuit 11 is inverted and supplied. A like this
The output sides of the ND circuits 11 and 12 are connected to the WAIT input terminal of the CPU 14 via the OR circuit 13.

Similarly, for the CPU 22, a 2-input A
The abnormal signal is supplied from the fail counter 18 to one input terminal of the ND circuit 19, and the WBST of the CPU 22 connected to the latch 24 to the other input terminal of the AND circuit 19.
A signal is supplied from the A terminal. 3-input AND circuit 20
The abnormal signal is supplied from the fail counter 18 to the input terminal of, and the WBMSK signal is supplied from the WBMSK signal output terminal of the CPU 22, and the output signal of the AND circuit 19 is inverted and supplied. Such an AND circuit 19,
The output side of 20 is the W of the CPU 22 via the OR circuit 21.
Connected to BINT input terminal.

The mask means 26 thus constructed is
For example, when the CPU 14 never operates abnormally or may operate abnormally, for example, the CPU
By sending the WAMSK signal from 14, the fail signal is not supplied to the CPU 14 even if the fail signal is sent from the fail counter 18.

The operation of the multiprocessor semiconductor integrated circuit device configured as described above will be described below. First, a case where the CPUs 14 and 22 are operating normally will be described. The CPUs 14 and 22 are, for example, programs 1
Execution shall be processed within 1 msec. For example, C
When the PU 14 is processing the program within the above 1 msec, the counter 15 displays the CP about every 1 msec.
Since the count value is periodically cleared by the WACLR signal supplied from U14, and the counter 15 sends an H level signal, for example, when the count value is cleared, the counter 1
5 periodically sends out H and L level signals to the AND circuit 17 through the latch 16. These operations are performed by the CPU 22
Is the same.

Since the clock signals sent from the CPUs 14 and 22 and the signals sent from the counters 15 and 23 are synchronized, the AND circuit 17 is periodically set to the H level via the latches 16 and 24. Are simultaneously supplied, so that the AND circuit 17 periodically sends out an H level clear signal to the counter 30 constituting the fail counter 18. The counter 30 periodically clears the count value that is being counted up by the supply of the clear signal, so that the count value supplied from the counter 30 in the comparator 31 exceeds the set count value supplied from the compare 32. In other words, the comparator 31 does not send an abnormal signal to the CPUs 14 and 22.

Next, one of the CPUs 14 and 22
Or if both are operating abnormally, CP
A case where U14 is operating abnormally will be described as an example.
Further, it is assumed that the compare 32 in the fail counter 18 stores data of a set count value of 5 msec, for example. The program execution in the CPU 14 is 5 m above
When the processing is performed for more than sec, the CPU14 does not send the WACLR signal to the counter 15 because the processing does not end, and the counter 15 continues to count up the count value by the counting operation. Therefore, the counter 15 continues to send the L-level signal, for example, and the AND circuit 17 does not send the H-level clear signal to the counter 30 provided in the fail counter 18.

Therefore, the counter 30 continues to count up the count value by the counting operation, and the value is supplied to the comparator 31. Therefore, the comparator 31
When the count value supplied from the counter 30 exceeds the value of "5 msec" supplied from the compare 32, an abnormal signal is sent to the CPUs 14 and 22. Where the CPU
When the 14 or the like does not send the WAMSK signal and the WBMSK signal to the mask means 26, the above-mentioned abnormal signal is sent to the CPU 1
4 and 22. The above-mentioned abnormal signal is masked and not supplied to the CPU that is sending WAMSK or the like.

Further, since the latch 16 sends the L level signal which is the output signal of the counter 15 to the CPUs 14 and 22, both the CPUs 14 and 22 can recognize that the CPU 14 is operating abnormally. Therefore, the CPUs 14 and 22 can take appropriate measures against the abnormal operation of the CPU 14.

As described above, in the multiprocessor semiconductor integrated circuit device of this embodiment, since one fail counter 18 is provided for the two CPUs 14 and 22, the increase of the chip area can be suppressed, and the latch 16 is further provided. ，
Since 24 is provided and the stored signal is supplied to the CPUs 14 and 22, the CPUs 14 and 22 can recognize the CPUs that are abnormally operating, and each CPU appropriately and cooperatively responds to the abnormal operation. can do.

In the above description of the operation, the case where the CPU 14 operates abnormally is taken as an example, but the CPU 22 or the CPU 1
The present apparatus operates similarly when both 4 and 22 are abnormally operated.

In the above embodiment, two CPUs are shown. However, the present invention is not limited to this, and when three or more CPUs are provided, the circuit configuration is the same as in the above embodiment and the CPUs operate in the same manner. be able to. As an example of the circuit configuration in this case, a counter shown in the counter 15 and a latch shown in the latch 16 are connected to the output side of the CPU, and the output side of the latch is connected to the AND circuit 17. Also, CPU
A mask means can be provided on the input side of.

[0027]

As described in detail above, according to the present invention, since one detecting means is provided for a plurality of CPUs, it is possible to suppress an increase in chip area.

Further, the present invention comprises the structure shown in claim 3,
Furthermore, the configuration according to claim 4 may be provided, and according to such a configuration, the first signal transmission means is stored in the storage means depending on whether the execution of the control program in the CPU is normal or abnormal. By differentiating the signals to be sent out, so that the storing signal is sent out from the storing means to each CPU, each CPU can recognize in which CPU the execution of the control program is abnormal.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a configuration of an embodiment of a multiprocessor semiconductor integrated circuit device of the present invention.

FIG. 2 is a block diagram showing a configuration example of a fail counter shown in FIG.

FIG. 3 is a logic circuit diagram showing a configuration example of a selection circuit shown in FIG.

FIG. 4 is a block diagram showing a configuration of a conventional dual processor.

[Explanation of symbols]

14 ... CPU, 15 ... Counter, 16 ... Latch, 17 ...
AND circuit, 18 ... Fail counter, 22 ... CPU,
23 ... Counter, 24 ... Latch, 25 ... Selection circuit, 26
... masking means, 30 ... counter, 31 ... comparator,
32 ... Compare.

Claims (5)

[Claims] 1. A plurality of central processing units and an output side of the central processing unit, which detects that the execution of a control program in at least one of the connected central processing units is abnormal. A multiprocessor semiconductor integrated circuit device, comprising: detection means for sending an abnormal signal to each of the central processing units. 2. A mask means connected between the output side of the detecting means and the input side of each of the central processing units to mask the supply of the abnormal signal to the central processing units. 1. The multiprocessor semiconductor integrated circuit device according to 1. 3. The plurality of detecting means are respectively connected to the output sides of the respective central processing units, and when the central processing units are operating normally, a plurality of predetermined signals are transmitted in synchronization with each other at a constant time interval. The first signal transmitting means and the output sides of the respective first signal transmitting means are all connected, and the clear signal is transmitted only when a constant signal is supplied from all the first signal transmitting means. Connected to the output side of the second signal sending means of the second signal sending means, and when the clear signal is supplied by the normal execution of the control program in each of the central processing units, the counting operation is performed. The clear signal is supplied when the control program is abnormally executed in at least one of the central processing units, while the count value is cleared and the abnormal signal is not transmitted. If not, the third signal sending means is provided for continuing the counting operation and sending an abnormal signal to each of the central processing units when the count value obtained by the counting operation reaches the set count value. Alternatively, the multiprocessor semiconductor integrated circuit device according to item 2. 4. A signal which is connected between an output side of the first signal sending means and an input side of the second signal sending means and which stores and stores a signal sent by the first signal sending means. 4. The multiprocessor semiconductor integrated circuit device according to claim 3, further comprising storage means for sending a signal to each of said central processing units. 5. The third signal sending means is connected to the output side of the second signal sending means, and the second signal sending means is connected to the output side of the second signal sending means.
Either the counting means for continuing the counting operation until the clear signal is supplied from the signal sending means, and clearing the count value by the counting operation by supplying the clear signal, and the central processing unit Connected to the output side of, and connected to the output side of the counting means and the setting count value storage means, setting count value storage means for storing the set count value that can be set in any one of the central processing unit, 4. The comparing means for comparing the count value supplied from the counting means with the set count value supplied from the set count value storage means, and sending out the abnormal signal when they match each other. Multiprocessor semiconductor integrated circuit device.