KR100223983B1 - Collision protecting circuit - Google Patents
Collision protecting circuit Download PDFInfo
- Publication number
- KR100223983B1 KR100223983B1 KR1019960074763A KR19960074763A KR100223983B1 KR 100223983 B1 KR100223983 B1 KR 100223983B1 KR 1019960074763 A KR1019960074763 A KR 1019960074763A KR 19960074763 A KR19960074763 A KR 19960074763A KR 100223983 B1 KR100223983 B1 KR 100223983B1
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- South Korea
- Prior art keywords
- computer
- register
- cpu
- priority
- central processing
- Prior art date
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Classifications
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system
- G06F13/368—Handling requests for interconnection or transfer for access to common bus or bus system with decentralised access control
- G06F13/376—Handling requests for interconnection or transfer for access to common bus or bus system with decentralised access control using a contention resolving method, e.g. collision detection, collision avoidance
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
- G06F13/24—Handling requests for interconnection or transfer for access to input/output bus using interrupt
- G06F13/26—Handling requests for interconnection or transfer for access to input/output bus using interrupt with priority control
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
- G06F13/4221—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F2213/0018—Industry standard architecture [ISA]
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- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Bus Control (AREA)
Abstract
본 발명은 충돌방지회로에 관한 것으로, 중앙처리장치와 컴퓨터에서 데이타를 레지스터에 셋팅할시 충돌현상이 있는가를 판단하는 단계와, 상기 충돌현상이 없다면 종료하는 단계와, 상기 충돌현상이 발생하면 데이타를 사용할수 있는 우선순위를 결정하는 단계와, 상기 우선순위가 중앙처리장치인가 컴퓨터인가를 판단하는 단계와, 상기 우선순위가 중앙처리라면 중앙처리장치를 레지스터에 셋팅하고 레지스터에 셋팅한만큼 컴퓨터에 지연신호를 입력하고 컴퓨터는 지연입력만큼 동작을 정지한후 지연입력이 없어지면 컴퓨터가 동작하는 단계와, 상기 우선순위가 컴퓨터라면 레지스터를 셋팅하고 레지스터 셋팅만큼 중앙처리장치 지연신호를 입력하고 중앙처리장치는 지연입력만큼 전체 신호동작을 정지하고 지연입력이 없어지면 중앙처리장치는 동작하는 단계를 포함하여 네트워크 인터페이스 카드에서 중앙처리장치와 컴퓨터의 아이사(ISA)버스간의 데이타를 송수신할때 프로토콜상에 발생하는 문제를 해결할 수 있다.The present invention relates to a collision avoidance circuit, comprising: determining whether a collision occurs when data is set in a register in a central processing unit and a computer; terminating if there is no collision; and if the collision occurs, Determining a priority that can be used, determining whether the priority is a central processing unit or a computer, and if the priority is central processing, setting the CPU in a register and delaying the computer as much as the register is set in the register. And the computer stops the operation by the delay input, and when the delay input disappears, the computer operates. If the priority is a computer, set the register and input the CPU delay signal as much as the register setting. Stop the entire signal operation as much as input and if there is no delay input, CPU Including the step of motion can solve the problem occurring in a protocol to send and receive data between the CPU and Isa (ISA) bus of a computer on a network interface card.
Description
제1도는 본 발명에 의한 구성도.1 is a block diagram according to the present invention.
제2도는 본 발명에 의한 플로우차트도.2 is a flowchart diagram according to the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
1 : 아이사(ISA) 버스 2 : 레지스터1: ISA bus 2: Register
3 : 충돌회로 4 : 우선순위 지정3: Collision Circuit 4: Priority Assignment
5 : 딜레이 6 : 중앙처리장치5: delay 6: central processing unit
본 발명은 충돌방지회로에 관한 것으로, 특히, 네트워크 인터페이스 카드에서 중앙처리장치와 컴퓨터의 아이사(ISA)버스간의 데이타를 송수신할때 발생하는 레지스터 셋팅의 문제를 해결하기 위한 충돌방지회로에 관한 것이다.The present invention relates to an anti-collision circuit, and more particularly, to an anti-collision circuit for solving a problem of register setting that occurs when a network interface card transmits and receives data between a CPU and an ISA bus of a computer. .
본 발명은 네트워크 인터페이스 카드에서 중앙처리장치와 컴퓨터의 ISA버스간의 데이타를 송수신할때 발생하는 레지스터 셋팅문제를 해결하는 것을 목적으로 한다.An object of the present invention is to solve a problem of register setting that occurs when a network interface card transmits and receives data between a central processing unit and an ISA bus of a computer.
본 발명은 상기 목적을 달성하기 위해 중앙처리장치와 컴퓨터에서 데이타를 레지스터에 셋팅할시 충돌현상이 있는가를 판단하는 단계와, 상기 충돌현상이 없다면 종료하는 단계와, 상기 충돌현상이 발생하면 데이타를 사용할수 있는 우선순위를 결정하는 단계와, 상기 우선순위가 중앙처리장치인가 컴퓨터인가를 판단하는 단계와, 상기 우선순위가 중앙처리라면 중앙처리장치를 레지스터에 셋팅하고 레지스터에 셋팅한만큼 컴퓨터에 지연신호를 입력하고 컴퓨터는 지연입력만큼 동작을 정지한후 지연입력이 없어지면 컴퓨터가 동작하는 단계와, 상기 우선순위가 컴퓨터라면 레지스터를 셋팅하고 레지스터 셋팅만큼 중앙처리장치 지연신호를 입력하고 중앙처리장치는 지연입력만큼 전체 신호동작을 정지하고 지연입력이 없어지면 중앙처리장치는 동작하는 단계를 포함하는 것을 특징으로 한다.In order to achieve the above object, the present invention provides a method for determining whether there is a collision when setting data in a register in a CPU and a computer, terminating if there is no collision, and using the data when the collision occurs. Determining the priority of the processor; determining whether the priority is a central processing unit or a computer; and if the priority is central processing, setting the CPU in a register and sending a delay signal to the computer as much as the register is set in the register. The computer stops the operation by the delay input, and if the delay input disappears, the computer operates. If the priority is a computer, the register is set and the CPU delay signal is input as much as the register setting. Stops the entire signal operation, and if there is no delay input, the CPU Characterized in that it comprises less.
이하, 첨부된 도면을 참조하여 본 발명을 상세하게 설명하기로 한다.Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.
제1도는 본 발명에 의한 블럭도로서, 아이사버스(ISA BUS, 1), 데이타를 저장하기 위한 레지스터(2), 충돌이 발생하는 충돌회로(3), 중요도에 의해 사용을 할수있는 우선순위지정(4), 일정시간동안 지연시키는 딜레이(5), 전체적인 제어를 하는 중앙처리장치(6)로 구성되어 있는것을 나타낸 것이다.1 is a block diagram according to the present invention, in which priority can be used according to ISA BUS 1, a register 2 for storing data, a collision circuit 3 in which a collision occurs, and importance. (4) It is shown that it consists of the delay 5 which delays for a predetermined time, and the central processing unit 6 which controls overall.
제2도는 본 발명에 의한 플로우차트도로서, 중앙처리장치와 컴퓨터에 데이타를 전송할때, 레지스터를 동시에 셋팅하는지를 검색하여 중앙처리장치와 컴퓨터에서 충돌현상이 있는가를 판단(101)하여 중앙처리장치와 컴퓨터중에서 데이타를 사용할수 있는 우선순위가 결정되고(102) 중앙처리장치인지 컴퓨터인지 판단하여(103) 중앙처리장치에 사용결정이 되면, 중앙처리장치의 레지스터에 셋팅하고(104) 충돌이 일어나는 시간만큼 컴퓨터쪽에서는 아이사(ISA)버스에 있는 모든 신호가 중지되도록 지연신호가 입력이 되고(105) 신호를 받은 컴퓨터는 모든 신호가 충돌시간만큼 동작이 정지하고 있으며(106) 충돌시간이 없어지면 컴퓨터는 다시 재신호를 가지고 동작을 하게된다.(107) 또한 컴퓨터에 사용결정이 되면 레지스터를 컴퓨터가 셋팅(108)하고 충돌한 시간만큼 중앙처리장치의 모든 신호가 중지하도록 지연신호가 입력된다.(109) 상기 중앙처리장치는 신호를 입력받아서 자기가 가지고 있는 모든 신호가 충돌된 시간만큼 신호동작이 정지해 있으며(110) 충돌된 시간이 지나고 없어지면 중앙처리장치는 멈추고 있던 모든 신호가 재동작하게 된다.(111)2 is a flowchart according to the present invention. When data is transmitted to the CPU and the computer, it is determined whether the registers are set at the same time to determine whether there is a collision between the CPU and the computer. If the priority to use the data is determined (102), it is determined whether it is a central processing unit or a computer (103), and if it is determined to be used by the central processing unit, it is set in the register of the central processing unit (104) and the time that a collision occurs On the computer side, a delay signal is inputted so that all signals on the ISA bus are stopped (105), and the computer that receives the signal stops operating as much as the collision time (106). When the computer decides to use it, the register is set 108 and the computer crashes. The delay signal is input to stop all the signals of the central processing unit as much as (109). The central processing unit receives the signal and stops the signal operation as much as the time when all the signals it owns collide (110). When the time has elapsed, the CPU will restart all the signals that were stopped.
본 발명은 네트워크 인터페이스 카드에서 중앙처리장치와 컴퓨터의 아이사(ISA)버스간의 데이타를 송수신할때 프로토콜상에 발생하는 문제를 해결할수 있다.The present invention solves a problem occurring in a protocol when a network interface card transmits and receives data between a CPU and an ISA bus of a computer.
Claims (1)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019960074763A KR100223983B1 (en) | 1996-12-28 | 1996-12-28 | Collision protecting circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019960074763A KR100223983B1 (en) | 1996-12-28 | 1996-12-28 | Collision protecting circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR19980055537A KR19980055537A (en) | 1998-09-25 |
| KR100223983B1 true KR100223983B1 (en) | 1999-10-15 |
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ID=19491656
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019960074763A KR100223983B1 (en) | 1996-12-28 | 1996-12-28 | Collision protecting circuit |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR100223983B1 (en) |
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1996
- 1996-12-28 KR KR1019960074763A patent/KR100223983B1/en not_active IP Right Cessation
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| Publication number | Publication date |
|---|---|
| KR19980055537A (en) | 1998-09-25 |
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