JPH0480829A - Arbitration/communication circuit for interruption signal - Google Patents

Abstract

PURPOSE:To prevent such a case where the received data are destroyed by the interruption of a lower rank communication processing operation by preventing the processing from being interrupted by the input of a higher rank interruption signal after an interruption processing operation is once carried out even with the low priority. CONSTITUTION:An interruption signal RxRDY of a serial communication control circuit 1-4 and a holding signal HOLD of an exclusive LAN control circuit 1-6 are inputted to a gate circuit 1-2A of an interruption preference circuit 1-2. Then the circuit 1-2A inputs the signal RxRDY directly to a terminal INT1 of a task arithmetic processing circuit 1-1. A signal line is cut by a relay so that the higher rank signals HOLD are not inputted to a terminal INTO of the circuit 1-1 with the interruption priority as long as the signal RxRDY is produced (level-on state). Meanwhile the circuit 1-2A is opened when no signal RxRDY is produced (level-on state). Thus the signal HOLD can be inputted to the circuit 1-1.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application 1] The present invention relates to a communication circuit that communicates with a plurality of communication partners, and an interrupt signal arbitration circuit that can be used in the communication circuit.

rPrior Art] FIG. 5 shows an example of the configuration of a communication circuit commonly used in bar code reading devices.

In FIG. 5, when the serial communication control circuit 1-4 receives a communication request from the personal computer 1O that processes information on barcode reading results, the serial communication control circuit 1-4 sends the task arithmetic processing circuit 4-4 to the serial communication control circuit 1-4. 1
Interrupt signals R, RD for the interrupt input terminal lNTl of
Transfer Y as a reception detection signal. Note that the transmission data from the personal computer IO is converted from a serial format to a parallel format signal in the serial communication control circuit 1-4.

When the task arithmetic processing circuit 4-1 receives the interrupt signals R and RDY, it interrupts the task (arithmetic processing) currently being performed and executes the serial communication task in an interrupt manner.

Specifically, a write signal is generated for the serial communication memory circuit 1-3, and communication data converted into a parallel signal by the serial communication control circuit 1-4 is stored in the serial communication memory circuit 1-3.

Thereafter, the task arithmetic processing circuit 4-1 analyzes the communication data stored in the serial communication memory circuit 1-3, creates response transmission data, and sends it to the personal computer 10 via the serial communication control circuit 1-4. Sends a response.

On the other hand, the barcode reader is connected to the sequencer 20, etc.
N (local area network), the data sent from the sequencer 20 is received by the dedicated LAN control circuit 1-6. Dedicated LAN control circuit 1
-6, when transmit data is received, hold signal HOLD
is transferred to the interrupt input terminal INTO of the task arithmetic processing circuit 4-1 as a reception detection signal. Further, while the dedicated LAN control circuit 1-6 is receiving communication data from the sequencer 20, it outputs the hold signal HOLD to the bus arbitration circuit 1-5, and connects the dedicated LAN storage circuit 1-7 and the dedicated LA.
A bus connection is made between the N control circuit 1-6 and the bus arbitration circuit 1-5. As a result, the communication data of the sequencer 20 is transferred to the dedicated L by the write signal from the sequencer 20.
After being converted into a parallel signal via the AN control circuit 1-6, it is written into the dedicated LAN storage circuit 1-7.

In response to the release of the hold signal, the task arithmetic processing circuit 4-1 reads communication data from the dedicated LAN storage circuit 1-7 and creates response transmission data.

Conventionally, in this type of communication circuit, the task arithmetic processing circuit 4-1 sets a priority order for interrupt signals in advance in order to prevent simultaneous communication with multiple communication partner devices, and interrupt signals are When input, the interrupt signal with higher priority is accepted.

[Problems to be Solved by the Invention] However, after accepting the low priority interrupt signals R and RDY, the high priority hold signal HOLD is sent to the task arithmetic processing circuit 4-1 as shown in FIG. When an interrupt is input at timing TIO, the task arithmetic processing circuit 4-1 temporarily suspends the current arithmetic processing, that is, the serial communication task, and executes the dedicated LAN task in an interrupt manner.

When the task arithmetic processing circuit 4-1 finishes the arithmetic processing of the dedicated LAN task and restarts the serial communication task, the data communication of the personal computer 10 ends. As a result, the data received from the personal computer IO is not partially stored, resulting in data omission.

In order to eliminate such problems, a direct memory access (DMA) control circuit 1-8 is provided as shown in FIG.
A communication circuit has also been proposed in which the data received by the personal computer 10 is written to the serial communication storage circuit 1-3, but the task arithmetic processing circuit 4-1 is not allowed to perform data reception processing (writing processing). There is.

However, conventionally, this type of communication circuit requires a task arithmetic processing circuit for a plurality of communication processes or a communication processing circuit having an equivalent function, which increases the manufacturing cost of the communication circuit.

SUMMARY OF THE INVENTION In view of the above-mentioned points, it is an object of the present invention to provide a system that, even if a task arithmetic processing circuit that performs communication processing is started by inputting an interrupt signal, the communication processing that is currently being executed and has a low interrupt priority is delayed. It is an object of the present invention to provide a communication circuit that is not interrupted by an input interrupt signal having a high priority, and to provide an arbitration circuit for interrupt signals that can be used in the communication circuit.

[Means for Solving the Problems 1] In order to achieve such an object, the present invention executes task processing corresponding to the interrupt signal in a predetermined priority order when a plurality of interrupt signals are input. an arbitration circuit that arbitrates and inputs the plurality of interrupt signals to the arithmetic processing circuit, and when none of the plurality of interrupt signals is generated, inputs the generated interrupt signal to the arithmetic processing circuit; after any one of the plurality of interrupt signals is generated;
Until the interrupt signal of the concerned occurrence disappears, input of the interrupt signal of the occurrence lower than the interrupt signal of the concerned occurrence in the priority order is allowed to be input to the arithmetic processing circuit, and the interrupt signal of the occurrence of the higher priority is allowed to be input to the processing circuit. The present invention is characterized by comprising a second signal switching means for inhibiting input.

Further, the present invention includes a plurality of receiving circuits each receiving communication data from a plurality of external devices and generating a reception detection signal, and manually inputting each of the reception detection signals and inputting them according to a predetermined priority order. arithmetic processing means for interruptively executing communication-related arithmetic processing corresponding to the reception detection signal of the current input reception detection signal; The present invention is characterized by comprising an arbitration means for prohibiting input of a signal to the arithmetic processing means.

[Function 1] The present invention focuses on the fact that an arithmetic processing circuit, for example, a CPU, has an arbitration function that selects a higher priority interrupt signal from parallel input interrupt signals in interrupt processing,
When an interrupt signal is currently being input to the arithmetic processing circuit, the second signal switching means prohibits the input of an interrupt signal higher than the interrupt signal, thereby preventing interruption of the task processing of the arithmetic processing circuit currently being executed. .

By using an arbitration circuit with such a function in a communication circuit, when multiple communication processes occur at the same time, the communication process with a high priority can be selectively executed, and even communication processes with a low priority can be executed. The communication process is not interrupted while it is being performed.

[Embodiment 1] Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 shows the circuit configuration of an embodiment of the present invention.

Note that the same parts as in the conventional example shown in FIG. 5 are given the same reference numerals, and detailed explanations will be omitted.

In FIG. 1, gate circuit 1 of interrupt priority circuit 1-2
-2A, the interrupt signals R and RDY of the serial communication control circuit 1-4 and the hold signal 10LD of the dedicated LAN control circuit 1-6 are input.

The gate circuit 1-2A directly inputs the interrupt signals R and RDY to the lNTl terminal of the task arithmetic processing circuit 1-1. When the interrupt signals R and RDY are generated (level on), the above-mentioned hold signal HOLD is higher in the interrupt priority order.
The signal line is disconnected by a relay so that the signal is not input to the INTO terminal of the task arithmetic processing circuit 1-1.

Note that when the interrupt signals R and RDY are not generated (level on), the gate path 1-2A is open, and input of the hold signal HOLD to the task arithmetic processing circuit is permitted. The interrupt priority circuit 1-2 operates as the arbitration means of the present invention, and the gate circuit 1-2A operates as the first and second signal switching means.

The communication operation of such a circuit will be explained with reference to the timing chart of FIG. 2 and the flowchart of FIG. 3.

1) When no communication is performed, the gate of the interrupt priority circuit 1-2 is open, and input of both the interrupt signal RxRDY and the hold signal 1 (OLD) to the task calculation circuit 1-1 is permitted.

At this point, the task arithmetic processing circuit 1-1 executes the main task, in this example, arithmetic processing such as controlling the barcode reading device (timing T21 in FIG. 2, step 5100 in FIG. 3).

2) Serial communication with the personal computer 10 When a communication request signal is received from the personal computer 10, interrupt signals R and RDY are generated in the serial communication control circuit 1-4, and the task arithmetic processing circuit 1-i
is input. Furthermore, in the interrupt priority circuit 1-2,
Input of the hold signal of the dedicated LAN control circuit 1-6 to the task arithmetic processing circuit 1-1 is prohibited (timing T22 in FIG. 2).

In the task arithmetic processing circuit 1-1, level-on R and RDY
By inputting a signal to the lNTl terminal, the currently executing main task is interrupted and a serial communication task is executed. As a specific control process, communication data received via the serial communication control circuit 1-4 is input, a write signal is generated, and the communication data is written into the serial communication memory circuit 1-3 (see Fig. 2). Timing below 23.3rd
Step 5200 in the figure).

3) When data is transmitted from the sequencer 20 while serial communication is being executed, the dedicated LAN control circuit 1-6 generates a level-on hold signal (10LD) according to the data transmitted from the sequencer 20, and the bus arbitration circuit 1-5 and make the bus connection (
Step T24 in FIG. 2). Next, communication data is written to the dedicated LAN storage circuit 1-7 in response to a write instruction from the sequencer 20 (step T25 in FIG. 2). However, since the ON hold signal HOLD is not input to the task arithmetic processing circuit 1-1, the serial communication processing currently being executed continues.

When the data transmission from the personal computer 10 ceases, the interrupt signals R and RDY also disappear (level off), so the interrupt priority circuit 1-2 is a task arithmetic processing circuit for the currently generated hold signal HOLD (level on). Allow input to H (timing T25 in Figure 2)
.

The task arithmetic processing circuit 1-1 returns the execution process to the main task when the interrupt signals R and RDY disappear, but since there is an interrupt input of the hold signal at almost the same time, the dedicated LAN task is subsequently executed as an interrupt. (Steps 5300-5400→5500 in FIG. 3). When the dedicated LAN task is completed, the task arithmetic processing circuit 1-1 returns to the main task.

4) Dedicated LAN communication task with sequencer 20 Interrupt priority circuit 1 while the arithmetic processing circuit 1-1 is executing the main task
-2 causes an interrupt signal RRDY.

Since the interrupt input of the hold signal HOLD is permitted, the task arithmetic processing circuit 1-1 executes a dedicated LAN task in response to the generation of the hold signal HOLD.

5) If serial communication occurs while dedicated LAN communication is being executed, interrupt priority circuit 1-2 will interrupt serial communication control circuit 1-
The interrupt signals R and RDY generated in step 4 are directly transferred to the task arithmetic processing circuit 1-1. At this time, the interrupt signal R,
RDY and hold signal HOLD are in a parallel input state.

However, since the interrupt priority of the interrupt signal RxRDY is lower than that of the currently input hold signal HOLD, the interrupt processing of the serial communication task cannot be accepted.

As a result, even if the personal computer IO sends out a communication request signal as communication data, the communication circuit does not send out a reception response signal, and the personal computer 10 performs a standby process until it becomes communicable.

As explained above, in this embodiment, the task arithmetic processing circuit 1-1 also uses an arbitration function that executes interrupt tasks in the priority order of the interrupt input signals, so the circuit configuration of the interrupt priority circuit 1-2 is simplified. can be converted into

In addition to this embodiment, the following examples are given.

1) Although this embodiment shows an example in which two communication tasks are executed by one task calculation processing circuit, the number of communication tasks is not limited to two, and the number of communication tasks is not limited to two. It may be determined in accordance with the type of communication method and the number of devices.

In this case, an interrupt priority circuit is configured depending on the number of interrupt signals. For reference, the circuit configuration of a three-person interrupt signal arbitration circuit is shown in FIG.

2) Although this embodiment shows an example in which the interrupt arbitration circuit is used in a communication circuit, the present invention can also be applied to an information processing device such as a communication circuit in which it is not desirable to interrupt the task processing currently being executed by a higher-level interrupt signal. arbitration circuit can be used.

3) This embodiment shows an example in which the interrupt signal priority circuit is configured with a relay switch, but depending on the signal format, a logic circuit such as an AND circuit or a signal holding circuit such as a flip-flop may be used to configure the priority circuit. may be configured.

[Effects of the Invention] As explained above, according to the present invention, when a plurality of interrupt signals are simultaneously input to the arithmetic processing circuit, the interrupt processing circuits execute the interrupt processing according to the priority order, Even if the priority level is low, once an interrupt process is executed, the process will not be interrupted by the input of a higher level interrupt signal.

As a result, in a plurality of types of communication processing, received data is no longer destroyed due to interruption of lower-level communication processing, as is the case in the past.

[Brief explanation of the drawing]

Fig. 1 is a block diagram showing the circuit configuration of the embodiment of the present invention, Fig. 2 is a timing chart showing the operation timing in the embodiment of the invention, Fig. 3 is a flowchart showing the operation procedure in the embodiment of the invention, and Fig. 4. is a circuit diagram showing the configuration of another arbitration circuit in the embodiment of the present invention, FIG. 5 is a block diagram showing the circuit configuration of the conventional example, FIG. 6 is a timing chart showing the operation timing of the conventional example, and FIG. 7 is another example. FIG. 2 is a block diagram showing a circuit configuration of a conventional example. 1-1...Task arithmetic processing circuit, 1-2...Interrupt priority circuit, 1-3...Serial communication memory circuit, 1-4...Serial communication control circuit, 1-5... - Bus arbitration circuit, 1-6... Dedicated LAN control circuit, 1-7... Dedicated LAN storage circuit, IO... Personal computer, 20... Sequencer. Tree 4f: Operator 14I shown in 1↑ in the example of torture 170-1000N Figure 3

Claims (1)

[Claims] 1) When a plurality of interrupt signals are input, arbitration input of the plurality of interrupt signals is provided to an arithmetic processing circuit that executes task processing corresponding to the interrupt signal in a predetermined priority order. a first signal switching means, which is an arbitration circuit configured to perform an arbitration circuit, and is capable of inputting a generated interrupt signal to the arithmetic processing circuit when none of the plurality of interrupt signals are generated;
After any one of the plurality of interrupt signals is generated, until the generated interrupt signal disappears,
a second signal switching means for permitting input of an interrupt signal of a lower level than the generated interrupt signal to the arithmetic processing circuit in the priority order, and prohibiting input of an interrupt signal of a higher level of occurrence; An arbitration circuit for interrupt signals, characterized in that: 2) A plurality of receiving circuits each receiving communication data from a plurality of external devices and generating a reception detection signal, and receiving each reception detection signal and generating the reception detection signal of the input according to a predetermined priority order. arithmetic processing means for interruptively executing communication-related arithmetic processing corresponding to the above, and the calculation processing means for the reception detection signal that is higher in priority than the reception detection signal of the input until the reception detection signal of the current input disappears; A communication circuit comprising: arbitration means for prohibiting input to the processing means.