JPH07261814A - Interruption synchronizing method for dual system of pc - Google Patents

Abstract

PURPOSE:To switch a control system and a stand-by system in the dual system of asynchronous PCs by enabling actuation only with a matching interruption signal while the states of the two systems match each other right after a synchronous instruction is executed by a processor. CONSTITUTION:An interruption processing part A and an interruption processing part B are of the same circuit constitution and both processors A and B constitute the dual system. In this case, an interruption signal A is held by a register 7 and inputted to a coincidence detecting circuit 8 with a SYNC-A signal outputted from a synchronous port A with a synchronous instruction of the processor A. The coincidence detecting circuit 8 decides whether or not the interruption signals of the systems A and B match each other when an RDY-A signal is active, and outputs an interruption request to the processors only with the matching interruption signal A when the RDY-A signal rises. Thus, interruption processing is performed only when the synchronization of the two processors A and B is completed, so the internal states of the two processors A and B can be matched with each other.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an interrupt synchronization method in a dual system of a programmable controller (hereinafter abbreviated as PC).

[0002]

2. Description of the Related Art When a processing device has a dual structure and a processing device performing control processing (hereinafter referred to as a control system) goes down, a processing device not performing control processing (hereinafter referred to as a standby system) The dual system, in which the control process is switched to, is an effective measure for PC failure,
In a system that requires real-time processing, this control processing must be switched immediately, so the standby system must always maintain the same internal state as the control system. In the prior art, the two synchronized processing devices use the same program and the same data, so that the internal states of the two processing devices are always the same.
The control system and the standby system are switched as needed.
In this case, in order to match the contents of the duplicated memory and I / O, writing to the memory and I / O is performed only for the control system and the standby system only by the processing unit of the control system. Reading into the memory or I / O is performed by the processing device corresponding to the memory or I / O of each of the control system and the standby system.

[0003]

In such a system, since it is necessary to synchronize high-frequency clocks in order to synchronize the two processing devices, the synchronization circuit becomes complicated, and the two processing devices need to be synchronized. Although it is difficult to divide the module into two modules, the reliability is reduced. However, by making the clocks of the two processing devices asynchronous, it is possible to avoid the use of complicated switching circuits and synchronization circuits. However, since the clocks are asynchronous, there is a problem in that the program steps for accepting an interrupt are misaligned because the program steps executed by the processing devices of the control system and the standby system are misaligned. Even if there is no deviation, if the interrupt signal itself is asynchronous with respect to both control systems due to the difference in the transmission path of the interrupt signal and other reasons, as in the former case,
There is a problem that the program steps that accept interrupts are misaligned. Therefore, in a dual system in which two processing units are asynchronous, there is a risk that the timing of the interrupt will shift if the execution steps of both processing units are synchronized by a synchronization instruction and the interrupt signal is received. The internal states of the two processing devices may be different. The present invention solves such a problem in an asynchronous PC dual system and provides a means for synchronizing interrupts even when the interrupt signal itself is asynchronous.

[0004]

In order to solve the above problems, the present invention provides an asynchronous PC dual system interrupt synchronization method for switching a plurality of programs by interrupt signals and executing them, and both PCs are defined by the programs. As a result of executing the synchronization instruction, when the internal states of both PCs match, the interrupts to both PCs are accepted only when the external interrupt signals to both PCs match.

[0005]

By the above means, the interrupt processing is performed only when the synchronization of the two processing devices is completed, so that the internal states of the two processing devices can be matched.

[0006]

Embodiments of the present invention will be described below with reference to the drawings. In FIG. 1, 1 is an interrupt processing unit A, 2 is an interrupt processing unit B, 3 is a processing device A, 4 is a processing device B, 5 is a synchronous port A, 6 is an OR circuit, 7 is a register circuit, and 8 is It is a match detection circuit. The interrupt processing unit A and the interrupt processing unit B have the same circuit configuration and constitute a dual system together with the processing device. Since the CPU clocks of the processing device A and the processing device B are operating asynchronously, the execution program steps are gradually displaced due to variations in clock frequency and the like. The synchronization port in the figure is for correcting the deviation, and its operation will be described below. The processing device A sends a synchronization instruction (synchronization port A
When the instruction for accessing (1) is executed, the SYNC_A signal becomes active. At this time, if SYNC_B is inactive, RDY_A does not become active, and the processing device A keeps the wait state by the synchronization instruction. SYNC_B
Becomes active, RDY_A becomes active, the wait state is released, and the process is restarted. On the other hand,
When the processor B also executes the synchronous instruction (the instruction to access the synchronous port A), the SYNC_B signal becomes active. At this time, if SYNC_A is inactive,
RDY_B does not become active, and the processor B keeps the wait state by the IN instruction. When SYNC_A becomes active, RDY_B becomes active, the wait state is released, and the process is restarted. RDY_A and RDY_B
(RDY signal of system B) is both SYNC_A and S
YNC_B is a logical product (AND signal), and the processing device A
The deviation of the timing when the wait of the processor B is released can be suppressed only by the phase shift of each system clock. Therefore, there is no deviation in the start of the instruction after the execution of the synchronous instruction, and the internal states of the two processors immediately after the synchronous instruction are completely the same. Next, a method of external interrupt processing will be described. The interrupt signal is held in the register by the SYNC_A signal output from the synchronous port according to the synchronous instruction of the processing device A, and is input to the coincidence detection circuit. When the RDY_A signal is active, the match detection circuit determines whether the interrupt signals of the systems A and B match or does not match, and
An interrupt request is output to the processing device only with the interrupt signal that coincides with the rising edge of the DY_A signal. The unmatched interrupt signal is stored in a register in the temporary match detection circuit so that the external interrupt signal is not unprocessed and discarded, and is logically ORed with the external interrupt signal at the next synchronization instruction. , Are again input to the match detection circuit.

[0007]

As described above, according to the present invention, the interrupt processing is activated only by the coincident interrupt signal in a state where the states of the two systems immediately after the execution of the synchronous instruction of the processing device coincide. Therefore, even if an interrupt occurs, the states of the two systems always match immediately after the synchronization instruction, so that the control system and the standby system can be switched. Further, the processing apparatus A is separated from the processing apparatus B and becomes an independent operation by forcibly activating SYNC_B and the interrupt signal_B, and similarly, the processing apparatus B is
By forcibly activating YNC_A and interrupt signal _A, it is separated from the processing unit B and operates independently, so dual and single (each operates independently)
Can also be easily switched.

[Brief description of drawings]

FIG. 1 is a configuration example of a dual system according to the present invention.

[Explanation of symbols]

 1 Interruption processing unit A 2 Interruption processing unit B 3 Processing device A 4 Processing device B 5 Synchronization port A 6 OR circuit 7 Register circuit 8 Match detection circuit

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI Technical display location G06F 15/16 470 J G05B 19/05 F

Claims (1)

[Claims] 1. In an asynchronous PC dual-system interrupt synchronization method for switching a plurality of programs by interrupt signals and executing them, the internal states of both PCs match as a result of execution of a synchronization instruction defined by the programs. Both PCs when in
An interrupt synchronization method in a dual system of PCs, characterized in that an interrupt to both PCs is accepted only when the external interrupt signals to PC match.