JPH0617320Y2 - Memory device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial field of application] The present invention relates to a memory device in which a memory cell is configured by using a switching transistor and a so-called stacked capacitive element.

[Outline of device]

According to the present invention, in the memory device as described above, one electrode of each capacitive element of two memory cells adjacent to each other is formed of first and second conductive layers which are different layers from each other, and By overlapping at least the end portions of the first and second conductive layers with each other, the integration degree can be increased while maintaining the reliability of the memory operation and the manufacturing yield.

[Prior Art] In order to increase the degree of integration of a memory device in which a memory cell includes a switching transistor and a stacked capacitive element, the capacitive element is connected to a source / drain region of the transistor. It is necessary to provide the capacitor with a sufficient capacity even if the area of the memory cell is small by forming the electrodes that are formed over substantially the entire area of the memory cell.

However, although it is necessary to bring the electrodes of the adjacent memory cells to be constructed in this way close to each other, it is not possible to bring them closer to each other within a certain distance due to the limitation of the linography technique.

Therefore, the present applicant has proposed a memory device which solves this problem by forming the electrodes in the adjacent memory cells not by the same conductive layer but by the first and second conductive layers which are different layers from each other. Japanese Patent Application No. 62-212574
I have already proposed it as an issue.

FIGS. 3 and 4 show a DRAM constructed in this way, and FIG. 5 shows its manufacturing process.

That is, in order to manufacture such a DRAM, an oxide film 12 for element isolation is first formed on the surface of a semiconductor substrate 11 such as a Si substrate as shown in FIG. 5A.

Then, on the oxide film 14 and the oxide film 12 in the element formation region 13 surrounded by the oxide film 12, the first-layer polycrystalline Si is formed.
Gate electrodes 15a, 15b, 16a, 16 composed of layers and the like
b is formed.

After that, the source / drain regions 17a to 17c are formed by self-alignment with the gate electrodes 15a to 16b, and further,
The entire surface of the semiconductor substrate 11 is covered with the interlayer insulating film 18. Then, openings 21 a and 22 reaching the source / drain regions 17 a and the oxide film 12 are formed in the interlayer insulating film 18.

Next, as shown in FIG. 5B, the gate electrodes 15a, 1a connected to the source / drain regions 17a through the openings 21a.
The electrode 23a extending up to 6b is formed on the second-layer polycrystalline Si.
It is formed of layers and the like. Then, the oxide film 2 is formed on the surface of the electrode 23a.
4 is formed, and an opening 21b reaching the source / drain region 17b is further formed in the interlayer insulating film 18.

Next, as shown in FIG. 5C, the gate electrodes 15b, 1b connected to the source / drain regions 17b through the openings 21b.
The electrode 23b extending up to 6a is formed on the third layer of polycrystalline Si.
It is formed of layers and the like. Since the electrode 23a is covered with the oxide film 24, the electrode 23a is not removed when the electrode 23b is patterned.

After that, the oxide film 24 is once removed, and then, as shown in FIG. 3, dielectric layers 25a and 25b which are oxide films are formed on the surfaces of the electrodes 23a and 23b. Then, the other electrode 26 made of the fourth-layer polycrystalline Si layer or the like, the interlayer insulating film 27, and the opening 28 reaching the source / drain region 17c.
And a bit line 31 made of A1 are formed.

Therefore, in this DRAM, one element formation region 13 has one
A pair of memory cells 32a and 32b are formed, and these memory cells 32a and 32b are configured by using switching transistors 33a and 33b and capacitors 34a and 34b.

In addition, the transistors 33a and 33b have a gate electrode 15
a and 15b and source / drain regions 17a to 17c, the capacitive elements 34a and 34b are the electrodes 23.
a, 23b and 26 and dielectric layers 25a and 25b.

Note that the gate electrodes 16a and 16b are used for the transistors of the memory cells adjacent to each other in the direction perpendicular to the paper surface of FIG. 3, as is apparent from FIG.

In such a DRAM, the electrode 23a of the memory cell 32a is
Is formed of the second-layer polycrystalline Si layer or the like, and the electrode 23b of the memory cell 32b is formed of the third-layer polycrystalline Si layer or the like. The regions of the memory cells 32b and 32a to be used can also be included in the region to be removed by patterning.

Therefore, as shown in FIG. 3, the electrodes 23a and 23b can be brought close to each other beyond the limit of lithography, and these electrodes 23a and 23b can be formed over substantially the entire area of the memory cells 32a and 32b. .

[Problems to be solved by the invention]

In the DRAM as described above, the electrodes 23a and 23b need to be patterned in the opening 22 of the interlayer insulating film 18, but anisotropic etching in the deep opening 22 requires long-time over-etching. .

Moreover, in order to remove the native oxide film before the growth of the third-layer polycrystalline Si layer and also remove the oxide film 24 before the growth of the fourth-layer polycrystalline Si layer, on the semiconductor substrate 11. Hydrofluoric acid treatment is applied to the entire surface of each.

Therefore, the recess 35 is formed in the oxide film 12 in the step of FIG. 5B, and the recess 35 becomes deeper in the step of FIG. 5C.
However, since the electrode 26 is also formed in the recess 35, the inversion layer is formed in the region below the oxide film 12. Therefore, a leak current flows and the stored information is lost. Therefore, in the above-mentioned DRAM, the reliability of the storage operation is not high.

When anisotropic etching is performed in the deep opening 22, the manufacturing stability is low and the manufacturing yield is low.

[Means for solving problems]

In the memory device according to the present invention, one electrode 23a of the capacitive element 34a in one of the two memory cells 32a and 32b adjacent to each other is formed of the first conductive layer, and the two memory cells 32a, One electrode 23b of the capacitive element 34b in the other 32b of the 32b is formed of a second conductive layer which is a layer different from the first conductive layer, and the first and second conductive layers include at least those electrodes. They overlap each other at the ends.

[Action]

In the memory device according to the present invention, each of the capacitive elements 34a of two memory cells 32a, 32b adjacent to each other,
Since one electrode 23a, 23b of 34b is formed of the first and second conductive layers which are different layers from each other, the adjacent memory cells 32b, 32a are patterned at the time of patterning the first and second conductive layers. This region can also be included in the region to be removed by patterning. Therefore, the capacitive element 3
The electrodes 23a and 23b on one side of 4a and 34b can be formed over substantially the entire area of the memory cells 32a and 32b.

Moreover, since the first and second conductive layers are overlapped with each other at least at their ends, the first and second conductive layers are different from the case where the first and second conductive layers are separated in a plane. The amount of etching of the element isolation film 12 due to the patterning of the conductive layer is small or none. Therefore, the generation of the inversion layer is small, and thus the leak current is small.

When the first and second conductive layers overlap at least at their ends, the deep recess 22 is etched as in the case where the first and second conductive layers are separated in a plane. There is no need, and manufacturing stability is high.

〔Example〕

An embodiment of the present invention applied to a DRAM will be described below with reference to FIGS. 1 and 2.

In this embodiment, as shown in FIGS. 1 and 2, the electrode 23a of the memory cell 32a extends so as to fill the opening 22 and approach the adjacent memory cell 32b, and the electrode 23b of the memory cell 32b also has an opening. 22 and the front face DRAM shown in FIGS. 3 to 5, except that the electrodes 23a and 23b overlap each other at their ends. It has a substantially similar configuration.

Even if configured in this way, it is not necessary to add a manufacturing process,
The area of the memory cells 32a and 32b does not increase.

In this embodiment, both electrodes 23a and 23b extend so as to approach the adjacent memory cells 32b and 32a.
Only one of the electrodes 23a and 23b is adjacent to the memory cell 32.
It may extend so as to approach b and 32a.

[Effect of device]

In the memory device according to the present invention, although one electrode of the capacitive element can be formed over almost the entire area of the memory cell, the leakage current is small, so that the integration degree is increased while maintaining the reliability of the memory operation. be able to.

Moreover, since it is not necessary to etch the deep recesses when patterning one electrode of the capacitive element, and the manufacturing stability is high, it is possible to increase the degree of integration while maintaining the manufacturing yield.

[Brief description of drawings]

1 and 2 show an embodiment of the present invention. FIG. 1 is a side sectional view taken along the line II of FIG. 2, and FIG. 2 is a plan view. FIGS. 3 to 5 show examples disclosed in the prior application of the present invention. FIG. 3 is a side sectional view taken along line III-III of FIG. 4, FIG. 4 is a plan view, and FIG. The drawings are side cross-sectional views sequentially showing the manufacturing process. In the reference numerals used in the drawings, 23a, 23b ... Electrodes 32a, 32b ... Memory cells 34a, 34b ... Capacitance elements.

Claims (1)

[Scope of utility model registration request] 1. A memory cell is configured using a switching transistor and a capacitive element, one electrode of the capacitive element being connected to one source / drain region of the transistor, and the capacitive element. In the memory device in which the other electrode is stacked on the one electrode via a dielectric layer, the one electrode of the capacitive element in one of two memory cells adjacent to each other has the first conductivity. A second conductive layer that is a layer different from the first conductive layer, and the one electrode of the capacitive element in the other of the two memory cells is formed of a second conductive layer that is different from the first conductive layer. And a second conductive layer overlapping each other at least at their ends.