JPH0727630Y2 - Memory device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial field of use] The present invention relates to a memory device in which a memory cell is configured by using a transistor for switching and a so-called laminated capacitive element.

[Outline of device]

According to the present invention, in the memory device as described above, one electrode of each capacitive element of two memory cells adjacent to each other is formed of first and second conductive layers which are different layers from each other. At least the end portions of the first and second conductive layers are overlapped with each other, and the overlapping areas of the first and second conductive layers with respect to the third conductive layer forming the other electrode of the capacitive element are substantially equal to each other. By making them equal, the degree of integration can be increased while maintaining the reliability of the memory operation and the manufacturing yield.

[Conventional technology]

In order to increase the degree of integration of a memory device in which a memory cell is configured using a switching transistor and a stacked capacitive element, the electrode connected to the source / drain region of the transistor in the capacitive element is used as a memory. It is necessary to provide the capacitor with a sufficient capacity even if the area of the memory cell is small by forming it over substantially the entire area of the cell.

However, in the case of such a configuration, it is necessary to bring the electrodes of the adjacent memory cells close to each other, but it is not possible to bring them closer to each other within a certain distance due to the limitation of the lithography technique.

Therefore, the present applicant solves this problem by forming the electrodes in the adjacent memory cells not by the same conductive layer but by the first and second conductive layers which are different layers from each other. A memory device in which reliability of a memory operation and manufacturing yield are maintained by overlapping at least end portions of the first and second conductive layers with each other,
It has already been proposed as Japanese Utility Model Application No. 62-178058.

2 and 3 show a DRAM constructed in this way. That is, in this DRAM, the element isolation film 12 is formed on the surface of the semiconductor substrate 11, and a pair of memory cells 14a and 14b are formed in one element formation region 13 surrounded by the element isolation film 12. There is.

Memory cells 14a and 14b are switching transistors.
It is configured by using 15a and 15b and capacitive elements 16a and 16b.

The transistors 15a and 15b are composed of gate electrodes 17a and 17b and source / drain regions 18a to 18c, and the capacitive elements 16a and 16b are composed of electrodes 21a, 21b and 22 and dielectric layers 23a and 23b. There is.

The gate electrodes 24a and 24b are used for the transistors of the memory cells adjacent to each other in the direction perpendicular to the paper surface of FIG. A bit line 25 made of Al is connected to the source / drain region 18c.

[Problems to be solved by the device]

By the way, in such a DRAM, as is clear from FIG. 3, the electrode 21b entirely faces the electrode 22,
The entire electrode 21b contributes to the accumulated charge capacity of the capacitive element 16b.

However, since the electrode 21a does not face the electrode 22 in the overlapping portion with the electrode 21b, only the portion of the electrode 21a not overlapping with the electrode 21b contributes to the accumulated charge capacity of the capacitive element 16a.

As is clear from FIG. 2, the area of the portion of the electrode 21a that does not overlap the electrode 21b is smaller than the area of the electrode 21b. Therefore, the capacitance elements 16a and 16b do not have equal accumulated charge capacities.

In the DRAM, a reference capacitance element having a reference accumulated charge is provided separately from the capacitance elements 16a and 16b in the memory cells 14a and 14b, and the signal voltage from the capacitance elements 16a and 16b extracted to the bit line 25 is supplied from the reference capacitance element. The read operation is performed by comparing with the signal voltage of.

That is, the capacitive element 16 in the adjacent memory cells 14a and 14b is
The signal voltages from a and 16b are not compared with each other. Therefore, even if the accumulated charge capacities of the capacitors 16a and 16b are not equal to each other, there is no problem in the operation principle of the DRAM.

However, if the signal voltages obtained from the capacitance elements 16a and 16b are not equal to each other because the capacitance values of the capacitance elements 16a and 16b are not equal to each other, the operating range is narrow and the noise margin is small.

Therefore, in the memory device shown in FIGS. 2 and 3, the reliability of the storage operation is not necessarily high.

[Means for Solving the Problems]

In the memory device according to the present invention, one electrode 21a of the capacitive element 16a in one of the two memory cells 14a, 14b adjacent to each other is formed of the first conductive layer, and the two memory cells 14a, 14a Capacitance element 1 on the other side 14b of 14b
One electrode 21b of 6b is formed of a second conductive layer which is a layer different from the first conductive layer, and the first and second electrodes
Conductive layers overlap each other at least at their ends, and the first and second conductive layers are interposed via the dielectric layers 23a and 23b.
The third conductive layer extending over the conductive layer of
The other electrode 22 of 6b is formed, and the overlapping areas of the first and second conductive layers with respect to the third conductive layer are substantially equal to each other.

[Action]

In the memory device according to the present invention, one electrode 21a, 21b of each of the capacitive elements 16a, 16b of two memory cells 14a, 14b adjacent to each other is a first layer and a second layer which are different layers.
Memory cells 14b, 1 which are adjacent to each other when patterning these first and second conductive layers.
The region 4a can also be included in the region to be removed by patterning. Therefore, one electrode 21a, 2 of the capacitive element 16a, 16b
1b can be formed over almost the entire area of the memory cells 14a and 14b.

Moreover, since the first and second conductive layers are overlapped with each other at least at their ends, the first and second conductive layers are different from the case where the first and second conductive layers are separated in a plane. The amount of etching of the element isolation film 12 due to the patterning of the conductive layer is small or not at all. Therefore, the generation of the inversion layer is small, and thus the leak current is small.

Further, when the first and second conductive layers overlap at least at their ends, the deep recess 26 is etched as in the case where the first and second conductive layers are separated in a plane. There is no need, and manufacturing stability is high.

Further, since the respective overlapping areas of the first and second conductive layers with respect to the third conductive layer forming the other electrode 22 are substantially equal to each other, the accumulated charge capacities of both the capacitance elements 34a and 34b are substantially equal to each other. equal. Therefore, substantially equal signal voltages can be obtained from any of the capacitive elements 34a and 34b, and the operating range is wide and the noise margin is large.

〔Example〕

An embodiment of the present invention applied to a DRAM will be described below with reference to FIG.

In this embodiment, as shown in FIG.
2 and 3 except that the size and shape of these electrodes 21a, 21b are selected so that the area of the portion not overlapping 1b is substantially equal to the area of the electrode 21b. It has substantially the same configuration as the DRAM of the prior application shown.

Even if configured in this way, it is not necessary to add a manufacturing process,
The area of the memory cells 14a and 14b does not increase.

[Effect of device]

In the memory device according to the present invention, one electrode of the capacitive element can be formed over substantially the entire area of the memory cell. Further, since the leakage current due to the inversion of the element isolation region is small, the integration degree can be increased while maintaining the reliability of the memory operation.

Further, since signal voltages that are substantially equal to each other are obtained from any of the capacitive elements, and the operating range is wide and the noise margin is large, the integration degree can be increased while maintaining the reliability of the memory operation.

Moreover, since it is not necessary to etch the deep recesses when patterning one electrode of the capacitive element, and the manufacturing stability is high, it is possible to increase the degree of integration while maintaining the manufacturing yield.

[Brief description of drawings]

FIG. 1 is a plan view showing an embodiment of the present invention. 2 and 3 show an example disclosed in the prior application of the present invention. FIG. 2 is a plan view and FIG. 3 is III-I in FIG.
It is a sectional side view in the II line. In the reference numerals used in the drawings, 14a, 14b ... Memory cells 16a, 16b ... Capacitance elements 21a, 21b, 22 ... Electrodes 23a, 23b ... Dielectric layers.

Claims (1)

[Scope of utility model registration request] 1. A memory cell is configured using a switching transistor and a capacitive element, one electrode of the capacitive element being connected to one source / drain region of the transistor, and the capacitive element. In the memory device in which the other electrode is stacked on the one electrode via a dielectric layer, the one electrode of the capacitive element in one of two memory cells adjacent to each other has the first conductivity. A second conductive layer that is a layer different from the first conductive layer, and the one electrode of the capacitive element in the other of the two memory cells is formed of a second conductive layer that is different from the first conductive layer. And the second conductive layer overlap each other at least at their ends, and the other electrode is a third conductive layer extending on the first and second conductive layers through the dielectric layer. It is formed, a memory device, wherein the overlapping area of each of said first and second conductive layer to the third conductive layer are substantially equal to each other.