JPS6068647A - Semiconductor memory - Google Patents

Abstract

PURPOSE:To largely reduce the exclusive area of a capacitor in a dynamic RAM without extremely decreasing the capacity by using the capacitor formed in a recess of a semiconductor substrate for two memory cells. CONSTITUTION:The first 1-transistor 1-capacitor structure memory cell is formed of the first MOS transistor Tr1 having the first drain region 12a, a gate oxidized film 14 and the first gate electrode 15a on a raised portion M, and the first capacitor region C1 formed on one side surface of the recess P and contacting with the transistor Tr1. Then, the second 1-transistor 1-capacitor structure memory cell is formed of the second MOS transistor Tr2 having the second drain region 12b, a gate oxidized film 14 and the second gate electrode 15b on the bottom of the recess P, and the second capacitor region C1 formed on the other side of the recess P and contacting with the transistor Tr2.

Description

DETAILED DESCRIPTION OF THE INVENTION (a) Technical Field of the Invention The present invention relates to a semiconductor memory device, and particularly to the structure of a dynamic random access memory (RAM).

fb) Prior Art and Problems A dynamic RAM has a structure in which a capacitor is provided in contact with an MIS transistor, and information is read out by the charge accumulated in the capacitor. Therefore, the detection sensitivity and reliability of information with a large amount of accumulated charge are increased. Figure 1 is a cross-sectional view schematically showing the structure of a conventional dynamic RAM. 2 is an isolation insulating film between elements, 3 is a drain region, 4 is a gate insulating film, 5 is a gate electrode, 6 is a capacitor edge film (dielectric film), 7 is a capacitor electrode, 8 is an insulating film, C is a capacitor , Tr are MIS transistors.

As shown in this figure, in the conventional structure, the eye capacitor C is formed in a planar shape, so by increasing its exclusive area to a certain extent, sufficient information read sensitivity and reliability can be obtained from the capacitor C. There was an accumulation of charges. Therefore, in the conventional structure, it is difficult to further reduce the area of the memory cell and further increase the degree of integration of the dynamic RAM.

(C) Object of the Invention The present invention has been made with the object of further increasing the degree of integration of a dynamic RAM without reducing the sensitivity and reliability of reading information.

(dl Structure of the Invention, that is, the present invention provides a semiconductor memory device in which a recess is formed on the surface of a semiconductor substrate, and a capacitor formed by laminating U[pole layers) is formed at least on the side surface of the recess with a dielectric film interposed therebetween. , a first (,')MIS) transistor is disposed in contact with the capacitor formed on a part of the side surface of the recess.
Configures a memory element with a transistor/1-capacitor structure,
A second MIS transistor is disposed in contact with the capacitor formed on the other side surface of the four parts to constitute a second memory element having a one-transistor/one-capacitor structure. .

(e) Examples of the Invention The present invention will be described below with reference to two figures. The second prisoner is a semiconductor memory device of the present invention, that is, a dynamic RAM.
This is a schematic cross-sectional view showing an example of a cell. In the figure, 11 is a p-type silicon (Sl) substrate, and 12a and 12b are n"
i m drain region, 13a, 13b, 13c are pl type channel cut regions, 14 is gate oxide film, 15a
, 1 and 5b are gate electrodes made of polycrystalline Si, etc., 16 is a dielectric film made of silicon dioxide (Si02), 17 is a capacitor electrode made of aluminum, etc., P is a concave portion 2M is a convex portion r c, T c, Capacitor region, Tr,
, Tr2 indicates an MO8 transistor.

In the dynamic RAM according to the present invention, for example, as shown in FIG. , p
A first MO8 transistor Tr consisting of a type drain region 12a, a gate oxide film 14, and a first gate electrode 15a.
A second MO8 transistor' [r2
will be placed.

A first capacitor region C3 and a second capacitor region C7 are formed on the side surfaces of the recess P, each of which is composed of a dielectric film 16 and a capacitor electrode 17. Note that the end portions of these capacitor regions that are not in contact with the gate electrode of the M/S transistor are PT x-shaped channel cut regions 13a and 13b formed on the upper surface of the convex portion M and the four portions.
, 13c from the drain regions of adjacent MO,S2) transistors.

That is, in this structure, the first drain region 12a on the convex portion M, the gate oxide film 14 and the first gate electrode 15a
A first MOS transistor Tr1 formed on a part of the side surface of the recess P;
A first 1-transistor/1-capacitor structure memory cell is formed by the first capacitor region C0 in contact with the
A second MO consisting of a second drain region 12b on the bottom surface of the recess P, a gate oxide film 14, and a second gate electrode 15b.
A second capacitor region C2 formed on the other side surface of the recess P and in contact with the second MO3 transistor Tr forms a memory cell having a second one-transistor one-capacitor structure. The following two points must be noted when using this structure. That is, the first point is that the gate of the MO8 transistor Tr2 formed on the bottom surface of the recess also functions on the side in contact with the substrate, and the gate length of the transistor is 1. +1. becomes. Therefore, the gate length is 1. +t, is formed on the convex portion M MO8l
- The width of the gate electrode 15b must be made narrow so that it is equal to the gate length of the transistor Tr.

The second point is that since the gate electrode 15b is formed on one side of the recess P, the area of the capacitor region formed on the side surface of the recess P is different. Therefore, in order to equalize the area, that is, the capacitance of each capacitor region, for example, Cr and Cx, it is necessary to adjust the arrangement positions of channel cut regions 13b, 13c, etc. that define the capacitor regions.

FIG. 3 is a schematic cross-sectional view showing another embodiment. In the figure, 11 is a p-type Si substrate, 12a, 12b, 12C are n-type drain regions, 13 is a pi-type child cut region, and 14 is a gate. Oxide film, 15a, 15b, 15c is gate electrode, 1
6 is a dielectric film, 17a.

], 7b, 17c are capacitor electrodes + PI T P
t is the concave part r Mlr M2 is the convex part + C1 + c2.
Cs is a capacitor region, 'l'r, 'L'r2.
'L'r3 indicates a Mos transistor.

This structure is symmetrical whereas the previous embodiments are asymmetrical with respect to the four sections. That is, in this structure ζ, all transistors are formed at the ends of the convex portions M, and all capacitors are formed within the concave portions P.

For example, the convex portion MLJ:,i first drain region 1
2a, a gate oxide film 14, and a gate electrode 15a.

A first capacitor region CI is formed by a dielectric film 16 and a first capacitor electrode 17a on a part of the side surface of the first recess P1 in contact with the first capacitor region CI.
A memory cell having a one-transistor/one-capacitor structure is formed in the second convex portion DIJ2.
3 A memory cell having a 1-transistor/1-capacitor structure is formed by the second capacitor region C8 formed on the other side surface of the transistor 1'r2 and the first recess P, and the following is similarly performed. Third. A fourth memory cell is formed.

As is clear from the above embodiments, the present invention uses four side surfaces formed on a semiconductor substrate surface as a capacitor formation region,
In addition, a capacitor formed on a part of the side surface of one recess is used for one memory cell.

The point is that the capacitor on the other side is used for another memory cell. That is, the capacitor formed in one recess is used for two memory cells.

Therefore, the area occupied by the capacitor in plan view is significantly reduced. In the structure of the present invention, the depth of the recess formed on the surface of the semiconductor substrate is suitably about 3 to 10 [μm].

If the depth is set to this level, a capacitor having almost the same capacitance as a conventional capacitor can be formed.

In the structure of the present invention, the pattern of the recesses formed on the C semiconductor substrate surface may be either striped or checkered.

(f) As described in detail, according to the present invention, the area occupied by a capacitor in a dynamic RAM can be significantly reduced without significantly reducing its capacity.

Therefore, the present invention is extremely effective in increasing the integration of diomic RAMs without sacrificing their sensitivity and reliability.

[Brief explanation of drawings]

FIG. 1 is a schematic sectional view of a conventional dynamic RAA'l, and FIGS. 2 and 3 are schematic sectional views of different embodiments of the structure of the present invention. In the figure, 11 is a p-type silicon substrate and 12a. 12b, 12C are NFL type drain regions, 13.13i
1113b and 13C are PTGE type channel cut regions. 4 is a gate oxide film, 15a, 15b, 15c are gate electrodes, 16 is a dielectric film, 17, 17a, 17b17
c is the capacitor electrode, P, P, , I) 2 is the recess 2
MM1. IVI2 is the convex part r 'l'r, l +llr
, + ""3 is y+os) transistor r C+ H
C2HCg indicates a capacitor region. Figure 1 Cicada, Figure 2 "r?I"

Claims (1)

[Claims] A recess is formed in the surface of the semiconductor substrate, a capacitor is formed in which an electrode layer is laminated on at least the side surfaces of the recess via a dielectric film, and the capacitor is in contact with the capacitor formed on a part of the side surfaces of the recess. A first M[s transistor is disposed in the recess to form a first one-transistor/one-capacitor structure memory element, and a second MIS is disposed in contact with the capacitor formed on the other side surface of the recess. ) A semiconductor memory device characterized in that a transistor is arranged to constitute a second memory element having a one-transistor/one-capacitor structure.