KR100344773B1 - Capacitors in semiconductor device and a layout thereof - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a capacitor of a semiconductor device. In particular, a dummy word line and a dummy bit line are respectively formed at an edge of a DRAM cell, and a plurality of dummy capacitors are formed between a dummy word line and a main word line that meet the dummy bit line. In the case where the dummy capacitor and the main capacitor are alternately formed between the dummy word line and the main word line located at one side thereof, the pair of dummy capacitors and the storage electrodes of the main capacitor are formed by merging them into one. The present invention relates to a capacitor structure and a layout of a semiconductor device which prevents data loss due to a short circuit of the capacitor, prevents a short circuit between adjacent capacitor electrodes, and increases the effective area to secure sufficient capacitance. The capacitor structure of the semiconductor device according to the present invention includes first and second impurity diffusion regions respectively formed in the first and second active regions of a semiconductor substrate in which a first active region and a second active region are separated by an isolation layer. And a first interlayer insulating film covering the semiconductor substrate including the first and second impurity diffusion regions, and first and second penetrating through the first interlayer insulating layer and in contact with the first and second impurity diffusion regions, respectively. A second interlayer insulating film covering a second contact plug, a first interlayer insulating film including surfaces of the first and second contact plugs, a plurality of bit lines formed on the second interlayer insulating film over the device isolation film, and A lower electrode formed through the second interlayer insulating layer and electrically connected to the first and second contact plugs and formed on the second interlayer insulating layer, and then formed on the surface of the lower electrode. It comprises an upper electrode.

Description

Capacitors in semiconductor device and a layout

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a capacitor of a semiconductor device. In particular, a dummy word line and a dummy bit line are respectively formed at an edge of a DRAM cell, and a plurality of dummy capacitors are formed between a dummy word line and a main word line that meet the dummy bit line. In the case where the dummy capacitor and the main capacitor are alternately formed between the dummy word line and the main word line located at one side thereof, the pair of dummy capacitors and the storage electrodes of the main capacitor are formed by merging them into one. The present invention relates to a capacitor structure and a layout of a semiconductor device which prevents data loss due to a short circuit of the capacitor, prevents a short circuit between adjacent capacitor electrodes, and increases the effective area to secure sufficient capacitance.

The structure of the DRAM memory cell of the prior art is placed in the direction of the sense amplifier located on the right side of the main cell to solve the loading effect during the photolithography process at the corner of the main cell when forming the capacitor of the cell. Four word lines and one dummy bit line are further formed to include a dummy cell pattern.

That is, in order to prevent poor patterning of the storage electrode due to the loading effect at the edge of the main cell during the photolithography process for forming the storage electrode of the main capacitor storing the data of the memory cell, A plurality of dummy gates are formed on an active region between a plurality of word lines that meet the dummy bit lines formed at the same time, and at the same time, a plurality of pairs are arranged on top of an active region of a pair of dummy word lines formed at a position closest to the sense amplifier. Dummy capacitors are formed in the longitudinal direction.

1 is a capacitor layout of a DRAM of a semiconductor device according to the prior art.

Referring to FIG. 1, a plurality of word lines 110 are parallel to each other on a semiconductor chip in which a sub-wordline driver (not shown) is positioned on the upper side and a sense amplifier (not shown) is disposed on the right side. It forms a column and is formed long in the longitudinal direction.

In the right end column of the plurality of word lines 110, a pair of dummy word lines 111 are also formed in parallel with the neighboring word lines 110.

A pair of impurity diffusion regions 13 are formed to correspond to each other around the word lines 110 and the dummy word lines 111.

One dummy bit line 121 is formed in the first row and intersects the word line 110 and the dummy word line 111 and forms a row in parallel with the sub-word line driver. 120 is a row. In this case, the bit line 120 and the dummy bit line 121 are formed so as not to overlap with the impurity diffusion region 13 serving as a source / drain.

The bit line 120 and the dummy bit line 121 are electrically connected to the impurity diffusion region 13 through the bit line contact 15.

One capacitor on each of the two edges of the pair of impurity diffusion regions 13 sharing one bit line contact 15, that is, on both corners of the impurity diffusion region 13 through which the two word lines 110 pass. Is formed. All of the dummy lower electrodes 161 of the capacitor are formed in a cell that meets the dummy bit line 121, and a pair of lower electrodes 160 are also formed in a cell where all of the pair of dummy word lines 111 pass. .

That is, the main lower electrode 160 of the capacitor is formed in the cell through which only one dummy word line 111 passes, and the main lower electrode 160 is also formed on all remaining cells.

The dummy and main lower electrodes are electrically connected to the impurity diffusion regions 13 through the lower electrode contacts 14, respectively.

The dummy lower electrode 161 positioned at the upper side between the last line word line 110 and the dummy word line 111 and the main lower electrode 160 positioned at the lower end thereof in the longitudinal direction have a lower bottom electrode forming process margin and are loaded. It is highly likely that short areas s will occur from each other by the effect.

That is, according to the related art, the loading effect prevention method using the dummy lower electrode of the capacitor contributes to improving the pattern forming ability of the main cell, but improves the space uniformity between the main lower electrode and the dummy lower electrodes. It is difficult to secure and a large number of minute short-circuit sites s are generated between them.

Therefore, when data '1' is written to all memory cells, data '1' is written to the main cell, but the dummy word line 111 is always kept at the ground level in the dummy cell, so data '1' is written. It is not written.

Subsequently, when reading data stored in the cells after a predetermined time elapses, the charges of the main cell shortly connected to the dummy lower electrode are discharged through the dummy lower electrode, and the 'data' in the shorted main cell. 0 fied fail 'occurs.

FIG. 2 is a cross-sectional view of a capacitor of the semiconductor device, taken along the line II ′ of FIG. 1 according to the prior art.

Referring to FIG. 2, a trench type device isolation film 101 defining a device isolation region and an active region is formed on a predetermined portion of a silicon substrate 100 as a semiconductor substrate.

An impurity diffusion region (not shown) is formed in the active region of the silicon substrate 100 to form the source / drain for the transistor of the memory cell.

A word line (not shown) formed of a gate is formed on the substrate 100 including the device isolation layer 101 and the active region, and a first interlayer insulating layer 102 formed of an oxide film on the substrate 100 including the word line. Is formed.

A capacitor lower electrode contact plug 14 penetrating a predetermined portion of the first interlayer insulating film 102 is formed in contact with the impurity diffusion region of the substrate.

The dummy bit line 121 and the plurality of bit lines 120 used in the main memory cell are formed in parallel with each other on the first interlayer insulating layer 102, and the dummy bit line 121 and the bit line 120 are formed in an oxide film. A second interlayer insulating film 103 composed of the same is covered.

The dummy lower electrode 161 and the lower electrode 160 are formed on the second interlayer insulating film 103 to penetrate the second interlayer insulating film 103 so as to be in electrical contact with the lower electrode contact plugs 14. have.

However, the minute lower portion s of the dummy lower electrode 161 and the lower electrode 160 is formed on the second interlayer insulating film 103.

However, the capacitor and the layout of the semiconductor device according to the related art described above are difficult to secure a space uniformity between the main lower electrode and the dummy lower electrode, and thus generate a large number of minute short-circuits s therebetween. When writing data '1' to all memory cells, data '1' is written to the main cell, but data '1' is written to the dummy cell since the dummy word line 111 always maintains the ground level. When the data stored in the cells is read after a predetermined time has passed, the charges of the dummy lower electrode and the finely shorted main cell are discharged through the dummy lower electrode and shorted to the main. Therefore, the present invention has a problem in that a 'data 0 fied fail' occurs in the cell. Accordingly, an object of the present invention is to form dummy word lines and dummy bit lines at the edges of DRAM cells, respectively. In the case where a plurality of dummy capacitors are formed between the dummy word line and the main word line which meet the line, and alternately formed between the dummy word line and the main word line located on one side thereof, as long as they are alternately formed The storage electrodes of the pair of dummy capacitors and the main capacitors are merged together to prevent data loss due to short circuits of these capacitors, to prevent short circuits with neighboring capacitor electrodes, and to increase the effective area. The present invention provides a capacitor structure and a layout of a semiconductor device for securing a capacitance.

A capacitor structure of a semiconductor device according to the present invention for achieving the above objects is a first formed in the first and second active regions of the semiconductor substrate defined by the first isolation region and the second active region separated by the device isolation film, respectively And a first interlayer insulating film covering the semiconductor substrate including the second impurity diffusion region, the first and second impurity diffusion regions, and the first and second impurity diffusion regions, respectively. A plurality of first and second contact plugs in contact, a second interlayer insulating film covering the first interlayer insulating film including surfaces of the first and second contact plugs, and a plurality of formed on the second interlayer insulating film on the device isolation film. A lower electrode formed on the second interlayer insulating film and having two bit lines, penetrating the second interlayer insulating film, and electrically connected to the first and second contact plugs; It comprises a dielectric film and an upper electrode sequentially formed on the surface.

A capacitor layout of a semiconductor device for achieving the above object includes a plurality of word lines arranged in parallel in a first direction to pass a pair of memory cell regions on a semiconductor substrate on which a plurality of memory cell regions and a dummy memory cell region are defined. And a pair of dummy word lines formed on one side of the word line so as to pass through the dummy memory cell region in parallel with the word lines, and a central portion overlapping the memory cell region with respect to the word lines. A second impurity diffusion region formed as in the memory cell region in the dummy memory cell region through which the first impurity diffusion regions shared by and remaining in the word line and the pair of dummy word lines respectively pass Regions, the first impurity diffusion region and the dummy war shared by the word line The second impurity diffusion region shared by a line is electrically connected by a bit line contact and is parallel to a second direction perpendicular to the first direction so as not to overlap the first impurity diffusion region and the second impurity diffusion region. One dummy bit line and a plurality of bit lines passing through the dummy memory cell region, and one unshared second impurity diffusion region of the dummy memory cell region and one unshared portion of the memory cell region. A first lower electrode electrically connecting the merged lower electrode formed over the first impurity diffused region, the second impurity diffused region overlapping the merged lower electrode, and the first impurity diffused region, respectively; A contact and a second lower electrode contact, a dielectric film and an upper electrode formed on the merged lower electrode; Group the word line and comprises a plurality of capacitors are formed such that the first impurity diffusion region and said second electrically connected to the upper second impurity diffusion regions that are not shared by the dummy word line.

1 is a capacitor layout of a DRAM of a semiconductor device according to the prior art.

FIG. 2 is a cross-sectional view of a capacitor of a semiconductor device, taken along the line II ′ of FIG. 1 according to the prior art.

Figure 3 is a capacitor layout of the DRAM of the semiconductor device according to the present invention

4 is a cross-sectional view of a capacitor of a semiconductor device taken along the line II-II 'of FIG. 3 according to the present invention.

Since the present invention is formed by combining a pair of dummy lower electrodes and a normal lower electrode in adjacent column directions of capacitors formed at the edge of the sense amplifier direction of the memory cell unit, the pattern is easy to define, and they are shorted to each other. Therefore, the problem of data writing and reading is fundamentally eliminated, and since the two lower electrodes are formed as one, the separation distance securing margin between these merged lower electrodes is increased, thereby easily preventing a short circuit.

That is, the word line is boosted to the Vpp level when performing the write and read functions, maintains the ground level when maintaining or storing data, and the dummy word line always maintains the ground level.

Therefore, when the dummy lower electrode and the normal lower electrode are combined to form one lower electrode, when the data '1' is written to all the cells, the data '1' is also applied to the memory cell having the lower electrode where the dummy lower electrode and the upper lower electrode are merged. Is written.

After a certain period of time, when data of such a memory cell is read, in a memory cell having a merged lower electrode, the leakage current through the dummy lower electrode node will be equivalent to the level of the leakage current through the normal lower electrode node. Inversion does not occur and data '1' is read.

Accordingly, the normal lower electrode merged with the dummy lower electrode can secure a higher memory cell capacitance and can sufficiently secure the separation distance between the plurality of merged lower electrodes, thereby preventing a short between them. have.

Hereinafter, with reference to the accompanying drawings will be described the present invention.

3 is a capacitor layout of the DRAM of the semiconductor device according to the present invention.

Referring to FIG. 3, a plurality of word lines 210 are parallel to each other on a semiconductor chip in which a sub-wordline driver (not shown) is positioned on the upper side and a sense amplifier (not shown) is disposed on the right side. It forms a column and is formed long in the longitudinal direction.

In the right end column of the plurality of word lines 210, a pair of dummy word lines 211 are also formed in parallel with the neighboring word lines 210.

A pair of impurity diffusion regions 23, which are active regions, are formed to correspond to each other around each of the word lines 210 and the dummy word lines 211. One impurity diffusion region is shared by two word lines.

One dummy bit line 221 is formed in the first row and intersects the word line 210 and the dummy word line 211 and forms a row in parallel with the sub-word line driver. 220 has a row at predetermined intervals. At this time, the bit line 220 and the dummy bit line 221 are formed so as not to overlap with the impurity diffusion region 23 serving as a source / drain.

The bit line 220 and the dummy bit line 221 are electrically connected to the impurity diffusion region 23 shared by the two word lines through the bit line contact 25.

One capacitor is formed on two edges of one impurity diffusion region 23 sharing one bit line contact 25, that is, on both corners of the impurity diffusion region 23 through which two word lines 210 pass. Is formed. Except for the cells where the dummy word line 211 and the dummy bit line 221 meet, all the cells that meet the dummy bit line 221 are formed with the dummy lower electrodes 261 of the capacitor.

In addition, the merged lower electrode 262 formed by merging the dummy lower electrode and the normal lower electrode on the impurity diffusion region 23 positioned between the dummy word line 211 and the adjacent word line 210 located on the left side. The two impurity diffusion regions 23 are formed to overlap each other. At this time, the merged lower electrode 262 is formed in a crown or square pillar structure.

The merged lower electrodes 262 may include a dummy bit line 221 forming a first row and a bit line 220 forming a second row, and a dummy word line 211 on the two bit lines 220. It is formed along. In this case, since the space d between the merged lower electrodes 262 is formed as two lower electrodes as compared to the prior art, the required space margin is sufficient, so that a short circuit between the merged lower electrodes 262 may be effectively prevented. have.

The dummy and top lower electrodes are electrically connected to the impurity diffusion regions 23 through the bottom electrode contacts 24, and the merged bottom electrode 262 is connected to the normal memory cell through the two bottom electrode contacts 24. And an impurity diffusion region 23 of the dummy memory cell.

The word line manufactured according to the embodiment of the present invention is boosted to the Vpp level when performing the write and read functions, maintains the ground level when maintaining or storing data, and the dummy word line always maintains the ground level.

Therefore, when data '1' is written to all cells, data '1' is also written to a memory cell having a lower electrode in which a dummy lower electrode and a normal lower electrode are merged.

After a certain period of time, when data of such a memory cell is read, in a memory cell having a merged lower electrode, the leakage current through the dummy lower electrode node will be equivalent to the level of the leakage current through the normal lower electrode node. Inversion does not occur and data '1' is read.

Accordingly, the normal lower electrode merged with the dummy lower electrode can secure a higher memory cell capacitance and can sufficiently secure the separation distance between the plurality of merged lower electrodes, thereby preventing a short between them. have.

4 is a cross-sectional view of a capacitor of the semiconductor device, taken along the line II-II 'of FIG. 3 according to the present invention.

Referring to FIG. 4, a trench type isolation layer 201 defining an isolation region and an active region is formed on a predetermined portion of the silicon substrate 200, which is a semiconductor substrate.

An impurity diffusion region (not shown) is formed in the active region of the silicon substrate 200 to form the source / drain for the transistor of the memory cell.

A word line (not shown) formed of a gate is formed on the substrate 200 including the device isolation layer 201 and the active region, and a first interlayer insulating layer 202 formed of an oxide film on the substrate 200 including the word line. Is formed.

A pair of capacitor lower electrode contact plugs 24 penetrating a predetermined portion of the first interlayer insulating film 202 is formed in contact with the impurity diffusion region of the substrate.

The dummy bit line 221 and the plurality of bit lines 220 used in the main memory cell are formed in parallel with each other on the first interlayer insulating layer 202, and the dummy bit line 221 and the bit line 220 are formed in an oxide film. A second interlayer insulating film 203 is formed.

In addition, a merged lower electrode 262 penetrating through the second interlayer insulating layer 203 so as to be in electrical contact with the lower electrode contact plugs 24, and the dummy lower electrode and the lower electrode are formed on the second interlayer insulating layer 203. Formed.

Therefore, since the dummy lower electrode and the lower electrode of the prior art are formed of a single lower electrode having a crown shape, there is no room for a minute short circuit portion on the second interlayer insulating film 203.

Accordingly, the present invention effectively prevents malfunction of write / read operations due to a short circuit occurring between the main lower electrode and the dummy lower electrode of the capacitor occurring at the corner of the main memory cell in the prior art and improves the capacitance of the capacitor. There is an advantage to be secured.

Claims (8)

A semiconductor substrate having a plurality of memory cell regions and a dummy memory cell region defined therein; A plurality of word lines arranged in parallel in a first direction to pass through the memory cell region, respectively; A pair of dummy word lines formed on one side of the word line so as to pass through the dummy memory cell region in parallel with the word lines; First impurity diffusion regions, each of which has a central portion overlapping the memory cell region with respect to the word line, is shared by the word line, and the remaining portions belong to one word line; Second impurity diffusion regions formed in the dummy memory cell region through which the pair of dummy word lines pass, as in the memory cell region; The first impurity diffusion region shared by the word line and the second impurity diffusion region shared by the dummy word line and the second impurity diffusion region are electrically connected to each other by a bit line contact, respectively. One dummy bit line and a plurality of bit lines passing through the dummy memory cell area formed in parallel in a second direction perpendicular to the first direction so as not to overlap the diffusion area; A merged lower electrode formed over an unshared second impurity diffusion region of the dummy memory cell region and an unshared first impurity diffusion region of the memory cell region; A first lower electrode contact and a second lower electrode contact electrically connecting the second impurity diffusion region and the first impurity diffusion region to the merged lower electrode, respectively; A dielectric film and an upper electrode formed on the merged lower electrode; And a plurality of capacitors formed to be electrically connected to an upper portion of the first impurity diffusion region and the second impurity diffusion region which are not shared by the word line and the dummy word line. The capacitor layout of claim 1, wherein the dummy memory cell region is arranged at an edge of the memory cell region. The capacitor layout of claim 1, wherein the merge lower electrode has a crown shape. The capacitor layout of claim 1, wherein the dummy memory cell region is formed to define the memory cell region. First and second impurity diffusion regions respectively formed in the first and second active regions of the semiconductor substrate having the first active region and the second active region separated by the device isolation film; A first interlayer insulating film covering the semiconductor substrate including the first and second impurity diffusion regions; First and second contact plugs penetrating the first interlayer insulating film and in contact with the first and second impurity diffusion regions, respectively; A second interlayer insulating film covering the first interlayer insulating film including the first and second contact plug surfaces; A plurality of bit lines formed on the second interlayer insulating film over the device isolation film; A lower electrode penetrating the second interlayer insulating film and electrically connected to the first and second contact plugs and formed on the second interlayer insulating film; And a dielectric film and an upper electrode sequentially formed on the lower electrode surface. The semiconductor device according to claim 5, wherein the lower electrode is formed to overlap the memory cell located at an edge of the semiconductor memory device and the dummy memory cell region formed of a plurality of memory cells and a dummy memory cell positioned at an edge of the memory cell. Capacitor of the device. The capacitor of claim 5, wherein the lower electrode is box-shaped or cylindrical. The capacitor of claim 5, wherein one of the bit lines is a dummy bit line.