KR100353553B1 - Capacitor layout in semiconductor device - Google Patents

Abstract

The present invention relates to a capacitor layout of a semiconductor device. In particular, a plurality of dummy capacitors are formed between a dummy word line and a main word line which form dummy word lines and dummy bit lines at edge portions of a DRAM cell and meet the dummy bit lines. In the case of forming a pair of the dummy capacitor and the main capacitor between the dummy word line and the main word line located on one side thereof, the pair of dummy capacitors and the lower electrodes of the main capacitor located at the edges are electrically connected to each other. It prevents data loss due to short circuit and replaces with redundancy cells in case of bridge phenomenon between probes during probe test, thereby improving product yield and packaging cost by repairing defects, and increasing effective area of lower electrode. Semiconductor field to ensure sufficient capacitance The present invention relates to a capacitor layout. A capacitor layout of a semiconductor device according to the present invention includes a word line formed in a first direction in a memory cell region on a semiconductor substrate on which a plurality of memory cell regions and a dummy memory cell region surrounding the memory cell region are defined, and the dummy memory. A capacitor including a dummy word line formed parallel to the word line on the semiconductor substrate in a cell region, a transistor connected to the word line, a dummy transistor connected to the dummy word line, and a lower electrode connected to a source of the transistor And a dummy capacitor including a dummy lower electrode connected to a dummy source of the dummy transistor, and a lower electrode connection pattern electrically connecting the lower electrode and the dummy lower electrode.

Description

Capacitor layout in semiconductor device

The present invention relates to a capacitor layout of a semiconductor device. In particular, a plurality of dummy capacitors are formed between a dummy word line and a main word line which form dummy word lines and dummy bit lines at edge portions of a DRAM cell and meet the dummy bit lines. In the case of forming a pair of the dummy capacitor and the main capacitor between the dummy word line and the main word line located on one side thereof, the pair of dummy capacitors and the lower electrodes of the main capacitor located at the edges are electrically connected to each other. It prevents data loss due to short circuit and replaces with redundancy cells in case of bridge phenomenon between probes during probe test, thereby improving product yield and packaging cost by repairing defects, and increasing effective area of lower electrode. Semiconductor field to ensure sufficient capacitance The present invention relates to a capacitor layout.

The structure of the DRAM memory cell of the prior art is placed in the direction of the sense amplifier located on the right side of the main cell to solve the loading effect during the photolithography process at the corner of the main cell when forming the capacitor of the cell. Four word lines and one dummy bit line are further formed to include a dummy cell pattern.

That is, in order to prevent poor patterning of the lower electrode due to the loading effect at the edge of the main cell during the photolithography process for forming the lower electrode of the main capacitor storing the data of the memory cell, A plurality of dummy gates are formed on an active region between a plurality of word lines that meet the dummy bit lines formed at the same time, and at the same time, a plurality of pairs are arranged on top of an active region of a pair of dummy word lines formed at a position closest to the sense amplifier. Dummy capacitors are formed in the longitudinal direction.

FIG. 1 is a capacitor layout of a DRAM of a semiconductor device according to the prior art, and is a partially enlarged layout of a capacitor lower electrode of a main cell portion MC1 and a dummy cell portion DC1.

Referring to FIG. 1, a plurality of word lines (not shown) are parallel to each other on a semiconductor chip in which a sub-wordline driver (not shown) is positioned on the upper side and a sense amplifier (not shown) is disposed on the right side. To form a column (long) in the longitudinal direction is formed.

On such a chip, dummy wordlines (not shown) are also formed in the edge column of the plurality of wordlines in parallel with neighboring wordlines.

A pair of impurity diffusion regions (not shown) are formed to correspond to each other around the word lines and the dummy word lines.

Intersect the word line and the dummy word line and form a row in parallel with the sub-word line driver, and one dummy bit line (not shown) is formed in the first row, and a plurality of bit lines (not shown) are formed. It is in a row. In this case, the bit line and the dummy bit line are formed so as not to overlap with the impurity diffusion region serving as a source / drain.

These bit lines and dummy bit lines are electrically connected to the impurity diffusion region through bit line contacts.

One capacitor is formed on two edges of the pair of impurity diffusion regions that share one bit line contact, that is, on both corners of the impurity diffusion region where two word lines pass. In the cell that meets the dummy bit line, the dummy lower electrodes 10 and 11 of the capacitor are both formed, and a pair of dummy lower electrodes are also formed in the cell through which the pair of dummy word lines pass.

That is, the main lower electrodes 12 and 13 of the capacitor are formed in the cell through which only one dummy word line passes, and the main lower electrodes (not shown) are also formed on all the remaining cells.

The dummy and main lower electrodes are electrically connected to the impurity diffusion regions through lower electrode contacts (not shown).

The dummy lower electrodes 10 and 11 positioned at the upper side between the last row word line and the dummy word line and the main lower electrodes 12 and 13 positioned at the lower end in the longitudinal direction have a lower margin for forming the lower electrode and have a lower loading effect. As a result, there is a high probability that a short portion B due to bridge phenomenon occurs.

That is, according to the related art, the loading effect prevention method using the dummy lower electrode of the capacitor contributes to improving the pattern forming ability of the main cell, but improves the space uniformity between the main lower electrode and the dummy lower electrodes. It is difficult to ensure, and many minute short circuit site | parts B are generated between them.

Therefore, when data '1' is written to all memory cells, data '1' is written to the main cell, but data '1' is not written to the dummy cell since the dummy word line always maintains the ground level. .

Subsequently, when reading data stored in the cells after a predetermined time elapses, the charges of the main cell shortly connected to the dummy lower electrode are discharged through the dummy lower electrode, and the 'data' in the shorted main cell. 0 fail 'occurs.

2 is a graph illustrating a level shift caused by a bridge phenomenon between a main cell and a dummy cell capacitor of a semiconductor device according to the related art.

Referring to FIG. 2, when a high data is written or a low data is written to a bridge phenomenon generating cell between a main cell disposed at an edge and a capacitor lower electrode of a dummy cell, a leakage current is generated in the dummy cell to an unidentified level. A data transition occurs, which causes a failure in reading the correct data and reading the data. In this case, reference numeral 'HLS' is a graph for explaining level transition when high data (VCC) is input, reference numeral 'LLS' is a graph for explaining level transition when low data is input, and reference numeral 'UL' is unconfirmed data. Indicates the level of (unknown data).

Therefore, the capacitor lower electrode layout of the semiconductor device according to the related art described above is difficult to secure a space uniformity between the main lower electrode and the dummy lower electrodes, and thus generates a large number of minute short-circuits s therebetween. Therefore, during the final inspection after the package process, a transition to an unidentified level occurs at the edge region of the memory cell, causing malfunction of the chip due to the data, causing unnecessary package cost and yield reduction.

Accordingly, an object of the present invention is to form a dummy word line and a dummy bit line at the edge of the DRAM cell, and to form a plurality of dummy capacitors between the dummy word line and the main word line that meet the dummy bit line. When the dummy capacitor and the main capacitor are formed in pairs between the main word lines located at one side thereof, the pair of dummy capacitors and the lower electrodes of the main capacitor located at the edges are electrically connected to prevent data loss due to short circuit of the capacitor. In the case of a probe test, when a bridge phenomenon occurs between capacitors, it is replaced with a redundancy cell to improve the yield of the product through defective repair and reduce the cost of packaging, and also increase the effective area of the lower electrode to secure sufficient capacitance. The present invention provides a capacitor layout of a semiconductor device.

A capacitor layout of a semiconductor device according to the present invention for achieving the above object is a word formed in the first direction in the memory cell region on the semiconductor substrate defined a plurality of memory cell region and a dummy memory cell region surrounding the memory cell region A line, a dummy word line formed on the semiconductor substrate in the dummy memory cell region in parallel with the word line, a transistor connected to the word line, a dummy transistor connected to the dummy word line, and a source connected to the transistor. And a dummy capacitor including a capacitor including a lower electrode, a dummy lower electrode connected to a dummy source of the dummy transistor, and a lower electrode connection pattern electrically connecting the lower electrode and the dummy lower electrode.

1 illustrates a capacitor layout at a main cell and a dummy cell boundary of a DRAM of a semiconductor device according to the related art.

2 is a graph showing a level shift caused by a bridge phenomenon between a main cell and a dummy cell capacitor of a semiconductor device according to the related art.

3 is a circuit diagram for explaining connecting the lower electrode of the main cell capacitor and the dummy cell capacitor according to the present invention.

4 is a chip layout of a semiconductor memory device in which both a main cell region and a dummy cell region having a main cell and a dummy cell capacitor lower electrode connection pattern according to the present invention are shown;

5 is a layout of a lower electrode pattern of a main cell and a dummy cell capacitor according to the present invention;

The present invention makes it easy to define a pattern by configuring a layout in which the dummy lower electrodes in the column direction of the capacitors formed on the edges of the sense amplifier direction of the memory cell unit and the normal lower electrode are merged into one, and they are shorted to each other. Therefore, the problem of data writing and reading is fundamentally eliminated, and since the two lower electrodes are formed as one, the separation distance securing margin between these merged lower electrodes is increased, thereby easily preventing a short circuit.

That is, the word line is boosted to the Vpp or Vcc level when performing the write and read functions, maintains the ground level when maintaining or storing data, and the dummy word line always maintains the ground level. At this time, the capacitance of the capacitor located at the edge of the main cell portion is increased by about twice the capacitance of the other normal capacitor.

Therefore, when the dummy lower electrode and the normal lower electrode are combined to form one lower electrode, when the data '1' is written to all the cells, the data '1' is also applied to the memory cell having the lower electrode where the dummy lower electrode and the upper lower electrode are merged. Is written.

After a certain period of time, when data of such a memory cell is read, in a memory cell having a merged lower electrode, the leakage current through the dummy lower electrode node will be equivalent to the level of the leakage current through the normal lower electrode node. Inversion does not occur and data '1' is read.

Accordingly, the normal lower electrode merged with the dummy lower electrode can secure a higher memory cell capacitance and can sufficiently secure the separation distance between the plurality of merged lower electrodes, thereby preventing a short between them. have.

Hereinafter, with reference to the accompanying drawings will be described the present invention.

3 is a circuit diagram illustrating a connection between a main cell capacitor and a lower electrode of a dummy cell capacitor according to an exemplary embodiment of the present invention, and the dummy cell part surrounds the main cell part at the edge of the main cell part and is defined on a chip.

Referring to FIG. 3, a dummy word line DWL is positioned in a dummy cell part while forming a row with a word line WL positioned at an edge of the main cell part.

The normal bit line BL of the main cell portion is formed to be orthogonal to the word line WL, and the dummy bit line DBL is formed in the dummy cell portion to be orthogonal to the dummy word line DWL in parallel with the normal bit line BL. It is.

A morph transistor connected to the normal capacitor is connected to the normal word line WL of the main cell unit, and a dummy MOS transistor having a dummy capacitor is connected to the dummy word line DWL of the dummy cell unit.

In an embodiment of the present invention, a layout is determined to electrically connect the dummy lower electrode node b of the dummy capacitor and the lower electrode node a of the normal capacitor.

FIG. 4 is a chip layout of a semiconductor memory device in which both a main cell region and a dummy cell region having a main cell and a dummy cell capacitor lower electrode connection pattern according to the present invention are shown, and FIG. 5 is according to the present invention shown in FIG. A partial enlarged layout view of the lower electrode patterns of the main cell and the dummy cell capacitor.

4 and 5, the main cell unit MC2 is positioned on one semiconductor chip, and the dummy cell unit DC2 is positioned at the edge of the semiconductor chip so as to surround the main cell unit MC2. At this time, although not shown, a plurality of normal word lines are formed in a row in the main cell unit MC2, and a plurality of normal bit lines are orthogonal to the word lines.

In the dummy cell unit DC2, dummy word lines and dummy bit lines are formed to extend from the normal word line and the normal bit line and have the same pattern.

One MOS transistor is formed in one normal memory cell defined by the region where the normal word line and the normal bit line cross each other, the gate of the MOS transistor is connected to the word line, the drain is connected to the bit line, and the source is It is connected to the lower electrode of the capacitor.

In addition, one dummy MOS transistor is formed in one dummy cell defined by an area where the dummy word line and the dummy bit line intersect, the gate of the dummy MOS transistor is connected to the dummy word line, and the drain is connected to the non-dermite line. The source is connected to the bottom electrode of the dummy capacitor.

Reference numeral 'E' denotes a boundary between the main cell portion MC2 and the dummy cell portion DC2, and an enlarged view of the portion E is shown in FIG. 5.

Referring to FIG. 5, on the semiconductor chip having the layout illustrated in FIG. 4, each of the normal lower electrodes 52 and 53 and each of the cells of the dummy cell portion DC2 is connected to the cells of the main cell portion MC2. 50 and 51 are formed in parallel.

One normal lower electrode and one dummy lower electrode corresponding to each other form a layout in the form of being electrically connected to each other by a lower electrode connection pattern. That is, the first normal lower electrode 52 positioned on the left side of the drawing is connected by the first dummy lower electrode 50 and the first lower electrode connection pattern 55 of the dummy cell unit DC2 adjacent thereto. The second normal lower electrode 53 positioned on the right side is connected by the second dummy lower electrode 56 and the second lower electrode connection pattern 56 of the dummy cell unit DC2 adjacent thereto.

The dummy and normal lower electrodes are electrically connected to the sources consisting of impurity diffusion regions through lower electrode contacts (not shown), and the lower electrode electrically connected by the lower electrode connection pattern is connected through two lower electrode contacts. It is electrically connected to a source of a normal memory cell and a dummy memory cell.

The word line manufactured according to the embodiment of the present invention is boosted to the Vpp level when performing the write and read functions, maintains the ground level when maintaining or storing data, and the dummy word line always maintains the ground level.

Therefore, when data '1' is written to all cells, data '1' is also written to a memory cell having a lower electrode in which a dummy lower electrode and a normal lower electrode are merged.

After a certain period of time, when data of such a memory cell is read, in a memory cell having a merged lower electrode, the leakage current through the dummy lower electrode node will be equivalent to the level of the leakage current through the normal lower electrode node. Inversion does not occur and data '1' is read.

Accordingly, the normal lower electrode merged with the dummy lower electrode can secure a higher memory cell capacitance and can sufficiently secure the separation distance between the plurality of merged lower electrodes, thereby preventing a short between them. have.

Accordingly, the present invention effectively prevents malfunction of write / read operations due to a short circuit occurring between the main lower electrode and the dummy lower electrode of the capacitor occurring at the corner of the main memory cell in the prior art and improves the capacitance of the capacitor. In addition, when a probe phenomenon occurs, bridges between capacitors are replaced with redundancy cells, thereby improving the yield of the product through defect repair and reducing the cost of packaging.

Claims (5)

A word line formed in a first direction in the memory cell region on the semiconductor substrate having a plurality of memory cell regions and a dummy memory cell region surrounding the memory cell region; A dummy word line formed on the semiconductor substrate in the dummy memory cell region in parallel with the word line; A transistor connected to the word line; A dummy transistor connected to the dummy word line; A capacitor including a lower electrode connected to a source of the transistor; A dummy capacitor including a dummy lower electrode connected to a dummy source of the dummy transistor; And a lower electrode connection pattern electrically connecting the lower electrode and the dummy lower electrode. The method according to claim 1, And a bit line and a dummy bit line formed to traverse the word line and the dummy word line in a second direction perpendicular to the first direction, respectively. The method according to claim 2, And the word line / bit line and the dummy word line / dummy bit line constitute normal memory cells and dummy memory cells, respectively. The method according to claim 3, And the capacitor is formed in the normal memory cell, and the dummy capacitor is formed in the dummy memory cell. The method according to claim 1, And the lower electrode connection pattern, the lower electrode, and the dummy lower electrode are formed of the same conductor in the same step.