JPH06164556A - Transmission characteristic measuring device - Google Patents

Abstract

PURPOSE:To measure the delay characteristic of a transmission line through the use of a pseudo random signal and without being restricted by the period of the pseudo random signal. CONSTITUTION:A specified bit error by bit inversion is added to arbitrary timing after synchronism is established by a bit error addition circuit 14 and the pseudo random signal from a pseudo random signal generation circuit 11 is transmitted to a transmission line 1, and a transmission timing signal is outputted to a delay quantity detection circuit 29 at that time. The bit error of the signal, which is returned from the transmission line 1, is detected in an error detection circuit 23. A specified bit error detection circuit 26 receiving the error signal outputs a received timing signal to the delay quantity detection circuit 29 when the error signal coincides with the error signal corresponding to the specified bit error added by the bit error addition circuit 14. The delay quantity detection circuit 29 measures time till the received timing signal is received from time when a transmission timing signal is received, and detects the delay quantity of the transmission line 1.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a transmission characteristic measuring device for measuring a signal delay amount occurring in a transmission line or a transmission device in a digital communication network.

[0002]

2. Description of the Related Art A transmission line 1 for transmitting a digital signal is generally connected between transmission devices 2 and 3 as terminals via a plurality of transmission lines 4 and a repeater 5, as shown in FIG. The signal sent from one transmission device is
It is transmitted to the other transmission device with a delay amount specific to the line. There are a signal delay amount and a signal error rate as important transmission characteristics of this kind of transmission line, and conventionally, a transmission characteristic measuring device (hereinafter referred to as a measuring device) capable of measuring both of these two properties is used.

As a delay measurement for a transmission line, a measuring device 6 is connected to one transmission device 2 and the other transmission device 3 is connected.
A general method is to obtain the round-trip delay amount by measuring the time taken for the signal sent from the measuring device 6 to be returned and returned by the transmission device 3 in the return mode. In addition, in the case of error rate measurement, [1]
When

Pseudo-random signals with a predetermined bit period with which the occurrence probabilities of [0] are almost equal are sent out to the transmission line, and the signal sequence returned from the transmission line and the sent signal are compared in bit units, and within a fixed time or within a predetermined period. A method of determining the number of error bits as an error rate is used.

As a signal for measuring the delay amount of a digital line, a clock signal (a) is used as shown in FIG.
There has been a method of using a signal (b) in which [1] continues from t0 as a measurement signal in synchronization with. When using such a measurement signal, the received signal is

The timing t1 at which [0] changes to [1] is detected, and t1-t0 is obtained as the round trip delay amount of this line.

However, according to this method, since the signal [1] which does not occur on the actual line is measured by the continuous signal, the true delay amount in the actual operation of the line cannot be measured, and In this method, since the delay amount is obtained at the timing when the first [1] is received, it is directly influenced by the error bit generated in the line itself, and it is difficult to measure the line having a high error rate. There's a problem.

In order to solve this, Japanese Patent Laid-Open No. 4-192
In Japanese Patent Laid-Open No. 830, as shown in FIG. 12, a time difference between a timing t0 when a specific bit pattern A [010011] in a pseudo-random signal is sent to a transmission line and a timing t1 when this bit pattern A is received is calculated. The applicant of the present application has proposed a technique for determining the delay amount of a line. In this technique, since the pseudo-random signal is used as it is, the true delay amount can be measured under the condition almost equal to the signal train actually generated in the line, and moreover, the coincidence of the pattern of the predetermined bit length is detected. , The influence of the error due to the line is stochastically small.

[0007]

However, in this method, since the specific pattern that always occurs once in one period of the pseudo random signal is used, when the line delay time is longer than the period of the pseudo random signal, The transmission timing of the current cycle precedes the reception timing of the specific pattern of the cycle, so that the correct delay time cannot be measured, and the measurable delay amount is limited by the cycle of the pseudo-random signal. .

It is an object of the present invention to solve this problem and to provide a transmission characteristic measuring apparatus capable of measuring the delay amount of a line without being limited by the period of a pseudo random signal.

[0009]

In order to achieve the above object, a transmission characteristic measuring apparatus of the present invention comprises a pseudo random signal generating circuit (1) for outputting a pseudo random signal of a predetermined bit period, and the pseudo random signal generating circuit. A specific bit error due to bit inversion is added to the pseudo random signal output from the circuit at an arbitrary timing and sent as a measurement signal to the transmission line under test, and a transmission timing signal synchronized with the transmission timing of the bit error is output. A bit error adding circuit (14) for receiving the measurement signal that has reciprocated through the transmission line under test, and each bit data of the pseudo random signal included in the measurement signal is output from the pseudo random signal generation circuit. Error detection circuit (23) for detecting whether or not each bit data of the random signal matches
And a specific bit error that receives an error signal from the error detection circuit and outputs a reception timing signal when the error signal matches an error signal corresponding to the specific bit error added by the bit error addition circuit. Detection circuit (26)
And a delay amount for detecting the signal delay amount of the transmission line under test by the time difference from the transmission timing signal output from the bit error addition circuit to the reception timing signal output from the specific bit error detection circuit. And a detection circuit (29).

[0010]

With this configuration, in the transmission characteristic measuring apparatus of the present invention, a specific error due to bit inversion is added to the pseudo random signal output from the pseudo random signal generating circuit at an arbitrary timing, and the pseudo random signal is transmitted to the transmission line under test. Sent out,
A transmission timing signal is output when the specific bit error is transmitted. The error detection circuit detects a match or mismatch between each bit data of the pseudo random signal included in the measurement signal that travels back and forth through the transmission line under test and each bit data of the pseudo random signal output from the pseudo random signal generation circuit. It The specific bit error detection circuit outputs a reception timing signal when the error signal received from the error detection circuit matches the error signal corresponding to the error of the specific bit added by the bit error addition circuit. The delay amount detection circuit which receives the transmission timing signal and the reception timing signal detects the signal delay amount of the transmission line under test from the time difference.

[0011]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 shows the configuration of a transmission characteristic measuring apparatus 10 of one embodiment. This measuring device has a function of measuring the error rate as well as the delay amount of the transmission line, and measures the delay amount using a pseudo random signal for error measurement.

In FIG. 1, the pseudo-random signal generating circuit 11 repeatedly outputs a pseudo-random signal (a) having 2 ^N -1 bit (N is an integer of 2 or more) as one cycle. As shown in the case of N = 4, 4 (= N) flip-flops 12 _{1 to} 12 ₄ forming a 4-stage shift register circuit and an EX-OR circuit 13 are provided, and the final stage flip-flop 12 is formed. _By inputting the exclusive OR of the output of _{4 and} the output of the first-stage flip-flop 12 ₁ to the first-stage flip-flop 12 ₁ , a pseudo-random signal having 15 bits as one cycle is generated in the final-stage flip-flop 12 _4. Is output to the bit error adding circuit 14 in synchronization with the clock signal.

The bit error addition circuit 14 adds a specific bit error to this pseudo random signal and outputs it. For example, as shown in FIG. 3, it is composed of an EX-OR circuit 15 and an error pattern generation circuit 16. , An error pattern signal in which [1] is continuous for 4 bits is input to the EX-OR circuit 15 from the error pattern generation circuit 16, and a pseudo-random signal whose logic is inverted only during the 4-bit period is a measurement signal for delay measurement. And the error pattern signal is

During [0], the pseudo random signal from the pseudo random signal generation circuit 11 is output as it is.

The error pattern generation circuit 16 receives only one clock cycle length by inputting a synchronization confirmation signal or turning on the switch 17.

The signal of [0] is flipped from the timer circuit 18 to flip-flops 19 ₁ to 19 forming a 4-stage shift register.
Input to the first stage of 9 ₄

The signal of [0] is shifted by one clock, and the NAND circuit 20 outputs an error pattern signal having a 4-clock cycle length. The error pattern signal is output to the delay amount detection circuit 29, which will be described later, as a transmission timing signal (b) whose falling timing is the transmission timing of the measurement signal.

In this way, the measurement signal (c) containing error bits of 4 consecutive bits is sent to the transmission line under test 1 via the signal transmission circuit 21. It should be noted that, at the time of this signal transmission, a clock signal component for receiving the measurement signal is included and transmitted.

The transmission line under test 1 is preset to return the signal from the measuring device as described above, and the signal reciprocated by the return of the line is clocked by the signal receiving circuit 22 (reception clock). Signal) is extracted and received, and is input to the error detection circuit 23.

The error detecting circuit 23 includes a reference signal generating circuit 24 for generating the same pseudo random signal as the pseudo random signal generating circuit 11 as a reference signal, and the reference signal generating circuit 2.
4 and the random signal (d) received by the signal receiving circuit 22. The bit error detecting circuit 25 determines whether the reference signal (e) and the random signal (d) received by the signal receiving circuit 22 are in units of bits.

The reference signal generating circuit 24 includes a random signal generating section having the same structure as that of the pseudo random signal generating circuit 11 shown in FIG. 2, and the first N bits of the random signal received by the signal receiving circuit 22 ( (In the above example, a 4-bit signal is used as an initial value, and each flip-flop of the random signal generation unit is initialized with an initialization unit (both not shown). The output pseudo random signal is output to the bit error detection circuit 25 as a reference signal, and the reference signal is synchronized with the received signal. If the initially set bit data contains an error due to the transmission line, the bit error detection circuit 25 outputs an error signal.
The reference signal generation circuit 24 continuously resets the initial value until, for example, N bits continue to generate no errors after the initial setting, or until the error rate becomes a predetermined value or less, and N bits continue to generate an error. When the error does not occur, or when the error rate falls below a predetermined level, the synchronization confirmation signal is output.

The error signal (f) from the bit error detection circuit 25 is input to the specific bit error detection circuit 26. The specific bit error detection circuit 26 receives the error signal sequence output from the bit error detection circuit 25 after the synchronization is established,
When this error signal sequence matches the error pattern added by the bit error adding circuit 14, the reception timing signal (g)
Is output.

FIG. 4 shows an example of the circuit configuration of the specific bit error detection circuit 26 corresponding to the case where an error of continuous 4 bits is added by the bit error addition circuit 14 as described above. When the error signal [1] indicating that there is an error is continuously input from the bit error detection circuit 25 to the four flip-flops 27 _{1 to} 27 ₄ formed by 4 bits, the flip-flops 27 ₁ to 27 ₁ to 27 _{4 are formed} .
All of the outputs of 27 ₄ are [1], and the AND circuit 28 which receives the output thereof outputs the reception timing signal of [1] for one cycle thereof in synchronization with the reception clock.

The transmission timing signal from the bit error addition circuit 14 and the reception timing signal from the specific bit error detection circuit 26 are input to the delay amount detection circuit 29.

The delay amount detection circuit 29 has a configuration shown in FIG. 5, for example, to measure the time from the input of the transmission timing signal to the input of the reception timing signal to measure the delay amount (delay time) of the transmission line under test. ) Is detected. That is,
By setting the output (h) of the set / reset circuit 30 composed of an RS type flip-flop or the like to [1] at the time of the fall of the transmission timing signal, the unit time of the unit time signal generation circuit 31 of 1 μS The pulse passes through the AND circuit 32, and the passing signal is used as the count input signal (i) to start counting by the counting circuit 33. Then, at the fall of the reception timing signal, the output of the set / reset circuit 30

The count is ended by resetting to [0], and the count result of the count circuit 33 after this reset is output as a delay time. The delay amount detected by the delay amount detection circuit 29 is numerically displayed by the delay amount display 34.

Next, the operation of adding a 4-bit length bit error to the N = 4 pseudo-random signal as described above will be described with reference to the timing chart of FIG. In this description, the delay time of the measuring device itself is not considered.

The pseudo random signal (a) from the pseudo random signal generating circuit 11 is [B1, B2, ..., B14, B
15] are repeatedly output as one cycle (B1 to B15 are

[0] or [1]).

This pseudo random signal is supplied to the error detection circuit 2
While 3 is not determined to be synchronous, as shown in FIG. 6C, the bit error addition circuit 14 sends the signal as it is to the transmission line 1 via the signal transmission circuit 21, and after an unknown delay time,
As shown in (d), the signal is received by the signal receiving circuit 22, and the error detecting circuit 23 detects a bit error with the reference signal (e). Here, as in (f), the reference signals B12 to B12
There is no error in 15 bits and the received signal for 4 consecutive bits, and t0
Assuming that the synchronization is fixed at this time, the error pattern signal (transmission timing signal) rises at time t1 synchronized with the clock on the transmission side immediately after that as shown in FIG. Therefore, during this period, error bits E6 to E9 are transmitted to the transmission line 1 by inverting B6 to B9. Further, at the time t2 of the fall of the transmission timing signal (b), the delay amount detection circuit 29 enters the set state as shown in (h), and the unit time pulse counting is started as shown in (i).

When there is no error due to the line itself and the transmitted error bits E6 to E9 are received with a delay of the transmission line delay time, the error signal (f) of [1] from the bit error detection circuit 25 is t3. 4 bits are continuously output from the time. Therefore, the reception timing signal rises in synchronization with the fourth-bit error signal as shown in (g) and falls at t4. The delay amount detection circuit 29 receives the received signal and enters the reset state (h) at t4, and the counting of the unit time pulse is completed. The count value D from t2 to t4 is
A numerical value is displayed on the delay amount display 34 as the round trip delay amount of the transmission line. From this display, the delay amount of the transmission line 1 is DμS.
It can be seen that it is (microsecond).

Since the error bit is added sporadically, even if the delay amount of the transmission line is longer than one period (15 × clock period in this case) of the pseudo-random signal, the delay amount can be accurately set. Can be measured. Also, unless an error due to the line itself occurs during the period from t3 to t4, the error has no effect on the measurement.

Further, if an error by the line itself happens by accident between t3 and t4 and any one of the specific bit errors returns to the correct bit, one delay after the synchronization is established. Although the measurement will fail, in such a case, the switch 17 may be turned on to add a specific bit error again. Further, the delay measurement may be started only by operating the switch 17 without automatically adding a specific bit error after the synchronization is established, and a predetermined time has elapsed since the synchronization was established by using a timer. Sometimes, bit errors may be automatically added, or errors may be automatically added at intervals of several cycles of the pseudo random signal, and the timing may be arbitrary. Further, the specific bit error may not be continuous 4 bits as in the above embodiment, but may be continuous 5 bits or an error may be added by a plurality of bits before and after a correct bit.

When an error occurs in the bit before and after the specific bit error due to the line, the reception timing deviates from the normal timing. In this case, an error longer than the added error bit length is detected. In this case, the received signal may be ignored and remeasurement may be performed, or an averaging process based on a plurality of delay measurements may be performed.

In this embodiment, the case where a 4-bit length bit error is added to the N = 4 pseudo-random signal has been described, but there is no reason to make the two equal, and for example, a pseudo-random signal with N = 32 is used. A bit error having an 8-bit length may be added. Even in this case, the reference signal generation circuit 24 of the pseudo random signal generation circuit 11 and the error detection circuit 23 is changed to a configuration corresponding to N = 32, and the bit error addition circuit 14 is added. And the specific bit error detection circuit 26 can be applied in exactly the same manner only by changing it to a structure corresponding to the 8-bit length.

Further, according to the error rate state of the line itself,
It is also possible to change the length of the error bit to be added. FIG. 7 shows a measuring apparatus 1 in which the length of the error bit to be added can be changed by the error bit length setting circuit 35.
0'is shown.

In this case, as shown in FIGS. 8 and 9, the bit error addition circuit 14 'and the specific bit error detection circuit 2 are provided.
Flip-flops 19 _{1 to} 19 _M and 27 ₁ to 2 in 6 '
When the maximum number of _M stages is 7 _{M and} the bit length P (P <M) is designated by the error bit length setting circuit 35, P +
The flip-flops of the first and subsequent stages are set in the signal generation circuit 3
If it is constituted by 6 and 37 so that it is always kept in the set state, it becomes possible to add and detect an error of an arbitrary bit length according to the line state.

In the above embodiment, the delay time of the measuring apparatus itself was not considered, but the delay time D ₀ of the measuring apparatus itself is the state in which the signal transmitting circuit 21 and the signal receiving circuit 22 are directly connected. Since it can be obtained by the same delay measurement as in the above-mentioned embodiment, the delay of only the transmission line can be measured by subtracting the delay time D ₀ of the measuring device itself from the delay time D when measuring the transmission line. it can. This subtraction can be or previously preset [-D _0] to the counting circuit 33, a method such as reducing or shortening the D ₀ minutes by counting time, or from the count result D by calculating the D ₀ is applied.

[0035]

As described above, the transmission characteristic measuring apparatus of the present invention sends a signal obtained by adding a specific bit error due to bit inversion to a pseudo random signal at an arbitrary timing to a transmission line as a measurement signal, and at that time. The delay amount of the transmission line is measured by measuring the time from the transmission timing of to the reception timing when the bit error of the signal returned on the transmission line matches the bit error added at the time of transmission. .

Therefore, it is possible to send a measurement signal having a random characteristic almost equal to that of the pseudo-random signal to the transmission line, and it is possible to accurately measure the delay under the condition close to the signal of the actual line. Further, since the timing of adding the specific bit error is arbitrary, it is possible to perform the delay measurement without being limited by the period of the pseudo random signal.

[Brief description of drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention.

FIG. 2 is a circuit diagram showing an example of a circuit configuration of a main part of one embodiment.

FIG. 3 is a circuit diagram showing an example of a circuit configuration of a main part of one embodiment.

FIG. 4 is a circuit diagram showing an example of a circuit configuration of a main part of one embodiment.

FIG. 5 is a circuit diagram showing an example of a circuit configuration of a main part of one embodiment.

FIG. 6 is a timing chart of each unit for explaining the operation of the embodiment.

FIG. 7 is a block diagram showing another embodiment of the present invention.

8 is a circuit diagram showing a circuit configuration of a main part of FIG.

9 is a circuit diagram showing a circuit configuration of a main part of FIG.

FIG. 10 is a connection diagram between a transmission line and a measuring device.

FIG. 11 is a timing diagram showing a conventional delay measurement method.

FIG. 12 is a timing diagram showing another conventional delay measurement method using a pseudo-random signal.

[Explanation of symbols]

 1 Transmission Line 10 Transmission Characteristic Measurement Device 11 Pseudo Random Signal Generation Circuit 14 Bit Error Addition Circuit 23 Error Detection Circuit 24 Reference Signal Generation Circuit 25 Bit Error Detection Circuit 26 Specific Bit Error Detection Circuit 29 Delay Amount Detection Circuit

Claims (1)

[Claims] 1. A pseudo random signal generating circuit (1) for outputting a pseudo random signal having a predetermined bit period, and a specific bit error due to bit inversion in a pseudo random signal output from the pseudo random signal generating circuit at an arbitrary timing. To the transmission line under test as a measurement signal, and outputs a transmission timing signal synchronized with the transmission timing of the bit error, and a measurement circuit that reciprocates through the transmission line under test. An error detection circuit (23) that receives a signal and detects whether or not each bit data of the pseudo random signal included in the measurement signal matches each bit data of the pseudo random signal output from the pseudo random signal generation circuit. ) And an error signal from the error detection circuit, and the error signal is added by the bit error addition circuit. A specific bit error detection circuit (26) that outputs a reception timing signal when it matches an error signal corresponding to a specific bit error, and the specific bit error detection after the transmission timing signal is output from the bit error addition circuit. A transmission characteristic measuring device comprising: a delay amount detection circuit (29) for detecting a signal delay amount of the transmission line under test based on a time difference until a reception timing signal is output from the circuit.