JPH0410726A - Instrument for counting delay time of network - Google Patents

Abstract

PURPOSE:To obtain an accurate measuring result of delay time by measuring only the receiving interval of respective receiving flags after sending the initial transmitting flag from a transmitting flag forming means, and calculating the delay time based upon the measured result. CONSTITUTION:The transmitting flag forming means 121 sends a transmitting flag to a network 111 at a constant period, and at the time of receiving the initial transmitting flag from the means 121, a receiving interval measuring means 123 starts operation, successively inputs receiving flags for which delay values corresponding to the internal state of the network 111 are added correspondingly to respective transmitting flags and measures the receiving intervals between two continued receiving flags. A delay time calculating means 125 accumulates the receiving intervals based upon the measurement of the means 123 and subtracts a value obtained by multiplying the transmitting flag sending interval with an integer from the accumulated value to calculate the delay time from the sending of the each transmitting flag up to the input of its corresponding receiving flag. Since the delay time is counted by measuring only the receiving interval of the receiving flags as a whole, the accurate delay time can be calculated.

Description

[Detailed Description of the Invention] [Summary] This invention relates to a navy blue delay time measuring device that measures the delay time of data input and output via a network in order to know the characteristics of a network such as a packet switching network. In order to obtain accurate measurement results, there is a transmission flag generation means that sends transmission flags to the network at regular intervals, and the operation starts when the first transmission flag is sent from the flag generation means. The reception flags to which a delay is added according to the internal state of the network are sequentially input corresponding to each of the reception flags. Delay time that calculates the delay time from sending out a sending flag until the corresponding receiving flag is input by accumulating the receiving interval and subtracting an integer multiple of the sending interval of the sending flag from this cumulative result. and calculation means.

[Industrial application field]

In order to know the characteristics of a network such as a packet switching network, the present invention provides
The present invention relates to a network delay time measuring device that measures the delay time of data input/output via a network.

[Prior Art] In a packet-switched network, the transmission route for packet data varies depending on the internal state of the network, so the delay time of packet data received via this packet-switched network is not constant. Therefore, it is necessary to measure the packet data delay time, examine the network characteristics, and determine the reception buffer setting time. A delay time measurement device measures the delay time of this packet data.

FIG. 6 shows the configuration of a conventional delay time measuring device.

A conventional delay time measurement device 611 includes a pattern generator 613 that outputs a transmission flag (pulse) a with a constant period.
A counter 615 is reset each time this transmission flag a is output, and when a reception flag b to which a delay is added in the bucket switching network 621 to the transmission flag a is input, the value of the counter 615 ( A personal computer (hereinafter referred to as a personal computer) 619 receives and analyzes the delay time held in the latch 617.
The distribution of delay times was analyzed and the analysis results were displayed.

[Problem to be solved by the invention]

By the way, in the conventional method described above, the transmission flag a
was output, the counter 615 was reset and the time from the output of this sending flag a until receiving flag b was sent back was measured, so the next sending flag was sent before receiving flag b was sent back. There is a problem in that when a is output, the counter 615 is reset before the measured value is read out, making it impossible to obtain accurate measurement results.

For example, as shown in FIG. 7, when the transmission flag a and the reception flag b are input and output alternately (A and A' and B and B
), the normal delay time xl.

When X2 is measured by the counter 615, but the transmission flag a is output before the reception flag b is returned (when D is output before the C corresponding to C is returned)
In this case, instead of the normal delay time X3, the measurement result is X4, which is the time interval between the next transmission flag a and the reception flag b corresponding to the previous transmission flag a.

The present invention was created in view of these points, and an object of the present invention is to provide a network delay time measuring device that can obtain accurate measurement results.

[Means to solve the problem]

FIG. 1 is a block diagram of the principle of a network delay time measuring device according to the present invention.

In the figure, a transmission flag generating means 121 sends a transmission flag to the network 111 at regular intervals.

The reception interval measuring means 123 starts operating when the first transmission flag is sent from the flag generation means 121, and thereafter performs reception with a delay added according to the internal state of the unit 111 corresponding to each transmission flag. The flags are manually added one by one,
Measure the reception interval between two consecutive reception flags.

The delay time calculation means 125 accumulates the reception intervals measured by the reception interval measurement means 123, and subtracts from this cumulative result a value obtained by multiplying the sending interval of the transmission flag by an integer.
Calculate the delay time from when a transmission flag is sent until the corresponding reception flag is input.

Therefore, the overall configuration is such that the delay time is measured by measuring only the reception interval of the reception flag.

[For production]

When the transmission flag generation means 121 outputs transmission flags at regular intervals, the network 111 returns reception flags to which a delay according to the internal state of the network 111 itself has been added corresponding to each of the transmission flags. .

The reception interval measuring means 123 starts its operation when the first transmission flag is sent out, and thereafter measures the reception interval of the reception flag every time the reception flag is sequentially input.The delay time calculation means 125 measures the reception interval of the reception flag. The delay time is calculated by subtracting a value obtained by multiplying the transmission interval of the transmission flag by an integer from the accumulated result.

For example, the transmission interval of transmission flags is T, the time from when the first transmission flag is sent until the first reception flag is input is Xl, and the reception interval of reception flags that are input sequentially thereafter is X2 + X3 + .・Then, the delay time added to the first transmission flag is (X
I +X2) 'rx1, (XIx2+x3)-T
X2. It is calculated by dividing...

In the present invention, after the first transmission flag is sent out from the transmission flag generation means 121, only the reception interval of each reception flag is measured by the reception interval measuring means 123, regardless of the size of the sending interval of the transmission flag. Based on this measurement result, the delay time calculation means 125 calculates an accurate delay time.

[Example] Hereinafter, an example of the present invention will be described in detail based on the drawings.

FIG. 2 shows the configuration of a network delay time measuring device in an embodiment of the present invention.

In the figure, 211 is a delay time measuring device, 221 is a pattern generator, 223 is a 7-bit reset type flip-flop (R3-FF), 225, 227 and 2
29 is an inverter, 231 is an AND gate, 233
235 is a clock generation circuit, 237 is a latch, 241 is a personal computer, and 251 is a packet switching network.

The pattern generator 221 generates the transmission flag 5FLG at a constant period, and the generated transmission flag 5
The FLG is input to the packet switching network 251 and is also input to the reset terminal R of the terminal R3-FF 223 via the inverter 225.

In R3-FF223, the power-on reset signal XR3T created when the power is turned on is input to the set terminal S, and when the power is turned on, it is set and outputs a logic "1" signal from the output terminal Q. , the first transmission flag 5F output from the pattern generator 221
It is reset by LG, and thereafter a logic 0' signal is output from the output terminal Q.

AND gate 231 connects R3 via inverter 227.
-The output of FF223 is connected to one input terminal of inverter 2.
The reception flag 5FLG via 29 is input to the other input terminal, respectively, and the AND output of the two signals is supplied to the load terminal of the counter 233.

The counter 233 takes in fixed data in which each bit input to the input terminals D1 to DN is "'1" when the logic of the signal inputted to the load terminal becomes "0"', and then the clock terminal CK Clock generation circuit 2 input to
The counting operation is performed in synchronization with the clock from 35. Since the value in which all bits are °l"' is taken as the initial value, r□,, rlJ,...
・The count is amplified in order. Each bit of this counter value is output from output terminals Q1 to QN.

The latch 237 captures and holds the counter value of the counter 233 that is input to the input terminals D1 to DN when the reception flag RFLG is input to the input terminal G, and the held counter value is transferred to the output terminals Q1 to DN. Output from QN.

The personal computer 241 reads the counter value held in the latch 237 and sets the transmission flag 5 based on this counter value.
The delay time from sending out FLG to receiving reception flag RFLG is calculated.

It also analyzes the calculated delay time and displays the delay time distribution and the like.

The packet switching network 251 shown in FIG. 2 is simulated using a personal computer or the like so as to cause a delay similar to that of an actual packet switching network.
It is configured to add a delay time simulating an actual packet switching network to G and send back a reception flag RFLG.

Next, the operation of the embodiment of the present invention described above will be explained.

FIG. 3 shows an outline of delay time measurement in one embodiment. In the same figure, A, B, etc. are transmission flags S F L
8", B", etc. indicate the reception timing of the reception flag RFLC corresponding to each transmission flag. Also, T indicates the reception timing of the reception flag RFLC; corresponding to each transmission flag. The delay time measuring device 211 described above measures the reception interval time of the reception flag RFLG such as XI+X2 shown in FIG. Specifically, the delay time of the first transmission flag 5FLG corresponding to A is the counter value X1 itself, and for B, (x, +xz-
'r), but for C, (x+ +χ2+ X 3 2
T ) are calculated as delay times, respectively.

FIG. 4 also shows the above-mentioned reception interval χ3. FIG. 5 shows the operation timing of the delay time measuring device 211 for determining X2, etc., and the operating procedure of the personal computer 241 for calculating the delay time based on the determined reception interval Xl+X2, etc.

Hereinafter, reference will be made to FIGS. 2 to 5.

When the delay time measuring device 211 is powered on, the R3FF 223 is set by the power-on reseller I signal XR3T output from the initial reset circuit (not shown), and as a result, the output logic of the inverter 227 becomes 0''. .This completes the preparation for delay time measurement.

In this state, when the first transmission flag 5FLG is output from the pattern generator 221 and sent to the packet switching network 251, the R3-FF 223 is reset at the same time as this sending operation. Therefore, the output logic of the inverter 223 and the output logic of the AND gate 231 become "1", and the counting operation by the counter 233 is started.

Reception flag R corresponding to this first transmission flag 5FLG
When the FLG is returned from the packet switching network 251,
In synchronization with this reception timing, the counter value X1 of the counter 233 is taken in by the watch 237. This held counter value is sent to the personal computer 241.

Further, when the reception flag RFLG is returned, the logic of the AND gate 231 is temporarily changed to 0' (by the pulse width of the reception flag RFLG), so that the initial value of the counter 233 is set again. Therefore, from now on, latch 237 outputs 1
Time interval X between the previous reception flag and the two previous reception flags
2+X3, etc. are held and output in sequence.

In the personal computer 241, initial values of variables m and n are set (both are set to "O") prior to the operation of calculating the delay operation (step 511).

Next, the personal computer 241 determines whether or not the counter value output from the latch 237 has been updated (step 51).
2) If no update has been made, a negative determination is made and the determination process in step 512 is repeated. When the reception flag RFLG is returned and the counter value held in the latch 237 is updated (affirmative judgment), the value obtained by adding the counter value output from the latch 237 to the value of the variable n is set as a new variable n. The variable n is updated as the value of (step 513). Therefore, when the counter value is first updated to Xl, the variable n is updated to X.

Next, the personal computer 241 calculates the delay time, t=nmXT
(T is the output cycle of the transmission flag 5FLG) (step 514).

Therefore, if the variable n is set to XI in step 513, the delay time j=x, -m (-〇)XT=x+
is calculated. The delay time t calculated in this manner is used for various statistical processing within the personal computer 241.

When the calculation of the delay time t in step 514 is completed,
Next, "1" is added to the value of variable m, and the variable m is updated using this addition result as a new value (after step 515L, the process returns to step 512 and repeats the process).

Therefore, next time the counter value held by the latch 237 is
When the variable n is updated to (x
l +xz), and in step 514, the delay time t is calculated as (x+ → -X2-T). Thereafter, an accurate delay time t is calculated in the same manner every time the reception flag RFLG is returned.

In this way, the reception flag RFL is set by the counter 233.
The reception interval of G is measured, and the corresponding transmission flag 5FL is determined from the value accumulated sequentially by the personal computer 241.
The delay time is calculated by subtracting O, T, 2T, etc., which are integral multiples of the G transmission interval.

Therefore, even if the output cycle T of the transmission flag 5FLG is small, the delay time can be calculated and the delay time can be measured accurately.

In the embodiment of the present invention described above, a case has been described in which the delay time due to the packet switching network 251 is measured. It can also be applied to the case of measuring delay time due to a network (for example, a TSDN switching network), and is not particularly limited by the type of network.

〔Effect of the invention〕

As described above, according to the present invention, after the first transmission flag is sent out from the transmission flag generation means, only the reception interval of each reception flag is measured by the reception interval measurement means, and the delay time is calculated based on this measurement result. This method is extremely useful in practice because it allows accurate measurement of delay time to be obtained.

[Brief explanation of drawings]

Fig. 1 is a principle block diagram of the network delay time measuring device of the present invention, Fig. 2 is a block diagram of an embodiment of the present invention, Fig. 3 is an explanatory diagram of delay time measurement of an embodiment, and Fig. 4 5 is an operational timing diagram of one embodiment, FIG. 5 is an explanatory diagram of operation of one embodiment, FIG. 6 is a configuration diagram of a conventional example, and FIG. 7 is an explanatory diagram of delay time measurement in a conventional example. In the figure, 111 is a network, 121 is a transmission flag generating means, 123 is a receiving interval measuring means, 125 is a delay time calculating means, 211 is a delay time measuring device, 221 is a pattern generator, and 223 is a set-reset flip-flop (RIF).
F), 225 227 229 is an inverter, 231 is an ant game, 233 is a counter, 235 is a clock generation circuit, 237 is a latch, 241 is a personal computer, 251
is a packet-switched network.

Claims (1)

[Claims] (1) A transmission flag generation means (121) that sends a transmission flag to the network (111) at a constant cycle; and starts operation when the first transmission flag is sent from the flag generation means (121); Reception interval measuring means (123) for measuring the reception interval of two successive reception flags, in which reception flags to which a delay is added according to the internal state of the network (111) are sequentially input corresponding to each of the transmission flags; and, by accumulating the reception interval measured by the reception interval measuring means (123) and subtracting a value obtained by multiplying the transmission interval of the transmission flag by an integer from this cumulative result, taking action after transmitting the transmission flag. delay time calculation means (125) for calculating the delay time until the reception flag is input;
), and a network delay time measuring device.