JPH06163612A - Manufacture and equipment for semiconductor device - Google Patents

Manufacture and equipment for semiconductor device

Info

Publication number
JPH06163612A
JPH06163612A JP31477592A JP31477592A JPH06163612A JP H06163612 A JPH06163612 A JP H06163612A JP 31477592 A JP31477592 A JP 31477592A JP 31477592 A JP31477592 A JP 31477592A JP H06163612 A JPH06163612 A JP H06163612A
Authority
JP
Japan
Prior art keywords
solder
semiconductor element
melting point
layer
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP31477592A
Other languages
Japanese (ja)
Inventor
Shunichi Abe
俊一 阿部
Michitaka Kimura
通孝 木村
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP31477592A priority Critical patent/JPH06163612A/en
Publication of JPH06163612A publication Critical patent/JPH06163612A/en
Pending legal-status Critical Current

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Abstract

PURPOSE:To make the thickness of molten solder even, for thermally treating a three-layer solder far jointing a semiconductor element with a supporter body. CONSTITUTION:A three-layer solder 3, wherein on bath sides of the first solder 3a made of a high melting point material, the second solder 3b made of the material whose melting point is lower than the first solder 3a is assigned, is sandwiched between a semiconductor element 1 and a supporter body 2 on which the element 1 is mounted, and then a pressure is applied on the three- layer solder 3 by a weight 5, so that, through heating and thermal treatment, only the second solder 3b is melted far jointing the semiconductor element 1 with the supporter body 2. With this, the thermal treatment period required for making the three-layer solder of higher melting paint can be shortened.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】この発明は、半導体素子とこれを
載置する支持体とを熱処理によって接合する際の半導体
装置の製造方法及び製造装置に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device and a manufacturing apparatus for bonding a semiconductor element and a support on which the semiconductor element is mounted by heat treatment.

【0002】[0002]

【従来の技術】図5は、例えば特願平3−4832号に
開示されたものと同様な従来の半導体装置の構造及び製
造過程を示す断面図である。
2. Description of the Related Art FIG. 5 is a sectional view showing the structure and manufacturing process of a conventional semiconductor device similar to that disclosed in, for example, Japanese Patent Application No. 3-4832.

【0003】図5において、1は半導体素子、2は半導
体素子を載置する支持体、例えばダイパット、3はこれ
ら半導体素子1とダイパット2とを接合するための三層
半田であって、例えば組成が95Pb−5Snで厚みが
50μmの高融点(305℃)半田(第1の半田)3a
及びこの高融点半田3aの上下両面にメッキ、又は蒸
着、スパッタ等により形成され、例えば組成がPb−6
3Snで厚みが10μmの共晶半田(第2の半田)3b
から成る。
In FIG. 5, reference numeral 1 is a semiconductor element, 2 is a support on which the semiconductor element is mounted, for example a die pad, and 3 is a three-layer solder for joining the semiconductor element 1 and the die pad 2. Is 95Pb-5Sn and has a thickness of 50 μm and high melting point (305 ° C.) solder (first solder) 3a
And the upper and lower surfaces of the high melting point solder 3a are formed by plating, vapor deposition, sputtering, or the like, and have a composition of Pb-6, for example.
Eutectic solder (second solder) 3b with 3Sn and a thickness of 10 μm
Consists of.

【0004】4は載置されたダイパット2を加熱するた
めのヒートブロックであり、但しこれは半導体装置の一
部ではない。
Reference numeral 4 is a heat block for heating the mounted die pad 2, but this is not a part of the semiconductor device.

【0005】このような半導体装置では、半導体素子1
とダイパット2とを三層半田3を介して重ね合せ、還元
性雰囲気中で共晶半田3bの融点183℃以上でかつ高
融点半田3aの融点305℃以下の温度、例えば200
℃にヒートブロック4で加熱し、共晶半田3bのみを溶
融させて半導体素子1とダイパット2を接合する。
In such a semiconductor device, the semiconductor element 1
And the die pad 2 are overlapped with each other via the three-layer solder 3, and the melting point of the eutectic solder 3b is 183 ° C. or higher and the melting point of the high melting point solder 3a is 305 ° C. or lower in a reducing atmosphere, for example, 200
The semiconductor block 1 and the die pad 2 are bonded by heating to ℃ by the heat block 4 to melt only the eutectic solder 3b.

【0006】その後、上述した温度200℃に保持する
ことによって共晶半田3bと高融点半田3aとの間でP
bとSnとが相互拡散を起こし、図6のPb−Sn系状
態図からわかるように、共晶半田3b中のSn濃度が約
18%以下、即ちPb濃度が約82%以上になると凝固
する。
Then, by maintaining the above-mentioned temperature of 200 ° C., P between the eutectic solder 3b and the high melting point solder 3a is obtained.
b and Sn cause mutual diffusion, and as can be seen from the Pb-Sn system phase diagram in FIG. 6, solidification occurs when the Sn concentration in the eutectic solder 3b is about 18% or less, that is, when the Pb concentration is about 82% or more. .

【0007】さらに、Sn濃度の低下に伴い、固相線温
度直下の温度に上昇させると、Snの拡散速度は更に加
速される。図6に示すように最終的には高融点半田3a
と共晶半田3bとの半田の組成が同じになり、最初の状
態の共晶半田3bよりも三層半田3の融点が高くなる。
Further, when the temperature is increased to a temperature just below the solidus temperature as the Sn concentration is lowered, the diffusion rate of Sn is further accelerated. Finally, as shown in FIG. 6, the high melting point solder 3a
And the eutectic solder 3b have the same solder composition, and the melting point of the three-layer solder 3 is higher than that of the eutectic solder 3b in the initial state.

【0008】このため、高融点半田3aが溶融されない
ことによる半導体素子1とダイパット2の間隔を一定に
保持するいわゆる間隔保持の効果に加えて、接合時の加
熱温度200℃より高い耐熱性を有する半導体装置を得
ることができる。
Therefore, in addition to the effect of keeping the distance between the semiconductor element 1 and the die pad 2 constant by not melting the high melting point solder 3a, it also has heat resistance higher than the heating temperature of 200 ° C. at the time of joining. A semiconductor device can be obtained.

【0009】半導体素子1とダイパット2を接合した
後、ヒートブロック4から半導体装置を取り上げ、半導
体素子1上の電極(図示しない)と外部リード(図示し
ない)とを金線(図示しない)で接続するワイヤボンド
工程、半導体装置を封止するモールド樹脂封止工程等の
諸工程を経て、半導体装置を完成させている。
After the semiconductor element 1 and the die pad 2 are joined, the semiconductor device is taken out from the heat block 4 and an electrode (not shown) on the semiconductor element 1 and an external lead (not shown) are connected by a gold wire (not shown). The semiconductor device is completed through various steps such as a wire bonding step and a molding resin sealing step of sealing the semiconductor device.

【0010】[0010]

【発明が解決しようとする課題】上述したような従来の
半導体装置では、三層半田3の共晶半田3bを溶融する
ための加熱時、及びその後PbとSnとが相互拡散を行
う熱処理中は、半導体素子1,ダイパット2間に何ら応
力は作用しなく、半導体素子1は溶融した共晶半田3b
上に浮かんだ状態となっている。
In the conventional semiconductor device as described above, during the heating for melting the eutectic solder 3b of the three-layer solder 3 and during the heat treatment in which Pb and Sn interdiffuse thereafter. , No stress acts between the semiconductor element 1 and the die pad 2, and the semiconductor element 1 melts the eutectic solder 3b.
It is floating above.

【0011】このため実際は、溶融した共晶半田3bは
流動し、半導体素子1側とダイパット2側の共晶半田3
bの厚みにバラツキが生じ、結果として、どちらか一方
の共晶半田3bの厚みが厚くなる。
Therefore, in reality, the melted eutectic solder 3b flows and the eutectic solder 3 on the semiconductor element 1 side and the die pad 2 side is melted.
Variation occurs in the thickness of b, and as a result, the thickness of either one of the eutectic solders 3b increases.

【0012】三層半田3の融点は、共晶半田3bと高融
点半田3aの厚みによって制御される三層半田全体のP
bとSnの組成比によって決定されるため、三層半田3
の融点は、共晶半田3bと高融点半田3aの厚みによっ
て制御されるといえる。
The melting point of the three-layer solder 3 is controlled by the thicknesses of the eutectic solder 3b and the high melting point solder 3a.
Since it is determined by the composition ratio of b and Sn, three-layer solder 3
It can be said that the melting point of is controlled by the thickness of the eutectic solder 3b and the high melting point solder 3a.

【0013】このため、三層半田3の高融点化の際に共
晶半田3bの厚みが厚く、しかも厚みにバラツキが生じ
ていると、必要な熱処理時間も図7の実測値と良く相関
がとれたシミュレーション結果からわかるように、バラ
ツクのみならず、長時間の熱処理が必要であるという問
題点があった。
Therefore, if the thickness of the eutectic solder 3b is large when the melting point of the three-layer solder 3 is increased and the thickness of the eutectic solder 3b varies, the required heat treatment time also correlates well with the measured value in FIG. As can be seen from the simulation results obtained, there was a problem that not only the variation but also the heat treatment for a long time was necessary.

【0014】因に、三層半田3に設けられている共晶半
田3bの厚みが10μmであれば、加熱、溶融後の共晶
半田3bの半導体素子1側とダイパット2側の厚みの差
が10μm程度生じ、例えば、半導体素子側共晶半田厚
5μmに対し、ダイパット側共晶半田厚15μmであっ
た。このため、熱処理時間は共晶半田厚の厚い側に制御
され、本来予想していた熱処理時間よりも数時間余分に
必要となっていた。(図7参照)
Incidentally, if the thickness of the eutectic solder 3b provided on the three-layer solder 3 is 10 μm, there is a difference in thickness between the semiconductor element 1 side and the die pad 2 side of the eutectic solder 3b after heating and melting. The thickness was about 10 μm. For example, the eutectic solder thickness on the semiconductor element side was 5 μm, while the eutectic solder thickness on the die pad side was 15 μm. For this reason, the heat treatment time is controlled to the thicker side of the eutectic solder, which requires several hours more than the originally expected heat treatment time. (See Figure 7)

【0015】また、共晶半田3bの厚さを例えば10μ
mとしてPbとSnとの相互拡散を行う熱処理用の炉の
温度を或る温度に設定していると、上述の如く共晶半田
3bの厚みの差にバラツキが生じた場合には15μmの
ダイパット側共晶半田は、その後のワイヤボンド工程等
における温度が上記炉内設定温度より高いと、熱処理段
階で熱処理時間不足により十分に凝固していないので、
溶融して半導体素子1がダイパット側共晶半田上に浮か
んでワイヤボンディング出来なくなる等の問題点があっ
た。
The thickness of the eutectic solder 3b is, for example, 10 μm.
When the temperature of the furnace for heat treatment that performs mutual diffusion of Pb and Sn is set to a certain temperature as m, when the difference in the thickness of the eutectic solder 3b is varied as described above, the die pad of 15 μm is used. The side eutectic solder is not sufficiently solidified due to insufficient heat treatment time in the heat treatment stage when the temperature in the subsequent wire bonding step or the like is higher than the set temperature in the furnace,
There is a problem that the semiconductor element 1 is melted and floats on the eutectic solder on the die pad side, and wire bonding cannot be performed.

【0016】この発明は、このような問題点を解決する
ためになされたもので、三層半田を熱処理する際の溶融
半田の厚さを薄く均一にすることにより、三層半田の高
融点化に必要な熱処理時間を短縮することができると共
に後工程での処理にも支障を来たすことのない半導体装
置の製造方法及び製造装置を提供することを目的として
いる。
The present invention has been made in order to solve the above problems, and increases the melting point of the three-layer solder by making the thickness of the molten solder when heat treating the three-layer solder thin and uniform. It is an object of the present invention to provide a method and an apparatus for manufacturing a semiconductor device, which can shorten the heat treatment time required for the above and do not hinder the processing in the subsequent steps.

【0017】[0017]

【課題を解決するための手段】この発明の半導体装置の
製造方法は、高融点材料からなる第1の半田の両面に、
該第1の半田よりも低融点の材料からなる第2の半田が
配設された三層半田を、半導体素子と該半導体素子を載
置する支持体の間に挟み、前記三層半田に圧力を付加
し、加熱及び熱処理によって前記第2の半田のみを溶融
させて前記半導体素子と支持体を接合させるようにした
ものである。
According to the method of manufacturing a semiconductor device of the present invention, the first solder made of a high melting point material is formed on both surfaces of the first solder.
The three-layer solder, in which the second solder made of a material having a melting point lower than that of the first solder is arranged, is sandwiched between the semiconductor element and the support on which the semiconductor element is mounted, and the three-layer solder is pressed. Is added, and only the second solder is melted by heating and heat treatment to bond the semiconductor element and the support.

【0018】また、この発明の半導体装置の製造装置
は、半導体素子と該半導体素子を載置する支持体との間
に挟まれた三層半田に圧力を付加する加圧手段を備えた
ものである。
Further, the semiconductor device manufacturing apparatus of the present invention comprises a pressurizing means for applying pressure to the three-layer solder sandwiched between the semiconductor element and the support on which the semiconductor element is mounted. is there.

【0019】[0019]

【作用】この発明の半導体装置の製造方法においては、
半導体素子と支持体の間に挟まれた三層半田を加熱、熱
処理する際に、三層半田に圧力を付加しているので、溶
融された半田の厚さを薄く均一にすることができ、三層
半田の高融点化に必要な熱処理時間を短縮することがで
き、しかも後工程も支障なく行うことができる。
According to the method of manufacturing the semiconductor device of the present invention,
Since the pressure is applied to the three-layer solder when heating and heat-treating the three-layer solder sandwiched between the semiconductor element and the support, the thickness of the melted solder can be made thin and uniform, The heat treatment time required for raising the melting point of the three-layer solder can be shortened, and the subsequent steps can be performed without any trouble.

【0020】この発明の半導体装置の製造装置において
は、加圧手段で加熱熱処理の際に三層半田に圧力を加え
る。これにより、簡単な構成で三層半田の高融点化に必
要な熱処理時間を短縮することができ、しかも後工程も
支障なく行うことができる。
In the semiconductor device manufacturing apparatus of the present invention, the pressure is applied to the three-layer solder by the pressing means during the heat treatment. This makes it possible to shorten the heat treatment time required for raising the melting point of the three-layer solder with a simple structure, and to perform the post-process without any trouble.

【0021】[0021]

【実施例】【Example】

実施例1.以下、この発明の一実施例について説明す
る。図1は、この発明の一実施例を示す断面図である。
Example 1. An embodiment of the present invention will be described below. FIG. 1 is a sectional view showing an embodiment of the present invention.

【0022】図1において、1,2,3,3a,3b,
4は、従来例と同じ半導体素子、ダイパット、三層半
田、高融点半田(第1の半田)、共晶半田(第2の半
田)、ヒートブロックである。5は半導体素子1上に置
かれた加重用のおもりである。
In FIG. 1, 1, 2, 3, 3a, 3b,
Reference numeral 4 is the same semiconductor element, die pad, three-layer solder, high melting point solder (first solder), eutectic solder (second solder), and heat block as in the conventional example. Reference numeral 5 is a weighting weight placed on the semiconductor element 1.

【0023】このように半導体素子1とダイパット2と
の間の三層半田に圧力を与える、つまり加重して従来と
同様な熱処理を行うことにより、半導体素子1とダイパ
ット2を接合するに過剰な共晶半田3bは側面に排出さ
れ、全体の共晶半田厚が減少し、この結果加熱、溶融後
の共晶半田3bの半導体素子1側とダイパット2側の厚
みの差は約2μm以内に収束した。例えば、実験による
と半導体素子側共晶半田厚6μmに対し、ダイパット側
共晶半田厚4μmであった。
As described above, the three-layer solder between the semiconductor element 1 and the die pad 2 is subjected to pressure, that is, weighted and subjected to the same heat treatment as in the conventional case, so that the semiconductor element 1 and the die pad 2 are excessively bonded. The eutectic solder 3b is discharged to the side surface, and the entire eutectic solder thickness is reduced. As a result, the difference in thickness between the semiconductor element 1 side and the die pad 2 side of the eutectic solder 3b after heating and melting converges within about 2 μm. did. For example, according to experiments, the eutectic solder thickness on the semiconductor element side was 6 μm, while the eutectic solder thickness on the die pad side was 4 μm.

【0024】このように本実施例では共晶半田厚を減少
させ、厚みをほぼ均一にすることによって、熱処理時間
を数時間短縮することができる。また、共晶半田厚をほ
ぼ均一に出来るので、従来のごとく熱処理段階で熱処理
時間不足により炉内設定温度に達しないで十分に凝固さ
れないということがなくなり、従ってその後のワイヤボ
ンド工程においても溶融して半導体素子1がその溶融し
た共晶半田上に浮かんでワイヤボンディングが出来なく
なる等の不都合もなくなる。
As described above, in the present embodiment, the heat treatment time can be shortened by several hours by reducing the eutectic solder thickness and making the thickness almost uniform. In addition, since the eutectic solder thickness can be made almost uniform, it does not happen that the solidification is not sufficiently solidified by not reaching the set temperature in the furnace due to insufficient heat treatment time in the conventional heat treatment step, so that it melts in the subsequent wire bonding process. As a result, the problem that the semiconductor element 1 floats on the melted eutectic solder and wire bonding becomes impossible is eliminated.

【0025】実施例2.図2はこの発明の他の実施例を
示す断面図である。実施例1では、加圧手段として、半
導体素子1上に直接おもりを置いたが、図2に示す様な
加重機能を持った治具6を使用してもよい。
Example 2. FIG. 2 is a sectional view showing another embodiment of the present invention. Although the weight is directly placed on the semiconductor element 1 as the pressing means in the first embodiment, a jig 6 having a weighting function as shown in FIG. 2 may be used.

【0026】図2において、6aは治具6の下面に取り
付けられた半導体素子1とダイパット2との間を加重す
るためのバネ、6bはバネ6aに取り付けられ、半導体
素子1表面に接融して加重を均一化させるための平板で
ある。
In FIG. 2, 6a is a spring for weighting between the semiconductor element 1 and the die pad 2 attached to the lower surface of the jig 6, and 6b is attached to the spring 6a and melts on the surface of the semiconductor element 1. It is a flat plate for uniformizing the weight by applying.

【0027】このように本実施例においても、治具6に
よって加重された半導体装置を加熱、熱処理することに
よって、実施例1と同様な効果を得ることができる。
As described above, also in this embodiment, the same effect as that of the first embodiment can be obtained by heating and heat treating the semiconductor device weighted by the jig 6.

【0028】実施例3.図3は、この発明の他の実施例
を示す断面図である。図3において、7は雰囲気炉本
体、8は炉から噴出される雰囲気ガス、9は加重用シリ
コンゴム、10はベルトコンベアである。ベルトコンベ
ア10上に半導体装置をある決められた間隔に並べ炉内
へ送りこむ。
Example 3. FIG. 3 is a sectional view showing another embodiment of the present invention. In FIG. 3, 7 is an atmosphere furnace main body, 8 is an atmosphere gas ejected from the furnace, 9 is a silicon rubber for weighting, and 10 is a belt conveyor. The semiconductor devices are arranged on the belt conveyor 10 at a predetermined interval and fed into the furnace.

【0029】炉内では半導体装置に各々に対応するべ
く、炉内ベルトコンベア10上にシリコンゴム9等で出
来た凸状の加重用物体が設けられており、それによって
半導体素子1とダイパット2との間を加重することがで
きる。又、その加重程度は凸状の形状を変更することに
よっても可能である。
In the furnace, a convex weighting object made of silicon rubber 9 or the like is provided on the in-furnace belt conveyor 10 so as to correspond to each semiconductor device, whereby the semiconductor element 1 and the die pad 2 are connected. You can weight between. Further, the weighting degree can be changed by changing the convex shape.

【0030】このように本実施例でも、半導体装置製造
に必要な熱処理時間を数時間短縮することができると共
に、後工程に何等支障をきたすことなく熱処理を流れ作
業で効率よく行うことができる。
As described above, also in this embodiment, the heat treatment time required for manufacturing the semiconductor device can be shortened by several hours, and the heat treatment can be efficiently carried out by the flow work without any trouble in the subsequent steps.

【0031】実施例4.図4はこの発明の他の実施例を
示す断面図である。実施例3の半導体装置製造装置に代
り、図4のような炉11を用いてもよい。図4におい
て、12は炉内加圧用ガス注入バルブである。炉11内
にガスを注入することによって炉内圧力を上げ、それに
よって半導体素子1とダイパット2との間に加重するこ
とが出来る。
Example 4. FIG. 4 is a sectional view showing another embodiment of the present invention. A furnace 11 as shown in FIG. 4 may be used instead of the semiconductor device manufacturing apparatus of the third embodiment. In FIG. 4, reference numeral 12 is a gas injection valve for pressurizing the furnace. By injecting the gas into the furnace 11, the pressure inside the furnace can be increased, and thereby, the weight can be applied between the semiconductor element 1 and the die pad 2.

【0032】このように本実施例においても、上記各実
施例と同様に、熱処理時間を短縮することができると共
に、後工程に何等支障をきたすことがない。
As described above, in this embodiment as well, the heat treatment time can be shortened and there is no hindrance to the subsequent steps, as in the above embodiments.

【0033】[0033]

【発明の効果】以上のように、この発明の半導体装置の
製造方法によれば、高融点材料からなる第1の半田の両
面に、該第1の半田よりも低融点の材料からなる第2の
半田が配設された三層半田を、半導体素子と該半導体素
子を載置する支持体の間に挟み、前記三層半田に圧力を
付加し、加熱及び熱処理によって前記第2の半田のみを
溶融させて前記半導体素子と支持体を接合させるように
したので、熱処理する際の溶融半田の厚さを薄く均一に
でき、三層半田の高融点化に必要な熱処理時間を短縮す
ることができると共に、後工程に何等支障をきたすこと
がないという効果がある。
As described above, according to the method of manufacturing a semiconductor device of the present invention, the second solder made of a material having a melting point lower than that of the first solder is formed on both surfaces of the first solder made of a high melting point material. Sandwiching the three-layer solder having the above-mentioned solder disposed between the semiconductor element and the support on which the semiconductor element is mounted, applying pressure to the three-layer solder, and heating and heat treating only the second solder. Since the semiconductor element and the support are melted and joined together, the thickness of the molten solder during the heat treatment can be made thin and uniform, and the heat treatment time required for increasing the melting point of the three-layer solder can be shortened. At the same time, there is an effect that the subsequent process is not hindered.

【0034】また、この発明の半導体装置の製造装置に
よれば、半導体素子とこれを載置する支持体の間に挟ま
れた三層半田に圧力を付加する加圧手段を備えたので、
簡単な構成で、後工程に何等支障をきたすことなく三層
半田の高融点化に必要な熱処理時間を短縮することがで
きるという効果がある。
Further, according to the semiconductor device manufacturing apparatus of the present invention, since the semiconductor element and the support on which the semiconductor element is mounted are provided with the pressurizing means for applying pressure to the three-layer solder,
With a simple configuration, there is an effect that the heat treatment time required for raising the melting point of the three-layer solder can be shortened without causing any trouble in the subsequent steps.

【図面の簡単な説明】[Brief description of drawings]

【図1】この発明の一実施例を示す断面図である。FIG. 1 is a sectional view showing an embodiment of the present invention.

【図2】この発明の他の実施例を示す断面図である。FIG. 2 is a sectional view showing another embodiment of the present invention.

【図3】この発明の他の実施例を示す断面図である。FIG. 3 is a sectional view showing another embodiment of the present invention.

【図4】この発明の他の実施例を示す断面図である。FIG. 4 is a sectional view showing another embodiment of the present invention.

【図5】従来の半導体装置の製造装置を示す断面図であ
る。
FIG. 5 is a cross-sectional view showing a conventional semiconductor device manufacturing apparatus.

【図6】三層半田の凝固過程を説明するための状態図で
ある。
FIG. 6 is a state diagram for explaining a solidification process of three-layer solder.

【図7】共晶半田の厚みと熱処理時間の関係のシミュレ
ーション結果を示す図である。
FIG. 7 is a diagram showing a simulation result of a relationship between a thickness of eutectic solder and a heat treatment time.

【符号の説明】[Explanation of symbols]

1 半導体素子 2 ダイパット 3 三層半田 3a 高融点半田(第1の半田) 3b 共晶半田(第2の半田) 4 ヒートブロック 5 加重用のおもり 6 治具 6a バネ 6b 平板 7 炉 9 加重用シリコンゴム 11 炉 12 炉内加圧用ガス注入バルブ 1 semiconductor element 2 die pad 3 three layer solder 3a high melting point solder (first solder) 3b eutectic solder (second solder) 4 heat block 5 weight for weight 6 jig 6a spring 6b flat plate 7 furnace 9 weight silicon Rubber 11 Furnace 12 Gas injection valve for pressurizing inside the furnace

─────────────────────────────────────────────────────
─────────────────────────────────────────────────── ───

【手続補正書】[Procedure amendment]

【提出日】平成5年7月8日[Submission date] July 8, 1993

【手続補正1】[Procedure Amendment 1]

【補正対象書類名】明細書[Document name to be amended] Statement

【補正対象項目名】0024[Name of item to be corrected] 0024

【補正方法】変更[Correction method] Change

【補正内容】[Correction content]

【0024】このように本実施例では共晶半田厚を減少
させ、厚みをほぼ均一にすることによって、熱処理時間
を数時間短縮することができる。また、共晶半田厚をほ
ぼ均一に出来るので、従来のごとく熱処理段階で熱処理
時間不足により三層半田全体の融点上昇が十分でない
いうことがなくなり、従ってその後のワイヤボンド工程
においても溶融して半導体素子1がその溶融した共晶半
田上に浮かんでワイヤボンディングが出来なくなる等の
不都合もなくなる。
As described above, in the present embodiment, the heat treatment time can be shortened by several hours by reducing the eutectic solder thickness and making the thickness almost uniform. Further, since the eutectic solder thickness can be made substantially uniform, it is possible to prevent the melting point of the entire three-layer solder from being insufficiently increased due to insufficient heat treatment time in the heat treatment step as in the conventional case, and therefore in the subsequent wire bonding step. And the semiconductor element 1 floats on the melted eutectic solder and wire bonding is no longer possible.

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】 高融点材料からなる第1の半田の両面
に、該第1の半田よりも低融点の材料からなる第2の半
田が配設された三層半田を、半導体素子と該半導体素子
を載置する支持体の間に挟み、前記三層半田に圧力を付
加し、 加熱及び熱処理によって前記第2の半田のみを溶融させ
て前記半導体素子と支持体を接合させるようにしたこと
を特徴とする半導体装置の製造方法。
1. A three-layer solder, in which a second solder made of a material having a melting point lower than that of the first solder is provided on both surfaces of a first solder made of a high melting point material, a semiconductor element and the semiconductor The device is sandwiched between the supports on which the device is placed, pressure is applied to the three-layer solder, and only the second solder is melted by heating and heat treatment so that the semiconductor device and the support are joined. A method for manufacturing a characteristic semiconductor device.
【請求項2】 半導体素子と該半導体素子を載置する支
持体との間に挟まれた三層半田を加熱及び熱処理して前
記半導体素子と支持体とを接合させる半導体装置の製造
装置において、 前記三層半田に圧力を付加する加圧手段を備えたことを
特徴とする半導体装置の製造装置。
2. An apparatus for manufacturing a semiconductor device, wherein a three-layer solder sandwiched between a semiconductor element and a support on which the semiconductor element is mounted is heated and heat-treated to bond the semiconductor element and the support. An apparatus for manufacturing a semiconductor device, comprising pressurizing means for applying pressure to the three-layer solder.
JP31477592A 1992-11-25 1992-11-25 Manufacture and equipment for semiconductor device Pending JPH06163612A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP31477592A JPH06163612A (en) 1992-11-25 1992-11-25 Manufacture and equipment for semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP31477592A JPH06163612A (en) 1992-11-25 1992-11-25 Manufacture and equipment for semiconductor device

Publications (1)

Publication Number Publication Date
JPH06163612A true JPH06163612A (en) 1994-06-10

Family

ID=18057445

Family Applications (1)

Application Number Title Priority Date Filing Date
JP31477592A Pending JPH06163612A (en) 1992-11-25 1992-11-25 Manufacture and equipment for semiconductor device

Country Status (1)

Country Link
JP (1) JPH06163612A (en)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2007074889A1 (en) 2005-12-28 2007-07-05 Kabushiki Kaisha Toyota Jidoshokki Soldering method, semiconductor module manufacturing method and soldering apparatus
WO2007077688A1 (en) 2005-12-28 2007-07-12 Kabushiki Kaisha Toyota Jidoshokki Soldering method and semiconductor module manufacturing method
WO2007077877A1 (en) * 2005-12-28 2007-07-12 Kabushiki Kaisha Toyota Jidoshokki Soldering method, soldering apparatus and method for manufacturing semiconductor device
JP2008159878A (en) * 2006-12-25 2008-07-10 Nippon Mektron Ltd Flip-chip interconnection method by no-flow underfill equipped with height control function
US9385103B2 (en) 2013-04-17 2016-07-05 Fuji Electric Co., Ltd. Semiconductor device manufacturing method
JPWO2016190205A1 (en) * 2015-05-26 2017-10-05 三菱電機株式会社 Semiconductor device, method for manufacturing semiconductor device, and bonding material

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2007074889A1 (en) 2005-12-28 2007-07-05 Kabushiki Kaisha Toyota Jidoshokki Soldering method, semiconductor module manufacturing method and soldering apparatus
WO2007077688A1 (en) 2005-12-28 2007-07-12 Kabushiki Kaisha Toyota Jidoshokki Soldering method and semiconductor module manufacturing method
WO2007077877A1 (en) * 2005-12-28 2007-07-12 Kabushiki Kaisha Toyota Jidoshokki Soldering method, soldering apparatus and method for manufacturing semiconductor device
JP2008159878A (en) * 2006-12-25 2008-07-10 Nippon Mektron Ltd Flip-chip interconnection method by no-flow underfill equipped with height control function
US9385103B2 (en) 2013-04-17 2016-07-05 Fuji Electric Co., Ltd. Semiconductor device manufacturing method
JPWO2016190205A1 (en) * 2015-05-26 2017-10-05 三菱電機株式会社 Semiconductor device, method for manufacturing semiconductor device, and bonding material

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