JP2770040B2 - Bump forming method and semiconductor element connecting method - Google Patents
Bump forming method and semiconductor element connecting methodInfo
- Publication number
- JP2770040B2 JP2770040B2 JP1027299A JP2729989A JP2770040B2 JP 2770040 B2 JP2770040 B2 JP 2770040B2 JP 1027299 A JP1027299 A JP 1027299A JP 2729989 A JP2729989 A JP 2729989A JP 2770040 B2 JP2770040 B2 JP 2770040B2
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor element
- bump
- superelastic
- electrode
- connection
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
Landscapes
- Wire Bonding (AREA)
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、半導体チップに代表される半導体素子と実
装基板の接続方法に関するものである。The present invention relates to a method for connecting a semiconductor element represented by a semiconductor chip to a mounting board.
〔従来の技術〕 従来の半導体素子のバンプによる接続方法の概略構造
を第２図に示す。バンプとは半導体または実装基板の電
極上に設けられた金属突起物のことであり、この方法に
よる接合ではボンディングワイヤーは不要である。図中
の１は半導体素子,2は実装基板,3は半導体素子または実
装基板に構成されたはんだバンプ,4は半導体素子１と実
装基板２の電極であり,A−Ａ′は半導体素子の中心を示
している。[Prior Art] FIG. 2 shows a schematic structure of a conventional method of connecting semiconductor elements by bumps. A bump is a metal protrusion provided on an electrode of a semiconductor or a mounting substrate, and a bonding wire is not required for bonding by this method. In the figure, reference numeral 1 denotes a semiconductor element, 2 denotes a mounting board, 3 denotes a solder bump formed on the semiconductor element or the mounting board, 4 denotes electrodes of the semiconductor element 1 and the mounting board 2, and AA ′ denotes a center of the semiconductor element. Is shown.
接続は、はんだバンプ３を加熱溶融することにより行
われ、一括接続であるため、ワイヤー接続方法に比べて
作業性に優れ、またワイヤ接続及びTAB（Tape Automate
d Bonding）方法の如く、電極配置がICチップの周辺に
限定されるものと比較して、大幅に接続端子数を増やす
ことができるという特徴を持っている。The connection is performed by heating and melting the solder bumps 3 and is a batch connection, so that the workability is superior to the wire connection method, and the wire connection and TAB (Tape Automate) are performed.
It has the feature that the number of connection terminals can be greatly increased as compared with the case where the electrode arrangement is limited to the periphery of the IC chip as in the d bonding method.
しかしながら、この方法では、温度変化により、第３
図に示すような半導体素子１と実装基板２との熱膨張差
による寸法ずれＢが起こり、はんだバンプ３にせん断歪
が生じ、接続信頼性が低下する。せん断歪は、はんだバ
ンプ３と半導体素子１の中心との距離の増加とともに増
大するため、はんだバンプ３の許容しうるせん断歪量か
らはんだバンプ３を配置できる領域が制限され多端子化
ならびに大面積の半導体素子への適用が困難であった。
このはんだバンプのせん断歪を低減させる手段として、
半導体素子と熱膨張係数の近い配線基板を用いる方法が
考えられるが、配線基板材料が限定されてしまうため、
熱膨張係数の異なる材質の半導体素子を混載することが
できない等の欠点がある。一方はんだバンプの高さを高
くしてせん断歪を低減させる手段が提案されている。こ
の手段としては、ポリイミドフィルムで支持したはんだ
バンプを重ねることにより、多段バンプを形成する方法
（特開昭62−293730号公報）があるが、この方法では、
はんだバンプを積み重ねるため、必要部材の増加、製造
工数増加にともなう価格上昇という問題がある。However, with this method, the third
As shown in the figure, a dimensional deviation B occurs due to a difference in thermal expansion between the semiconductor element 1 and the mounting substrate 2, and shear distortion occurs in the solder bumps 3, thereby reducing connection reliability. Since the shear strain increases as the distance between the solder bump 3 and the center of the semiconductor element 1 increases, the area where the solder bump 3 can be arranged is limited due to the allowable shear strain of the solder bump 3, so that the number of terminals and the area are increased. Is difficult to apply to semiconductor devices.
As means for reducing the shear strain of this solder bump,
A method using a wiring board having a thermal expansion coefficient close to that of the semiconductor element is conceivable, but since the wiring board material is limited,
There are drawbacks such as the inability to mix semiconductor elements of materials having different coefficients of thermal expansion. On the other hand, means for increasing the height of the solder bump to reduce shear strain has been proposed. As this means, there is a method of forming a multi-stage bump by laminating solder bumps supported by a polyimide film (Japanese Patent Application Laid-Open No. 62-293730).
Since the solder bumps are stacked, there is a problem that the number of required members increases and the number of manufacturing steps increases, thereby increasing the price.
また、第４図は、はんだバンプを圧力で接触させて電
気的接続を得る半導体素子接続構造である。第４図にお
いて、半導体素子１と実装基板２のそれぞれの電極４上
にははんだバンプ３が形成されている。このはんだバン
プ３には樹脂５の硬化時の収縮力により圧力が加わり、
はんだバンプ３同士が機械的に接触し電気的接続が得ら
れる。FIG. 4 shows a semiconductor element connection structure in which solder bumps are brought into contact with each other under pressure to obtain electrical connection. In FIG. 4, solder bumps 3 are formed on respective electrodes 4 of the semiconductor element 1 and the mounting substrate 2. Pressure is applied to the solder bumps 3 by the shrinkage force of the resin 5 during curing,
The solder bumps 3 are brought into mechanical contact with each other, and electrical connection is obtained.
しかしながら、この接続構造でははんだバンプ３の高
さがばらつくと電気的接続が得られない箇所が生ずる。
また、樹脂５の膨張係数は金属バンプに比べて大きいた
め、温度変化が生じると圧力が弱まり、はんだバンプ３
の接触が不安定になるので、接続信頼性に欠けるという
問題があった。However, in this connection structure, if the height of the solder bumps 3 varies, there are places where electrical connection cannot be obtained.
Further, since the expansion coefficient of the resin 5 is larger than that of the metal bump, the pressure is weakened when the temperature changes, and the solder bump 3
However, there has been a problem that the connection reliability is poor because the contact of the wire becomes unstable.
本発明では、上記の如き熱応力による歪，バンプ高さ
のばらつき及び樹脂の熱膨張による圧力変動に対して信
頼性が高く、容易に微細な接続が可能なバンプ接続方法
を提供することを目的とする。An object of the present invention is to provide a bump connection method which is highly reliable against the above-described distortion due to thermal stress, variation in bump height, and pressure fluctuation due to thermal expansion of resin, and which can easily perform fine connection. And
本発明は、半導体素子上にバンプを形成する手段とし
て、溶融した超弾性合金に半導体素子を浸漬させること
により、半導体素子の電極上に選択的に超弾性バンプを
形成することを特徴とするバンプ形成方法、及び前述の
方法により形成した超弾性バンプを介して、加熱溶融法
により実装基板との電気的接続を得ることを特徴とする
半導体素子接続方法である。The present invention provides a method for forming a bump on a semiconductor element by selectively immersing the semiconductor element in a molten superelastic alloy to form a superelastic bump on an electrode of the semiconductor element. A method of connecting a semiconductor element, wherein a method of forming a semiconductor element and an electrical connection with a mounting substrate are obtained by a heating and melting method via a superelastic bump formed by the method described above.
指定の位置に電極を設けた半導体素子を溶融した超弾
性合金中に浸漬すると、電極の大きさにほぼ等しい面積
の超弾性バンプが形成される。これを必要に応じて加熱
炉に入れバンプ形状を半球状に整形し、実装基板の電極
との接続を行う。このときバンプ高さには多少のバラツ
キが生ずる場合もあるが、超弾性合金を用いているた
め、高さの高いものは超弾性の弾性域内で変形され電気
的な接続が維持される。また使用時の温度変化によるせ
ん断変形に対しても超弾性の弾性変形で補うことができ
る。When a semiconductor element provided with an electrode at a specified position is immersed in a melted superelastic alloy, a superelastic bump having an area substantially equal to the size of the electrode is formed. This is placed in a heating furnace as necessary, the bump shape is shaped into a hemisphere, and connection with the electrodes of the mounting board is performed. At this time, the bump height may vary slightly, but since the super-elastic alloy is used, the high one is deformed in the super-elastic elastic region and the electrical connection is maintained. In addition, shear deformation due to temperature change during use can be compensated for by superelastic elastic deformation.
電極のついた半導体素子ごと溶融した超弾性合金に浸
漬する際に溶融した超弾性合金が不必要な箇所に付着し
ないためと半導体素子の耐熱の観点から必要に応じてマ
スキングを施すことが望ましい。It is desirable to perform masking as necessary from the viewpoint of heat resistance of the semiconductor element because the molten superelastic alloy does not adhere to unnecessary portions when the semiconductor element with the electrodes is immersed in the molten superelastic alloy.
また、半導体素子への熱によるダメージを少なくする
ため、本発明における超弾性合金としては低融点のもの
が適している。本発明で用いる低融点の超弾性合金とし
ては、In−21〜22at％Tl,In−12〜13at％Pb,In−30〜36
at％Pb,In−４〜6at％Cd等のように、融点が300℃以下
の熱弾性型形状記憶合金で、超弾性硬化を有する合金が
望ましい。Further, in order to reduce heat damage to the semiconductor element, a superelastic alloy having a low melting point is suitable for the present invention. As the low melting point superelastic alloy used in the present invention, In-21 to 22 at% Tl, In-12 to 13 at% Pb, In-30 to 36
A thermoelastic shape memory alloy having a melting point of 300 ° C. or less, such as at% Pb, In-4 to 6at% Cd, and an alloy having superelastic hardening is desirable.
また、このような方法で形成した半導体素子接続用バ
ンプは、形成後加熱溶融炉に入れて整形してもよい。Further, the bump for connecting a semiconductor element formed by such a method may be put into a heating and melting furnace after the formation to be shaped.
このように、半導体素子上にバンプを形成する手段と
して、溶融した超弾性合金に半導体素子を浸漬すること
により、半導体素子上の電極位置に容易にバンプを形成
することができ、しかも超弾性効果を有するため、バン
プの高さバラツキ、熱歪に対しても弾性変形で補うこと
ができ信頼性の高い接続が実現できる。As described above, as a means for forming a bump on a semiconductor element, by immersing the semiconductor element in a molten superelastic alloy, the bump can be easily formed at the electrode position on the semiconductor element, and furthermore, the superelastic effect can be obtained. Therefore, unevenness in bump height and thermal strain can be compensated for by elastic deformation, and a highly reliable connection can be realized.
次に、本発明を図面に示す実施例に基づいて説明す
る。Next, the present invention will be described based on an embodiment shown in the drawings.
第１図は、接続バンプが構成された半導体チップの断
面で、図中の１は半導体素子、２は実装基板、４は金属
電極、６は低融点超弾性バンプを示す。FIG. 1 is a cross section of a semiconductor chip on which connection bumps are formed. In the figure, reference numeral 1 denotes a semiconductor element, 2 denotes a mounting board, 4 denotes a metal electrode, and 6 denotes a low melting point superelastic bump.
本発明の接続バンプ構成法を説明する。 The connection bump forming method of the present invention will be described.
金属電極（Al電極）の形成された半導体素子１を、In
−Al合金を溶融した溶液７に浸漬する。In−Tl合金６′
は半導体素子の金属電極上にだけ選択的に形成される。
次にこの半導体素子をリフロー炉に入れ、In−Tl合金の
形状を整えバンプ６とする。このようにしてできたバン
プつき半導体素子を実装基板上の所定の位置に置き、リ
フロー炉で加熱、接合する。なお、In−Tl合金の組成
は、室温以上の温度で超弾性を示すIn−22.0at％Tlを選
んでいる。このような構造にすることにより本超弾性バ
ンプは1.5％の弾性変形を有し、０〜150℃の温度サイク
ルを1000回繰り返しても電気的接触は維持された。The semiconductor element 1 on which the metal electrode (Al electrode) is formed is
-Dipping the Al alloy in the molten solution 7; In-Tl alloy 6 '
Is selectively formed only on the metal electrode of the semiconductor element.
Next, this semiconductor element is put into a reflow furnace, and the shape of the In-Tl alloy is adjusted to form a bump 6. The semiconductor device with bumps thus formed is placed at a predetermined position on a mounting board, and heated and joined in a reflow furnace. The composition of the In-Tl alloy is selected to be In-22.0 at% Tl which exhibits superelasticity at a temperature higher than room temperature. By adopting such a structure, the present superelastic bump has an elastic deformation of 1.5%, and the electrical contact is maintained even when the temperature cycle of 0 to 150 ° C. is repeated 1,000 times.
以上の如く本発明は、融点の低い超弾性合金の溶融液
に半導体素子を浸漬し、半導体素子の電極上に選択的に
超弾性バンプを形成したことを特徴としている。このよ
うなバンプの形成方法を用いることにより、簡単かつ確
実に電極位置に超弾性バンプが形成でき、また超弾性の
効果により、温度変化で生じる熱応力による歪やバンプ
高さのバラツキに対して信頼性の高い半導体素子の接合
が可能となった。As described above, the present invention is characterized in that a semiconductor element is immersed in a melt of a superelastic alloy having a low melting point, and a superelastic bump is selectively formed on an electrode of the semiconductor element. By using such a bump forming method, a superelastic bump can be easily and reliably formed at an electrode position, and due to the effect of superelasticity, it is possible to prevent distortion due to thermal stress caused by a temperature change and variation in bump height. It has become possible to join highly reliable semiconductor elements.
第１図（ａ）〜（ｅ）は、低融点の超弾性合金の溶融液
に半導体素子を浸漬し、半導体素子の電極上に選択的に
超弾性バンプを形成する方法の概略図である。第２図〜
第４図は、従来のはんだバンプにより接続された半導体
素子と配線基板の断面図で、第２図は正常な状態を示す
説明図、第３図は、温度変化により配線基板が膨張し、
バンプにせん断歪みが導入された様子を示す図、第４図
は、はんだバンプを圧力で接触させて、樹脂で固めた場
合の半導体素子構造の断面図である。 １……半導体素子、２……実装基板（配線基板）、３…
…はんだバンプ、４……金属電極、５……樹脂、６′…
…整形される前の超弾性バンプ、６……超弾性バンプ、
７……溶融した超弾性合金1 (a) to 1 (e) are schematic views of a method for immersing a semiconductor element in a melt of a low melting point superelastic alloy and selectively forming a superelastic bump on an electrode of the semiconductor element. Fig. 2 ~
FIG. 4 is a cross-sectional view of a conventional semiconductor device and a wiring board connected by solder bumps, FIG. 2 is an explanatory view showing a normal state, and FIG.
FIG. 4 is a cross-sectional view of a semiconductor element structure in a case where a shear strain is introduced into a bump, and FIG. 1 ... semiconductor element, 2 ... mounting board (wiring board), 3 ...
... solder bumps, 4 ... metal electrodes, 5 ... resin, 6 '...
... super-elastic bump before shaping, 6 ... super-elastic bump,
7 ... Melted superelastic alloy
───────────────────────────────────────────────────── フロントページの続き (72)発明者 大関 芳雄 神奈川県川崎市中原区井田1618番地 新 日本製鐵株式會社第１技術研究所内 (72)発明者 渡辺 敬介 東京都港区虎ノ門１丁目７番12号 沖電 気工業株式会社内 (72)発明者 金森 孝史 東京都港区虎ノ門１丁目７番12号 沖電 気工業株式会社内 (72)発明者 井口 泰男 東京都港区虎ノ門１丁目７番12号 沖電 気工業株式会社内 (56)参考文献 特開 平２−58346（ＪＰ，Ａ) 特開 昭64−81264（ＪＰ，Ａ) 特開 昭63−106979（ＪＰ，Ａ) 特開 昭62−258675（ＪＰ，Ａ) (58)調査した分野(Int.Cl.6，ＤＢ名) H01L 21/60 H01L 21/321──────────────────────────────────────────────────続 き Continuing from the front page (72) Inventor Yoshio Ozeki 1618 Ida, Nakahara-ku, Kawasaki-shi, Kanagawa Prefecture New Nippon Steel Corporation 1st Technical Research Institute (72) Inventor Keisuke Watanabe 1-7-7 Toranomon, Minato-ku, Tokyo No. 12 Oki Electric Industry Co., Ltd. (72) Inventor Takashi Kanamori 1-7-1, Toranomon, Minato-ku, Tokyo Oki Electric Industry Co., Ltd. (72) Inventor Yasuo Iguchi 1-7-7 Toranomon, Minato-ku, Tokyo No. 12 Oki Electric Industry Co., Ltd. (56) Reference JP-A-2-58346 (JP, A) JP-A 64-81264 (JP, A) JP-A 63-106979 (JP, A) JP-A Sho 62-258675 (JP, A) (58) Fields investigated (Int. Cl. 6 , DB name) H01L 21/60 H01L 21/321
Claims (2)
形成する手段として、溶融した超弾性合金に半導体素子
を浸漬させることにより、半導体素子の電極上に選択的
に超弾性バンプを形成することを特徴とするバンプ形成
方法。As a means for forming a bump (metal projection electrode) on a semiconductor element, a superelastic bump is selectively formed on an electrode of the semiconductor element by immersing the semiconductor element in a molten superelastic alloy. A method for forming a bump.
極上に選択的に形成した超弾性合金バンプを介して、加
熱溶融法により実装基板との電気的接続を得ることを特
徴とする半導体素子接続方法。2. A semiconductor according to claim 1, wherein an electrical connection with a mounting substrate is obtained by a heat melting method via a superelastic alloy bump selectively formed on an electrode of a semiconductor element. Element connection method.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1027299A JP2770040B2 (en) | 1989-02-06 | 1989-02-06 | Bump forming method and semiconductor element connecting method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1027299A JP2770040B2 (en) | 1989-02-06 | 1989-02-06 | Bump forming method and semiconductor element connecting method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH02206124A JPH02206124A (en) | 1990-08-15 |
| JP2770040B2 true JP2770040B2 (en) | 1998-06-25 |
Family
ID=12217213
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1027299A Expired - Fee Related JP2770040B2 (en) | 1989-02-06 | 1989-02-06 | Bump forming method and semiconductor element connecting method |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2770040B2 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH03209831A (en) * | 1990-01-12 | 1991-09-12 | Matsushita Electric Ind Co Ltd | Semiconductor device |
-
1989
- 1989-02-06 JP JP1027299A patent/JP2770040B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH02206124A (en) | 1990-08-15 |
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