JPH03276750A - Hybrid element and manufacture thereof - Google Patents
Hybrid element and manufacture thereofInfo
- Publication number
- JPH03276750A JPH03276750A JP2078227A JP7822790A JPH03276750A JP H03276750 A JPH03276750 A JP H03276750A JP 2078227 A JP2078227 A JP 2078227A JP 7822790 A JP7822790 A JP 7822790A JP H03276750 A JPH03276750 A JP H03276750A
- Authority
- JP
- Japan
- Prior art keywords
- indium
- bump
- electrodes
- semiconductor chips
- pair
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 8
- 239000004065 semiconductor Substances 0.000 claims abstract description 26
- 229910052738 indium Inorganic materials 0.000 claims abstract description 21
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical group [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 claims abstract description 20
- 229910000807 Ga alloy Inorganic materials 0.000 claims abstract description 13
- 239000000853 adhesive Substances 0.000 claims abstract description 13
- 230000001070 adhesive effect Effects 0.000 claims abstract description 13
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 claims description 18
- 229910052733 gallium Inorganic materials 0.000 claims description 9
- 239000000758 substrate Substances 0.000 claims description 7
- 230000008878 coupling Effects 0.000 claims description 6
- 238000010168 coupling process Methods 0.000 claims description 6
- 238000005859 coupling reaction Methods 0.000 claims description 6
- 230000002093 peripheral effect Effects 0.000 claims description 6
- 239000010409 thin film Substances 0.000 claims description 6
- 238000005275 alloying Methods 0.000 claims description 2
- 230000008018 melting Effects 0.000 abstract description 4
- 238000002844 melting Methods 0.000 abstract description 4
- 239000000203 mixture Substances 0.000 abstract description 4
- 230000006866 deterioration Effects 0.000 abstract description 3
- 230000005496 eutectics Effects 0.000 abstract description 3
- 229910000846 In alloy Inorganic materials 0.000 description 10
- 238000000034 method Methods 0.000 description 7
- 239000010408 film Substances 0.000 description 6
- 230000015572 biosynthetic process Effects 0.000 description 3
- 238000006243 chemical reaction Methods 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- 238000001514 detection method Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000002457 bidirectional effect Effects 0.000 description 1
- 229920006332 epoxy adhesive Polymers 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 150000002471 indium Chemical class 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 239000013464 silicone adhesive Substances 0.000 description 1
- 230000008646 thermal stress Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
- H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/13101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
- H01L2224/13109—Indium [In] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/0132—Binary Alloys
- H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
Landscapes
- Solid State Image Pick-Up Elements (AREA)
- Wire Bonding (AREA)
Abstract
Description
【発明の詳細な説明】
［産業上の利用分野］
本発明は一対の半導体チップを相互のバンプ電極同士を
対向させて電気的９機械的に結合するハイブリッド素子
及びその製造方法に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a hybrid element in which a pair of semiconductor chips are electrically and mechanically coupled with their bump electrodes facing each other, and a method for manufacturing the hybrid element.
［従来の技術］
半導体基板上に赤外線検出素子が配設されている光電変
換用半導体チップと、検出信号を処理する回路が形成さ
れたシリコンＩＣ半導体チップとを数千点以上の対応す
るバンプで結合したハイブリッド型赤外線イメージセン
サ−が知られている。[Prior Art] A photoelectric conversion semiconductor chip in which an infrared detection element is disposed on a semiconductor substrate and a silicon IC semiconductor chip in which a circuit for processing a detection signal is formed are connected to each other by using more than several thousand corresponding bumps. Hybrid infrared image sensors are known.
こうしたバンプ結合は、例えば特開昭５９−１５５１６
２号に示されているように、両チップのそれぞれ対応す
る位置にインジウム等の軟質金属からなる円柱状のバン
プ結合電極を形成し、目合わせして熱圧着し、電気的か
つ機械的に結合するものである。Such bump bonding is known, for example, in Japanese Patent Application Laid-open No. 59-15516.
As shown in No. 2, cylindrical bump bonding electrodes made of soft metal such as indium are formed at corresponding positions on both chips, aligned and bonded by thermocompression, and electrically and mechanically bonded. It is something to do.
このとき、対応するバンプ電極同士は電気的。 At this time, the corresponding bump electrodes are electrically connected.
機械的に充分に結合されなければならないが、従来のバ
ンプ結合電極では必すしも充分ではなかった。一般に光
電変換用半導体チップでは温度を」―げると素子特性が
劣化するため、例えばｌ−１ｇｃｄＴｅでは印加できる
温度は１００℃以下に制限される。Although sufficient mechanical bonding is required, conventional bump-coupled electrodes have not always been sufficient. In general, when the temperature of a semiconductor chip for photoelectric conversion is increased, the device characteristics deteriorate, so for example, in the case of l-1gcdTe, the temperature that can be applied is limited to 100°C or less.
方、１００℃以下で融解するものとしてガリウムや、イ
ンジウムとガリウムとの合金が知られているが、バンプ
形成プロセスの際の温度で融解してしまうなどの困難が
ある。従って通常はバンプ結合電極としてインジウムが
用いられ、結合は融解ではなく、あくまでも熱圧着によ
っている。しかし、このインジウムの表面に酸化皮膜が
形成されていると、加熱と加圧をしても酸化皮膜は破れ
にくく、これが結合の邪魔をして導通不良といった故障
や、接触抵抗の増加からくるノイズの増大といった特性
の劣化、さらには両チップ間の剥離を招き易い。On the other hand, gallium and alloys of indium and gallium are known as materials that melt at temperatures below 100° C., but these have problems such as melting at the temperature during the bump formation process. Therefore, indium is usually used as the bump bonding electrode, and the bonding is not by melting but by thermocompression bonding. However, when an oxide film is formed on the surface of this indium, the oxide film is difficult to break even when heated and pressurized, and this interferes with the bonding, resulting in failures such as poor continuity and noise due to increased contact resistance. This tends to lead to deterioration of characteristics such as an increase in the number of chips, as well as peeling between the two chips.
本発明の目的は、上記の欠点を解決し、充分に結合でき
るハイブリッド素子及びその製造方法を提供することに
ある。SUMMARY OF THE INVENTION An object of the present invention is to solve the above-mentioned drawbacks and provide a hybrid device that can be sufficiently combined and a method for manufacturing the same.
［課題を解決するための手段］
前記目的を達成するため、本発明に係るハイブリッド素
子においては、対向させた一対の半導体チップを電気的
に接続するバンプ結合電極を有するハイブリッド素子で
あって、
前記バンプ結合電極は、前記一対の半導体チップに接す
る基部かインジウムからなり、中間部がインジウムとガ
リウムとの合金からなるものであり、
さらに前記一対の半導体チップの周辺部を接着剤で機械
的に結合したものである。[Means for Solving the Problem] In order to achieve the above-mentioned object, a hybrid element according to the present invention is a hybrid element having a bump coupling electrode that electrically connects a pair of semiconductor chips facing each other, the hybrid element comprising: The bump bonding electrode has a base portion in contact with the pair of semiconductor chips made of indium, a middle portion made of an alloy of indium and gallium, and a peripheral portion of the pair of semiconductor chips mechanically bonded with an adhesive. This is what I did.
また、本発明に係るハイブリッド素子は、一対の半導体
チップのそれぞれにインジウムからなるバンプ電極を形
成し、前記一対の半導体チップの少なくとも一方に、ガ
リウムの薄膜を形成した平滑な基板を対向接触させて前
記バンプ電極の接触部すなわち頭部を合金化してから前
記平滑な基板を剥離した後、前記一対の半導体チップを
対向して結合し、さらにその周辺部を接着剤で固定する
製造方法により得られる。Further, in the hybrid element according to the present invention, a bump electrode made of indium is formed on each of a pair of semiconductor chips, and a smooth substrate on which a thin film of gallium is formed is brought into opposing contact with at least one of the pair of semiconductor chips. Obtained by a manufacturing method in which the contact portion, that is, the head of the bump electrode is alloyed, the smooth substrate is peeled off, the pair of semiconductor chips are bonded facing each other, and the peripheral portion thereof is further fixed with an adhesive. .
次に、本発明の実施例について図面を参照して説明する
。Next, embodiments of the present invention will be described with reference to the drawings.
第１図は本発明のハイブリッド素子の一実施例を示す断
面図であり、第２図はバンプ結合電極の拡大断面図であ
る。FIG. 1 is a sectional view showing an embodiment of the hybrid element of the present invention, and FIG. 2 is an enlarged sectional view of a bump-coupled electrode.
対向させた一対の半導体チップ１．２は、バンプ結合電
極３によって電気的に接続し、周辺部を接着剤４で機械
的に結合している。またバンプ結合電極３は半導体チッ
プ１，２のそれぞれの電極５，６に接する基部７，８は
インジウムとし、中間部９はインジウムとガリウムとの
合金としている。ここで、バンプ結合電極３の高さは約
２０ｐｍ、また中間部９のインジウムとガリウムとの合
金厚さが約２１、組成比はインジウムが約１６％の共晶
組成としている。A pair of opposing semiconductor chips 1.2 are electrically connected by bump bonding electrodes 3 and mechanically bonded at their peripheral portions by adhesive 4. Further, in the bump coupling electrode 3, the base portions 7 and 8 in contact with the respective electrodes 5 and 6 of the semiconductor chips 1 and 2 are made of indium, and the intermediate portion 9 is made of an alloy of indium and gallium. Here, the height of the bump bonding electrode 3 is approximately 20 pm, the thickness of the alloy of indium and gallium in the intermediate portion 9 is approximately 21, and the composition ratio is a eutectic composition in which indium is approximately 16%.
良く知られているように、共晶組成のインジウムとガリ
ウムとの合金の融点は約１７℃と低く、通常の室温では
バンプ結合電極３の中間部９は融けた状態となっており
、従来のインジウムのみのバンプによる結合での酸化膜
による電気的な接続不良の問題はない。一方、機械的な
結合強度は室温では周辺部の接着剤４が、また７７Ｋに
冷却した動作時には接着剤４と固体化したバンプ結合電
極３が寄与するため、剥離の問題もない。さらに、この
インジウムとガリウムとの合金の中間部により、両生導
体チップの熱膨張率の差による熱ストレスの影響を受け
にくいという利点もあり、時間的な劣化もないものとな
っている。As is well known, the melting point of an alloy of indium and gallium with a eutectic composition is as low as about 17°C, and at normal room temperature, the middle part 9 of the bump bonded electrode 3 is in a molten state, which is different from the conventional one. There is no problem of electrical connection failure due to the oxide film when bonding using only indium bumps. On the other hand, the mechanical bonding strength is contributed by the adhesive 4 in the periphery at room temperature, and by the adhesive 4 and the solidified bump bonding electrode 3 during operation cooled to 77K, so there is no problem of peeling. Furthermore, the intermediate portion of the alloy of indium and gallium has the advantage that it is less susceptible to thermal stress due to the difference in thermal expansion coefficients of the bidirectional conductor chips, and there is no deterioration over time.
次に、このバンプ結合電極の形成方法を説明する。Next, a method for forming this bump bonding electrode will be explained.
第３図（ａ）〜（ロ）は本発明のハイブリッド素子の製
造方法の一実施例を工程順に示す部分拡大断面図である
。FIGS. 3(a) to 3(b) are partially enlarged cross-sectional views showing one embodiment of the method for manufacturing a hybrid element of the present invention in the order of steps.
まず、第３図（ａ）に示すように従来の通常の形成方法
によって半導体チップ１１の電極１５上にインジウムか
らなるバンプ基部１７を形成する。次いで、第３図（ハ
）に示すように、ガリウムの薄膜２０を形成した平滑な
基板２１を対向接触させる。このとき、ガリウムの薄膜
２０は必ずしも融解している必要はなく、温度は室温か
ら３５℃程度としておけば良い。First, as shown in FIG. 3(a), a bump base 17 made of indium is formed on the electrode 15 of the semiconductor chip 11 by a conventional normal forming method. Next, as shown in FIG. 3(c), a smooth substrate 21 on which a gallium thin film 20 is formed is brought into opposing contact. At this time, the gallium thin film 20 does not necessarily need to be melted, and the temperature may be kept at about 35° C. from room temperature.
この状態で第３図０に示すようにガリウムの薄膜２０と
バンプ基部Ｉ７の接触部２５のインジウムを合金化させ
た後、第３図（ロ）に示すように平滑な基板２１を剥離
することで、頭部２２がインジウムとガリウムとの合金
からなるバンブ電極２３の形成が完了する。一方半導体
チツブ１２の電極１６上には第３図（ｅ）に示すように
インジウムのみからなるバンブ電極２４を形成する。In this state, as shown in FIG. 30, the gallium thin film 20 and indium at the contact portion 25 of the bump base I7 are alloyed, and then the smooth substrate 21 is peeled off as shown in FIG. 3(b). This completes the formation of the bump electrode 23 whose head 22 is made of an alloy of indium and gallium. On the other hand, a bump electrode 24 made only of indium is formed on the electrode 16 of the semiconductor chip 12, as shown in FIG. 3(e).
ここで、高さ２０μｍのバンプ結合電極３を形成しよう
とする場合は、インジウムからなるバンプ基部Ｉ７、及
びバンブ電極２４の高さをそれぞれｌｏｐｍ程度とし、
ガリウムの薄膜２０の膜厚をｌｐｍ程度としておけば良
い。また、ガリウムの簿膜２０とバンプ基部１７のイン
ジウムを合金化させる時間としては、温度によっても変
わるが、室温で１０分程度でよい。Here, when trying to form the bump coupling electrode 3 with a height of 20 μm, the heights of the bump base I7 made of indium and the bump electrode 24 are each about lopm,
The thickness of the gallium thin film 20 may be approximately lpm. Further, the time for alloying the gallium film 20 and the indium of the bump base 17 may vary depending on the temperature, but may be about 10 minutes at room temperature.
次に、第３図のに示すように両生導体チップ１１゜１２
を向い合わせ、目合わせして各々の対応するバンプ電極
２３．２４を接触させることでバンブ電極が接続され、
バンプ結合電極１３の形成が完了する。Next, as shown in FIG.
The bump electrodes are connected by facing each other, aligning them, and bringing the corresponding bump electrodes 23 and 24 into contact with each other.
Formation of bump coupling electrode 13 is completed.
このとき、バンブ電極２３の頭部２２のインジウムとガ
リウムとの合金は融けた状態となっておりバンブ電極２
４のインジウムと容易に合金化し、バンプ結合電極１３
の中間部１９となる。尚、このままでも従来のような酸
化膜の問題はなく、十分な電気接続を行えるが、さらに
これを加熱、加圧することでより完全に接続することが
できる。At this time, the alloy of indium and gallium in the head 22 of the bump electrode 23 is in a molten state, and the bump electrode 23 is in a molten state.
Easily alloyed with indium of No. 4, bump bonding electrode 13
This is the middle part 19 of . It should be noted that even with this as it is, there is no problem with the oxide film as in the prior art, and a sufficient electrical connection can be made, but a more complete connection can be made by further heating and pressurizing this.
最後に、第３図＠に示すように、結合した両生導体チッ
プＩＩ、 ＋２の周辺部を接着剤１４で機械的に固定結
合し、ハイブリッド素子の製造が完了する。Finally, as shown in FIG. 3, the peripheral portions of the combined amphibic conductor chips II and +2 are mechanically fixedly connected using adhesive 14, completing the production of the hybrid element.
ここで接着剤としては通常のエポキシ系接着剤でも、又
やや弾力のあるシリコン系接着剤でも良い。The adhesive here may be a normal epoxy adhesive or a slightly elastic silicone adhesive.
なお、以上の実施例では一方の半導体チップのバンブ電
極の頭部のみをインジウムとガリウムとの合金としてい
るが、これを両方の半導体チップに適用しても全く同様
であることは言うまでもない。In the above embodiment, only the head of the bump electrode of one semiconductor chip is made of an alloy of indium and gallium, but it goes without saying that the same effect can be obtained even if this is applied to both semiconductor chips.
以上説明したように本発明によれば、バンブ電極の接続
部をインジウムとガリウムとの合金とし８−
ており、従来のインジウムバンプ結合での酸化膜による
接続不良がないため、電気的に充分に接続され、かつ機
械強度の問題もない、充分に結合されたハイブリッド素
子が得られる。As explained above, according to the present invention, the connection part of the bump electrode is made of an alloy of indium and gallium8-, and there is no connection failure due to the oxide film in conventional indium bump bonding, so it is electrically sufficient. A well-coupled hybrid element is obtained which is connected and has no mechanical strength problems.
【図面の簡単な説明】
第１図は本発明のハイブリッド素子の一実施例を示す断
面図、第２図はバンプ結合電極の拡大断面図、第３図（
ａ）〜■は本発明のハイブリッド素子の製造方法の一実
施例を工程順に示しす部分拡大断面図である。[Brief Description of the Drawings] Fig. 1 is a sectional view showing one embodiment of the hybrid element of the present invention, Fig. 2 is an enlarged sectional view of a bump-coupled electrode, and Fig. 3 (
a) to {circle around (2)} are partially enlarged cross-sectional views showing one embodiment of the method for manufacturing a hybrid element of the present invention in the order of steps;
Claims (2)
るバンプ結合電極を有するハイブリッド素子であって、 前記バンプ結合電極は、前記一対の半導体チップに接す
る基部がインジウムからなり、中間部がインジウムとガ
リウムとの合金からなるものであり、 さらに前記一対の半導体チップの周辺部を接着剤で機械
的に結合したことを特徴とするハイブリッド素子。(1) A hybrid element having a bump coupling electrode that electrically connects a pair of opposing semiconductor chips, wherein the bump coupling electrode has a base portion in contact with the pair of semiconductor chips made of indium, and an intermediate portion made of indium. What is claimed is: 1. A hybrid element comprising an alloy of gallium and gallium, and further comprising: a peripheral portion of the pair of semiconductor chips mechanically bonded to each other with an adhesive.
なるバンプ電極を形成し、前記一対の半導体チップの少
なくとも一方に、ガリウムの薄膜を形成した平滑な基板
を対向接触させて前記バンプ電極の接触部すなわち頭部
を合金化してから前記平滑な基板を剥離した後、前記一
対の半導体チップを対向して結合し、さらにその周辺部
を接着剤で固定することを特徴とするハイブリッド素子
の製造方法。(2) A bump electrode made of indium is formed on each of a pair of semiconductor chips, and a smooth substrate on which a thin film of gallium is formed is brought into opposing contact with at least one of the pair of semiconductor chips, so that the contact portion of the bump electrode is A method of manufacturing a hybrid element, comprising: alloying the head, peeling off the smooth substrate, bonding the pair of semiconductor chips facing each other, and further fixing the peripheral portions with an adhesive.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2078227A JP2546407B2 (en) | 1990-03-27 | 1990-03-27 | Hybrid element and manufacturing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2078227A JP2546407B2 (en) | 1990-03-27 | 1990-03-27 | Hybrid element and manufacturing method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH03276750A true JPH03276750A (en) | 1991-12-06 |
| JP2546407B2 JP2546407B2 (en) | 1996-10-23 |
Family
ID=13656165
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2078227A Expired - Lifetime JP2546407B2 (en) | 1990-03-27 | 1990-03-27 | Hybrid element and manufacturing method thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2546407B2 (en) |
Cited By (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1994018698A1 (en) * | 1993-02-09 | 1994-08-18 | Hans Peter Peloschek | METHOD FOR ELECTRICALLY CONDUCTIVE CONNECTING AND MECHANICAL FASTENING OF ICs ON CONDUCTING PATTERNS OF SUBSTRATES AND THE APPLICATION THEREOF |
| JPH0758149A (en) * | 1993-08-11 | 1995-03-03 | Nec Corp | Method for mounting chip part |
| US5440454A (en) * | 1993-10-14 | 1995-08-08 | Fujitsu Limited | Electrical connecting device and method for making same |
| US5610371A (en) * | 1994-03-15 | 1997-03-11 | Fujitsu Limited | Electrical connecting device and method for making same |
| US6032852A (en) * | 1997-09-22 | 2000-03-07 | Trw Inc. | Reworkable microelectronic multi-chip module |
| WO2002007219A1 (en) * | 2000-07-17 | 2002-01-24 | Rohm Co., Ltd. | Semiconductor device and its manufacturing method |
| US6583514B2 (en) | 2000-10-04 | 2003-06-24 | Nec Corporation | Semiconductor device with a binary alloy bonding layer |
| WO2005119776A1 (en) * | 2004-06-04 | 2005-12-15 | Zycube Co., Ltd. | Semiconductor device having three-dimensional stack structure and method for manufacturing the same |
| US7112468B2 (en) | 1998-09-25 | 2006-09-26 | Stmicroelectronics, Inc. | Stacked multi-component integrated circuit microprocessor |
| US7906363B2 (en) | 2004-08-20 | 2011-03-15 | Zycube Co., Ltd. | Method of fabricating semiconductor device having three-dimensional stacked structure |
| JP2011134770A (en) * | 2009-12-22 | 2011-07-07 | Sumitomo Electric Ind Ltd | Detector, light-receiving element array, and method of manufacturing the detector |
| JP2011146603A (en) * | 2010-01-15 | 2011-07-28 | Sumitomo Electric Ind Ltd | Detection device, photodetector array, electronic apparatus, and methods of manufacturing the same |
| JP2016066683A (en) * | 2014-09-24 | 2016-04-28 | 住友電気工業株式会社 | Infrared image sensor |
-
1990
- 1990-03-27 JP JP2078227A patent/JP2546407B2/en not_active Expired - Lifetime
Cited By (24)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1994018698A1 (en) * | 1993-02-09 | 1994-08-18 | Hans Peter Peloschek | METHOD FOR ELECTRICALLY CONDUCTIVE CONNECTING AND MECHANICAL FASTENING OF ICs ON CONDUCTING PATTERNS OF SUBSTRATES AND THE APPLICATION THEREOF |
| JPH0758149A (en) * | 1993-08-11 | 1995-03-03 | Nec Corp | Method for mounting chip part |
| US5746927A (en) * | 1993-10-14 | 1998-05-05 | Fujitsu Limited | Electrical connecting device and method for making same |
| US5440454A (en) * | 1993-10-14 | 1995-08-08 | Fujitsu Limited | Electrical connecting device and method for making same |
| US5603981A (en) * | 1993-10-14 | 1997-02-18 | Fujitsu Limited | Electrical connecting device and method for making same |
| US5610371A (en) * | 1994-03-15 | 1997-03-11 | Fujitsu Limited | Electrical connecting device and method for making same |
| US6032852A (en) * | 1997-09-22 | 2000-03-07 | Trw Inc. | Reworkable microelectronic multi-chip module |
| US6050476A (en) * | 1997-09-22 | 2000-04-18 | Trw Inc. | Reworkable microelectronic multi-chip module |
| US7112468B2 (en) | 1998-09-25 | 2006-09-26 | Stmicroelectronics, Inc. | Stacked multi-component integrated circuit microprocessor |
| WO2002007219A1 (en) * | 2000-07-17 | 2002-01-24 | Rohm Co., Ltd. | Semiconductor device and its manufacturing method |
| EP1229583A1 (en) * | 2000-07-17 | 2002-08-07 | Rohm Co., Ltd. | Semiconductor device and its manufacturing method |
| US6734556B2 (en) | 2000-07-17 | 2004-05-11 | Rohm Co., Ltd. | Semiconductor device with chip-on-chip construction joined via a low-melting point metal layer |
| US7384863B2 (en) | 2000-07-17 | 2008-06-10 | Rohm Co., Ltd. | Semiconductor device and method for manufacturing the same |
| EP1229583A4 (en) * | 2000-07-17 | 2007-01-03 | Rohm Co Ltd | Semiconductor device and its manufacturing method |
| KR100846270B1 (en) * | 2000-07-17 | 2008-07-16 | 로무 가부시키가이샤 | Semiconductor device and its manufacturing method |
| US6583514B2 (en) | 2000-10-04 | 2003-06-24 | Nec Corporation | Semiconductor device with a binary alloy bonding layer |
| WO2005119776A1 (en) * | 2004-06-04 | 2005-12-15 | Zycube Co., Ltd. | Semiconductor device having three-dimensional stack structure and method for manufacturing the same |
| JPWO2005119776A1 (en) * | 2004-06-04 | 2008-04-03 | 株式会社ザイキューブ | Semiconductor device having three-dimensional laminated structure and method for manufacturing the same |
| JP5052130B2 (en) * | 2004-06-04 | 2012-10-17 | カミヤチョウ アイピー ホールディングス | Semiconductor device having three-dimensional laminated structure and method for manufacturing the same |
| US7906363B2 (en) | 2004-08-20 | 2011-03-15 | Zycube Co., Ltd. | Method of fabricating semiconductor device having three-dimensional stacked structure |
| JP2011134770A (en) * | 2009-12-22 | 2011-07-07 | Sumitomo Electric Ind Ltd | Detector, light-receiving element array, and method of manufacturing the detector |
| US8969851B2 (en) | 2009-12-22 | 2015-03-03 | Sumitomo Electric Industries, Ltd. | Detection device, photodiode array, and method for manufacturing the same |
| JP2011146603A (en) * | 2010-01-15 | 2011-07-28 | Sumitomo Electric Ind Ltd | Detection device, photodetector array, electronic apparatus, and methods of manufacturing the same |
| JP2016066683A (en) * | 2014-09-24 | 2016-04-28 | 住友電気工業株式会社 | Infrared image sensor |
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| Publication number | Publication date |
|---|---|
| JP2546407B2 (en) | 1996-10-23 |
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