JPH04213832A - Semiconductor element having solder bump electrode - Google Patents

Abstract

PURPOSE:To avoid the defective junction of the solder bump electrode of a semiconductor flip chip element due to the gouging on the silicon chip surface. CONSTITUTION:In order to form a solder bump electrode 50 above a semiconductor substrate 41 in PN junction, an opening is made in an insulating film 43; a contact hole 44 is formed in the central part of the surface whereon said bump electrode 50 is formed; while the diameter phi2 of said contact hole 44 is made smaller than the diameter phi1 of the contact surface of said solder bump electrode 50; the ends of the surface whereon said bump electrode 50 is formed are separated from the semiconductor substrate 41 by said insulating film 43.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to the structure of a semiconductor element having solder bump electrodes.

0002

[Prior Art] Conventionally, technologies in this field include:
For example, Japanese Patent Publication No. 43-28735, Japanese Patent Publication No. 62-16
There was one described in No. 0744. FIG. 3 is a sectional view showing a solder bump electrode structure of a semiconductor flip chip device having such a conventional solder bump electrode.

Generally, methods for forming solder bumps on semiconductor flip chip devices include selective vapor deposition, electroplating, solder ball method, and solder dip method. A solder bump electrode of a semiconductor flip device formed by electroplating has a cross-sectional shape as shown in FIG. That is, the solder bump electrode is formed directly above the PN junction through which a large current can flow. Normally, solder bump electrodes are often formed on an insulating film, but when a large-area semiconductor layer is placed at the output in order to flow a large current, as shown in this figure, it is necessary to , a solder bump electrode is formed directly above the PN junction.

In this figure, 1 is a P-type semiconductor substrate; 2 is a P-type semiconductor substrate;
is an N-type semiconductor diffusion layer, 3 is an insulating film, and 4 is a window region provided for electrically connecting the N-type semiconductor diffusion layer 2 to the outside via a solder bump electrode. 5 is an Al electrode pad, and 6 is a glass film (passivation protective film) formed by the CVD method. 7 and 8 are an Al--Ni alloy layer and a Ni layer formed by vapor deposition, respectively. 9 is a Cu plating layer formed by a plating method, and 10 is a solder bump in which the solder plating layer formed by a plating method becomes spherical due to surface tension during subsequent melting treatment.

Next, an example will be described in which a flip chip element having solder bump electrodes is directly mounted on a mounting substrate such as ceramic. FIG. 4 is a cross-sectional view of a flip chip device with solder bump electrodes. In this figure, 11 is a semiconductor substrate (silicon chip), 12 is an insulating film, and 13 is a solder bump electrode. Solder bump electrode 13
A detailed explanation of the connecting portion between the semiconductor substrate 11 and the semiconductor substrate 11 has the structure shown in FIG. 3, but from FIG. 4 onwards, the connecting portion will be omitted from illustration. Normally, a semiconductor substrate has a plurality of 3 to 10 solder bump electrodes 13 for connection with the outside, and sometimes as many as 200 solder bump electrodes 13 are formed on both ends of the flip chip element 22. This will be explained in detail using only the two solder bump electrodes.

FIG. 5 shows a state in which the thus obtained flip chip element is directly mounted on a mounting substrate such as a ceramic substrate. In this figure, reference numeral 21 denotes a mounting substrate (ceramic substrate), on which a flip chip element 22 having the solder bump electrodes 13 described above is mounted.

[0007]

[Problems to be Solved by the Invention] However, in the solder bump electrode structure described above, for example, two
In the process of melting the solder at 00 to 220°C and then cooling it to room temperature, stress is applied due to misalignment of the solder bump connection due to the difference in thermal expansion coefficient between the semiconductor substrate and the mounted substrate such as ceramic. , a problem occurs in that the semiconductor substrate on the flip chip side is destroyed and gouged out. This situation will be explained using FIGS. 6 to 9.

From FIG. 6 onwards, a case will be described in which ceramic is used for the mounting substrate 21 and silicon is used for the semiconductor substrate 11. In the connection process, silicon chip 1
1 is mounted face down on a ceramic substrate 21 with the solder bump electrode 13 as a fulcrum. In FIG. 6, the face surface of the silicon chip 11 is covered with an insulating film 12. Thereafter, the ceramic substrate 21 with the silicon chip 11 mounted thereon is inserted into a 220° C. reflow oven, and the solder bumps 10 are melted at this temperature of 220° C. and are preformed at predetermined positions on the ceramic substrate 21 side. It is glued with a metal pattern.

Next, the ceramic substrate 21 with the silicon chip 11 mounted thereon is taken out of the reflow oven and cooled to room temperature. At this time, the ceramic substrate 21 and the silicon chip 11 are connected by solder when the solder is melted, and are cooled while being fixed as such. occurs. Let's now calculate the amount of this deviation.

As shown in FIG. 6, if point C of the solder bump electrode on one side is considered as a fulcrum, the difference in shrinkage between the silicon chip 11 and the ceramic substrate 21 near the solder bump electrode 13 on the other side is as follows. When the distance between the electrodes of the silicon chip 11 is 8 mm, the amount of shrinkage Δl of the ceramic substrate 21 is
c is Δlc=6.5×10-6/℃×(220℃-20
℃)×8mm=10.4μm The shrinkage amount Δls of the silicon chip 11 is Δls=3.5×10-6/℃×
(220° C.-20° C.)×8 mm=5.6 μm Difference in shrinkage=Δlc−Δls=10.4−5.6=4.8 μm.

In reality, it is reasonable to assume that the amount of deviation is not applied only to one electrode with point C as the fulcrum, but is applied uniformly to both sides in the case of a chip that is symmetrical on both sides. The amount of deviation caused by this is estimated to be 2.4 μm. The manner in which the force of displacement described in FIG. 6 is applied to one solder pump electrode will be described with reference to FIG. 7.

In FIG. 7, reference numeral 31 denotes an electrode for connecting the solder bump 10 and the silicon chip 11. As shown in FIG. Both the silicon chip 11 and the ceramic substrate 21 shrink at the same time, but there is a difference in the amount, so when focusing on one solder bump electrode, the solder bump 10 shrinks in the opposite direction as shown by arrows D and E in FIG. This results in the addition of stress. Due to this stress, the silicon chip 11 is gouged out at the weakest point in the silicon chip 11/solder bump 10/ceramic substrate 21 connection system, that is, the surface of the silicon chip 11, as shown in FIG. This may cause an open failure in which the connection between the silicon chip 11 and the ceramic substrate 21 becomes defective.

The phenomenon in which the silicon chip 11 side is gouged will be explained in more detail. In FIG. 9 showing a partial enlargement of FIG. 3, the boundary surfaces indicated by letters F to J and arrows are:
Solder and copper, copper and Ni, Ni and Al-Ni alloy, respectively.
These are the bonding surfaces of Al-Ni alloy and Al, and Al and silicon, but each surface has very strong adhesive strength, and when stress as shown by arrow K in the figure is applied, the area indicated by L in the figure appears as if it were It moves as if it were a single object, and stress is generated in the direction opposite to the direction M of the force applied to the silicon chip 11.

[0014] Also, if we examine the distribution of the stress generated at this time, indicated by the arrow K in the figure, we will see that when we compare the point N at the end of the joint surface with the point O at the center of the joint surface, the stress at point N is the stress at point O. It is well known that it is larger. In this solder bump electrode structure where the strength of the bonding surface is extremely strong, when stress is generated in the solder bump electrode, the silicon is gouged out near the N point, which is the area where stress is concentrated on the surface of the relatively fragile silicon chip 11, resulting in an open hole. Generate defects.

SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor element having a solder bump electrode which can prevent bonding failure due to the solder bump electrode going into the surface of a silicon chip as described above.

[0016]

[Means for Solving the Problems] In order to achieve the above object, the present invention includes a semiconductor substrate, an insulating film formed on the semiconductor substrate, and a semiconductor substrate and an external terminal formed on a part of the insulating film. A wiring metal electrode is formed on a part of the insulating film to cover the contact hole, and a passivation protection is applied to cover the entire semiconductor surface, including the wiring metal electrode. A semiconductor element having a solder bump electrode in which a film is formed, a part of the passivation protective film in a region covering the wiring metal electrode is opened, and the wiring metal electrode and the solder bump electrode are connected through the opening. A contact hole is formed in the insulating film at the center of the surface on which the solder bump electrode is formed, and the diameter of the contact hole is made smaller than the diameter of the connection surface of the solder bump electrode. The end portion of the surface where is formed is separated from the semiconductor substrate by the insulating film.

[0017]

[Operation] According to the present invention, as described above, in a semiconductor element having solder bump electrodes, when the solder bump electrodes are formed directly on the semiconductor substrate of the PN junction, the window opening area of the insulating film directly under the solder bump electrodes is provided. is provided in the center of the solder bump electrode joint where stress is relatively low, and in a small size. Therefore, the only force directly transmitted to the semiconductor substrate is a small force generated at the center of the solder bump joint, and a large force generated at the edge of the solder bump joint is relaxed on the insulating film, which has relatively weak adhesion. In other words, the part where stress tends to concentrate at the end of the solder bump electrode joint is separated by a stress-resistant insulating film between the solder bump electrode and the PN junction, so that the stress applied to the solder bump electrode is not directly applied to the semiconductor substrate. be able to.

[0018] Therefore, it is possible to prevent open failures in which silicon is gouged out due to stress applied to the solder bump electrodes. The only force directly transmitted to the semiconductor substrate is a small force generated at the center of the solder bump joint, and a large force generated at the edge of the solder bump joint is relaxed on the insulating film, which has relatively weak adhesion.

[0019]

Embodiments Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. FIG. 1 is a sectional view showing a solder bump electrode structure of a semiconductor flip-chip device formed by electroplating according to an embodiment of the present invention. In this figure, 41
42 is a P-type semiconductor substrate, 42 is an N-type semiconductor layer, 43 is an insulating film, 44 is a contact hole for connection made in the insulating film 43, 45 is an Al electrode pad, and 46 is a glass formed by the CVD method. Film (passivation film), 47, 48
are an Al-Ni alloy layer formed by vapor deposition, and N
i layer, 49 is a Cu plating layer formed by plating method,
50 is a solder bump in which a solder plating layer formed by a plating method becomes spherical due to surface tension during subsequent melting treatment. Further, 51 is a contact hole formed in the glass film 46.

As shown in this figure, the solder bump electrode and N
The type semiconductor layer 42 is connected to an Al electrode pad 45 through a contact hole 44 made in the insulating film 43 at the center of the joint directly under the solder bump electrode and made as small as possible at least smaller than the joint. ing. The process of forming this solder bump electrode on a flip chip element, directly mounting it on a ceramic substrate, etc., and applying stress due to the difference in thermal expansion coefficient to the solder bump electrode by cooling after connection by solder reflow is explained in the conventional technology section. I have already explained this, so I will omit it here.

Next, a detailed description will be given of the structure in which the stress applied to the solder bump electrodes is not directly applied to the silicon substrate. FIG. 2 is an enlarged sectional view showing a portion of a contact hole formed in an insulating film, which is at least as small as possible and smaller than the bonding portion, at the center of the bonding portion directly below the solder bump electrode in FIG.

As shown in this figure, the stress generated due to the difference in thermal expansion coefficients between the ceramic substrate and the silicon substrate causes forces in opposite directions indicated by arrows L and M at the connection between the solder bump electrode and the silicon substrate. Join next. However, the stress in solder bump joints is small at the joint center;
Since the stress distribution is large at the end of the bonding portion, the stress on the silicon substrate represented by the P-type semiconductor substrate 41 and the N-type semiconductor layer 42 acts directly on the inside of the contact hole 44 made in the insulating film 43. For example, there is only a small stress indicated by the arrow from point O. Also, regarding the large stress acting on the edge of the joint, for example, as indicated by the arrow from the N point, the Al electrode pad 45 and the insulating film 43 (generally a SiO2 film)
The boundary 53 between the N-type semiconductor layer 42 and the Al electrode pad 4
Compared to the boundary 52 with 5, the adhesion strength is weak, and as Al slides on the insulating film 43, it is relaxed, and large stress acts directly on the insulating film 43, the P-type semiconductor substrate 41, and the N-type semiconductor layer 42. This means that the silicone will no longer be gouged out.

For example, as shown in FIG. 4, the distance between the solder bump electrodes is 8 mm, and the solder bump electrode bonding surface is φ1 (10
0 μmφ) In the case of a certain semiconductor flip chip device, the contact hole diameter of the insulating film 43 is changed from 100 μmφ to φ2.
It has been found that by changing the diameter to (50 μmφ), the incidence of gouging defects becomes approximately 0%. However, if the diameter of the contact hole in the insulating film becomes too small, problems such as an increase in electrical resistance and limitations in film formation will occur.

Therefore, in the present invention, it is desirable that the diameter of the contact hole in the insulating film is 50 to 60% of the diameter of the connection surface of the solder bump electrode. In addition,
The present invention is not limited to the above embodiments, and various modifications can be made based on the spirit of the present invention, and these are not excluded from the scope of the present invention.

[0025]

As described above in detail, according to the present invention, when a contact hole is formed in an insulating film directly under a solder bump electrode for electrical connection with a semiconductor substrate, the solder bump electrode Since we have made a small hole in the center of the bonding surface, the only force directly transmitted to the semiconductor substrate is the small force generated at the center of the solder bump joint, and the large force generated at the edge of the solder bump joint is due to the comparison of adhesion strength. It is relaxed on a weak insulating film. Therefore, it is possible to obtain a semiconductor element having highly reliable solder bump electrodes in which the silicon substrate is not gouged out.

[Brief explanation of the drawing]

FIG. 1 is a cross-sectional view of a solder bump electrode of a semiconductor flip-chip device formed by electroplating according to an embodiment of the present invention.

2 is an enlarged cross-sectional view showing a portion of a contact hole formed in an insulating film, which is at least as small as possible and smaller than the bonding portion, at the center of the bonding portion directly below the solder bump electrode in FIG. 1; FIG.

FIG. 3 is a cross-sectional view of a solder bump electrode of a semiconductor flip-chip device formed by conventional electroplating.

FIG. 4 is a cross-sectional view of a semiconductor flip chip device having conventional solder bump electrodes.

FIG. 5 is a sectional view showing a state in which a conventional semiconductor flip chip element having solder bump electrodes is mounted on a ceramic substrate.

FIG. 6 is a cross-sectional view showing how stress is generated when a conventional semiconductor flip-chip element having solder bump electrodes is mounted on a ceramic substrate.

FIG. 7 is a cross-sectional view showing a state in which shear force is generated on the solder bump electrodes when a semiconductor flip-chip element having conventional solder bump electrodes is mounted on a ceramic substrate.

FIG. 8 is a cross-sectional view showing a gouged state of a silicon chip, which shows a conventional problem.

9 is a partially enlarged cross-sectional view of FIG. 3 showing how stress is generated on solder bump electrodes of a conventional semiconductor flip-chip device.

[Explanation of symbols]

41 P-type semiconductor substrate 42 N-type semiconductor layer 43 Insulating film 44, 51 Contact hole 45 Al electrode pad 46 Glass film (passivation film) 47, 4
8 Al-Ni alloy layer, Ni layer 49 Cu
Plating layer 50 Solder bump

Claims (2)

[Claims] 1. A semiconductor substrate, an insulating film formed on the semiconductor substrate, and a contact hole for electrically connecting the semiconductor substrate and an external terminal in a part of the insulating film, the contact hole being A wiring metal electrode is formed on a part of the insulating film so as to cover it, and a passivation protection film is formed to cover the entire semiconductor surface including the wiring metal electrode,
In a semiconductor element having a solder bump electrode in which a part of the passivation protective film in a region covering the wiring metal electrode is opened, and the wiring metal electrode and the solder bump electrode are connected through the opening, (a) the insulating film A contact hole is formed in the center of the surface on which the solder bump electrode is formed, and (
b) Soldering characterized in that the diameter of the contact hole is smaller than the diameter of the connection surface of the solder bump electrode, and the end of the surface on which the solder bump electrode is formed is separated from the semiconductor substrate by the insulating film. A semiconductor element with bump electrodes. 2. A semiconductor device having a solder bump electrode according to claim 1, wherein the diameter of the contact hole is 50 to 60% of the diameter of the connection surface of the solder bump electrode.