JP2929764B2 - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JP2929764B2 JP2929764B2 JP3134521A JP13452191A JP2929764B2 JP 2929764 B2 JP2929764 B2 JP 2929764B2 JP 3134521 A JP3134521 A JP 3134521A JP 13452191 A JP13452191 A JP 13452191A JP 2929764 B2 JP2929764 B2 JP 2929764B2
- Authority
- JP
- Japan
- Prior art keywords
- chip
- projection type
- type electrode
- electrode
- pad
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/102—Material of the semiconductor or solid state bodies
- H01L2924/1025—Semiconducting materials
- H01L2924/10251—Elemental semiconductors, i.e. Group IV
- H01L2924/10253—Silicon [Si]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
Abstract
Description
【0001】[0001]
【産業上の利用分野】本発明は、半導体チップのパッケ
ージに関し、特にTAB(Tape Automate
d Bonding)を利用したパッケージに関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor chip package, and more particularly to a TAB (Tape Automate).
d Bonding).
【0002】[0002]
【従来の技術】従来のTABによるパッケージは図3に
示すような構造となっている。例えば、ポリイミドなど
の樹脂フィルム上にテープを送り用のガイドとしてスプ
ロケットホール25を設け、さらに、テープの中央部に
は半導体チップを搭載できるようにデバイスホールをも
うけ、その内へチップ上の電極へ接続するためのTAB
リード27を設けている。このTABリード27には、
チップの電気的な選別ができるようにフィルム上にパッ
ド26を設けてある。2. Description of the Related Art A conventional TAB package has a structure as shown in FIG. For example, a sprocket hole 25 is provided as a guide for feeding a tape on a resin film such as polyimide, and a device hole is provided in a central portion of the tape so that a semiconductor chip can be mounted thereon. TAB to connect
A lead 27 is provided. In this TAB lead 27,
Pads 26 are provided on the film so that the chips can be electrically selected.
【0003】このようにして、リードは金またはスズな
どのメッキで、被覆されている。このようなリードの先
端部に対応する位置に半導体チップのパッド上に金など
で突起形電極28をもうけて、通常インナーリードボン
ディング(ILB)という工程でかつボンディングで、
バンプとリードを熱圧着でボンディングする。これを側
面から見ると図3(b)のような形となる。[0003] In this way, the leads are covered with plating of gold or tin. A protruding electrode 28 is formed with gold or the like on a pad of a semiconductor chip at a position corresponding to the tip of such a lead, and is usually formed by a process called inner lead bonding (ILB) and bonding.
The bump and the lead are bonded by thermocompression bonding. When viewed from the side, the shape is as shown in FIG.
【0004】[0004]
【発明が解決しようとする課題】このような半導体パッ
ケージでは、小さいチップの少ないピンのものでは問題
ないが、大チップ高速の高パワーのものになると周辺部
からのみの電源、グランドの引き出しのみでは十分に電
力を供給できなくなる欠点があった。In such a semiconductor package, there is no problem with a small package having a small number of pins and a small number of pins. There was a drawback that power could not be supplied sufficiently.
【0005】現在、バイポーラのECLデバイスでは、
例えば50W〜100Wというようなものも実現的なも
のとなってきており、ICチップにいかに電源を流しこ
めるかが高速化の達成に不可欠となってきた。At present, in a bipolar ECL device,
For example, a power of 50 W to 100 W has become practical, and how to supply power to the IC chip has become indispensable for achieving high speed.
【0006】本発明の目的は、十分な給電能力が得られ
る半導体装置を提供することにある。An object of the present invention is to provide a semiconductor device capable of obtaining a sufficient power supply capability.
【0007】[0007]
【課題を解決するための手段】本発明のTABパッケー
ジでは単一のTABテープでは非常に接続しにくいチッ
プ内部の外部への接続を半田などの溶融する合金によっ
て行なうことが目的である。この場合内側にワイヤボン
ディングの装置を用いて金属細線の先端にボール状の部
分を設け、それをチップ内側に設けたボンディングパッ
ド上に接着し、ボール部分のみを残留させる。この残留
したボール上に内部への給電を目的とした別のベースフ
ィルム上の配線パターンを熱で溶融接続して、十分な給
電能力を与える。SUMMARY OF THE INVENTION It is an object of the TAB package of the present invention to make connection to the inside of a chip, which is very difficult to connect with a single TAB tape, using a melting alloy such as solder. In this case, a ball-shaped portion is provided at the tip of the thin metal wire using a wire bonding apparatus inside, and the ball-shaped portion is adhered to a bonding pad provided inside the chip, leaving only the ball portion. A wiring pattern on another base film intended for power supply to the inside is melt-connected to the remaining ball by heat to provide sufficient power supply capability.
【0008】[0008]
【実施例】次に、本発明について図面を参照して説明す
る。図1は本発明の一実施例の半導体用のTABパッケ
ージの製造方法に関する各工程の断面図である。図1
(a)には、TAB用のバンプを形成した半導体チップ
を示す。半導体チップ1の表面に絶縁膜2を介してチッ
プ周辺に電極パッドを設け、その上に金などの突起形電
極3を形成する。このときバンプの下には、バリアメタ
ル,接着金属層として、Ti−Pd,Ti−Auなどを
形成するのが普通である。このチップの内側には第2の
配線4があり例えば、酸化シリコン膜,窒化シリコン
膜,シリコンポリイミド膜などの絶縁膜5を介し、一部
はスルーホール6を設けて内側の電極パッド7となる金
属層が形成されている。Next, the present invention will be described with reference to the drawings. FIG. 1 is a cross-sectional view of each step relating to a method for manufacturing a TAB package for a semiconductor according to one embodiment of the present invention. FIG.
(A) shows a semiconductor chip on which TAB bumps are formed. An electrode pad is provided around the surface of a semiconductor chip 1 with an insulating film 2 interposed therebetween, and a protruding electrode 3 such as gold is formed thereon. At this time, it is usual to form Ti-Pd, Ti-Au, etc. under the bumps as a barrier metal and an adhesive metal layer. A second wiring 4 is provided inside the chip, for example, through an insulating film 5 such as a silicon oxide film, a silicon nitride film, a silicon polyimide film or the like, and a part thereof is provided with a through hole 6 to become an inner electrode pad 7. A metal layer is formed.
【0009】このように形成された半導体チップに対
し、TABリード8を熱圧着により周囲のバンプと接続
させる。この時TABリードは通常、金またはスズのメ
ッキがほどこされており、ILBの条件は400℃前後
の温度で1秒程度加圧することにより行なわれる。The TAB leads 8 are connected to the surrounding bumps by thermocompression bonding to the semiconductor chip thus formed. At this time, the TAB lead is usually plated with gold or tin, and the condition of ILB is performed by pressing at a temperature of about 400 ° C. for about 1 second.
【0010】次に、ワイヤボンンダーと同様にして内側
のパッドに対し、半田などの金属溶融形のもののボール
を残留させるようにする。この時パッドがAlの場合に
は、間にAgなどの金属層をもうけることが必要である
(図1(c))。Next, similarly to the wire bonder, a metal-melted ball such as solder is left on the inner pad. At this time, when the pad is made of Al, it is necessary to provide a metal layer such as Ag between the pads (FIG. 1C).
【0011】次に、このようにして残した半田ボールの
突起部に対し、前述のものとは別のTABのベースフィ
ルム上にリードパターンを形成したものを熱を加えて半
田ボールを溶融させて接続させたのが、図1(d)とな
る。この半田ボー20は図2のように第1のTABテー
プ上に形成して第2のテープ23と第1のテープを接続
することにより、電気的の導通させることができる。[0011] Next, with respect to the protruding portion of the solder ball left in this way, a lead pattern formed on a TAB base film different from that described above is heated to melt the solder ball. FIG. 1D shows the connection. As shown in FIG. 2, the solder bow 20 is formed on the first TAB tape, and the second tape 23 and the first tape are connected to each other so that electrical conduction can be achieved.
【0012】この時の配線層は35μm厚の銅を用いる
ことができるので、十分な給電効果があるため有効であ
る。At this time, since the wiring layer can be made of copper having a thickness of 35 μm, it is effective because it has a sufficient power supply effect.
【0013】上記に示したのは、ポリイミドフィルムを
二種類用いる方法であるが、他の実施例として半田ボー
ルの接続をもう一つのシリコンチップで行なう方法も可
能である。Although the above is a method using two kinds of polyimide films, a method of connecting solder balls with another silicon chip as another embodiment is also possible.
【0014】[0014]
【発明の効果】以上説明したように本発明はチップ内側
に通常のTABのように内部パターン上にバンプを設け
ると能動素子の破壊させるほどの加圧しないとILBが
できないのであるが、チップ内側は半田による溶融の接
続となるために、デバイスを破壊することなく十分な給
電能力を得られる利点がある。またポリイミドフィルム
をチップ表面をおおうようにするとポリイミドのベース
フィルムによりα線の防止効果もある。As described above, according to the present invention, if bumps are provided on an internal pattern like a normal TAB inside a chip, ILB cannot be performed unless pressure is applied to break active elements. Has the advantage that a sufficient power supply capability can be obtained without breaking the device because the connection is made by melting with solder. When a polyimide film is coated on the chip surface, the polyimide base film has an effect of preventing α rays.
【0015】また半田としてはなまりすずの64半田が
通常であるがインジウム・鉛など他の合金を用いること
も可能である。The solder is usually 64 tinned tin solder, but other alloys such as indium and lead can be used.
【図1】本発明のTABパッケージ構造の製造方法の各
工程の断面図である。FIG. 1 is a sectional view of each step of a method for manufacturing a TAB package structure according to the present invention.
【図2】本発明の一実施例を示す断面図である。FIG. 2 is a sectional view showing one embodiment of the present invention.
【図3】従来のTABパッケージの断面図である。FIG. 3 is a cross-sectional view of a conventional TAB package.
1,13,28 半導体基板 2,14,5,16 絶縁膜 3,15,29 バンプ 8,17,31 TABリード 10,19,20 半田ボール 7,4,18,12,22 配線層1,13,28 semiconductor substrate 2,14,5,16 insulating film 3,15,29 bump 8,17,31 TAB leads 10,19,20 solder balls 7,4,18, 12, 22 wiring layer
Claims (1)
外部へ信号等を引き出すために形成された第1の絶縁膜
上のチップ周辺のパッド上に設けられた第1の金属によ
る突起形電極と、第2の絶縁膜上にスルーホールを介し
て下部配線に接続されたチップ内側に設けられた電極パ
ッド上に低温溶融金属で作られた金属細線の先端に形成
された球と、前記球を前記電極パッドに接着させて第2
の突起形電極を形成した半導体装置において、周辺の電
極パット上の突起型電極と外部リードは熱圧着法により
接着され、チップ内側の突起形電極と外部リードは、熱
溶融より金属接続されたことを特徴とする半導体装置。1. A protruding electrode made of a first metal provided on a pad around a chip on a first insulating film formed for extracting a signal or the like to the outside from an integrated circuit formed on a semiconductor substrate. A sphere formed at the tip of a thin metal wire made of a low-temperature molten metal on an electrode pad provided on the inside of a chip connected to a lower wiring via a through hole on a second insulating film; Is adhered to the electrode pad to form a second
In the semiconductor device in which the protruding electrodes are formed, the protruding electrodes on the peripheral electrode pads and the external leads are bonded by thermocompression bonding, and the protruding electrodes and the external leads inside the chip are metal-connected by thermal melting. A semiconductor device characterized by the above-mentioned.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP3134521A JP2929764B2 (en) | 1991-06-06 | 1991-06-06 | Semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP3134521A JP2929764B2 (en) | 1991-06-06 | 1991-06-06 | Semiconductor device |
Publications (2)
Publication Number | Publication Date |
---|---|
JPH04359439A JPH04359439A (en) | 1992-12-11 |
JP2929764B2 true JP2929764B2 (en) | 1999-08-03 |
Family
ID=15130273
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP3134521A Expired - Lifetime JP2929764B2 (en) | 1991-06-06 | 1991-06-06 | Semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP2929764B2 (en) |
-
1991
- 1991-06-06 JP JP3134521A patent/JP2929764B2/en not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
JPH04359439A (en) | 1992-12-11 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 19990420 |