JPS6091656A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS6091656A JPS6091656A JP58199369A JP19936983A JPS6091656A JP S6091656 A JPS6091656 A JP S6091656A JP 58199369 A JP58199369 A JP 58199369A JP 19936983 A JP19936983 A JP 19936983A JP S6091656 A JPS6091656 A JP S6091656A
- Authority
- JP
- Japan
- Prior art keywords
- metal
- semiconductor element
- electrode
- substrate
- film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/11—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01013—Aluminum [Al]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01042—Molybdenum [Mo]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01078—Platinum [Pt]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
本発明は半導体素子等の高密度、薄型のパッケージング
の製造方法に関するものである。DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a method for manufacturing high-density, thin packaging for semiconductor devices and the like.
従来例の構成とその問題点
近年、IC,LSI等の半導体素子は各種の家庭電化製
品、産業用機器の分野へ導入されている。2. Description of the Related Art Structures of Conventional Examples and Their Problems In recent years, semiconductor elements such as ICs and LSIs have been introduced into the fields of various home appliances and industrial equipment.
これら家庭電化製品、産業用機器は省資源化、省電力化
のためにあるいは利用範囲を拡大させるだ、16K、小
型化、薄型化のいわゆるボータモル化カ促進されてきて
いる。In order to conserve resources and power, and to expand the scope of use of these household electrical appliances and industrial equipment, the so-called bothamolarization of 16K, smaller size, and thinner products is being promoted.
半導体素子においてもポータプル化に対応するために、
パッケージングの小型化、薄型化が要求されてきている
。拡散工程、電極配線工程の終了したシリコンスライス
は半導体素子単位のチップに切断され、チップの周辺に
設けられたアルば電極端子から外部端子へ電極リードを
取出して取扱いやすくし、また機械的保護のためにパッ
ケージングされる。通常、これら半導体素子のパンケー
ジングにはDXL 、チップキャリヤ、フリソプチツブ
テープキャリヤ方式等が用いられているが、DIL 、
チップキャリヤの如きは半導体素子の電極端子から外部
端子へは25〜35μφのムUまたはA7jの極細線で
一本づつ順次接続するものである。このために、半導体
素子上の電極端子数が増大するにしたがい、接続の箇所
の信頼度は低下するばかりか、外部端子の数もこれにし
たがって一定間隔で増大するだめ、パッケージングの大
きさも増大する。In order to respond to the portupling of semiconductor devices,
There is a growing demand for smaller and thinner packaging. After the diffusion process and electrode wiring process have been completed, the silicon slice is cut into chips for each semiconductor element, and electrode leads are taken out from the aluminum electrode terminals provided around the chip to external terminals for easy handling and for mechanical protection. packaged for. Normally, DXL, chip carrier, frisoptic tape carrier methods, etc. are used for pancaging these semiconductor devices, but DIL,
In a chip carrier or the like, the electrode terminals of the semiconductor element are connected to the external terminals one by one using ultrafine wires of 25 to 35 .mu..phi. or A7j. For this reason, as the number of electrode terminals on a semiconductor device increases, not only does the reliability of the connection points decrease, but the number of external terminals also increases at regular intervals, which also increases the size of the packaging. do.
メモリーやマイクロコンピュータ用のLSI、!:連結
しているIloの如きLSIでは機能数の増大とともに
一電極端子数も60〜100端子と著しるしく増大して
しまい、前述した如く、ノくツケージングの大きさは、
わずか数10afの半導体素子を取扱うのに数10af
と大きくなってしまう。LSI for memory and microcomputers! : In connected LSIs such as Ilo, as the number of functions increases, the number of terminals per electrode increases significantly to 60 to 100 terminals, and as mentioned above, the size of the disconnection is
Several tens of af are required to handle semiconductor elements of only a few tens of af.
It gets bigger.
このことは小型化、薄型化の機器の促進を妨げるもので
あった。This has hindered the promotion of smaller and thinner devices.
一方、接続箇所の信頼性が高く、小型化、薄型化のパッ
ケージングを提供できるものとして、フリップチップテ
ープキャリヤ方式がある。チップキャリヤやテープキャ
リヤ方式による半導体素子のパッケージングは半導体素
子上の電極端子上にバリヤメタルと呼ばれる多層金属膜
を設け、さらに、この多層金属膜上に電気メ・ツキ法に
より金属突起を設ける。フリップチップ方式の場合、金
属突起は半田材で構成されており、前記金属突起と回路
基板上の配線パターンを位置合せし一半田リフローさせ
ることにより一括接合するものである〇一方、フィルム
キャリヤ方式の場合は、一定幅の長尺のポリイミドテー
プ上に金属リード端子を設は一半導体素子の電極端子上
の金属突起とリード端子とを、電極端子数に無関係に同
時に一括接続するものであるoしたがって、両方の方式
においては一本づつ電極端子に極細線を接続する前述の
ワイヤポンディング方式と比較して、接続箇所の信頼度
は高くなり、かつ半導体素子の電極端子に設けられるバ
ンプおよびリード端子の破壊強度が40g以上もあるた
めに半導体素子をバンプ又はリード端子のみで保持でき
る。さらにこのために前記半導体素子上の表面に薄い保
護コートをするのみで機器の実装が可能となり、薄型、
小型化したパッケージングとして利用できる。On the other hand, there is a flip-chip tape carrier method that has high reliability at connection points and can provide packaging that is smaller and thinner. In packaging a semiconductor device using a chip carrier or tape carrier method, a multilayer metal film called a barrier metal is provided on the electrode terminals on the semiconductor device, and metal protrusions are further provided on this multilayer metal film by an electroplating method. In the case of the flip-chip method, the metal protrusions are made of solder material, and the metal protrusions and the wiring pattern on the circuit board are aligned and bonded all at once by reflowing the solder.On the other hand, in the film carrier method In this case, metal lead terminals are placed on a long polyimide tape of a constant width, and the metal protrusions on the electrode terminals of one semiconductor element and the lead terminals are simultaneously connected all at once, regardless of the number of electrode terminals. Therefore, in both methods, the reliability of the connection points is higher than in the wire bonding method described above, in which ultra-fine wires are connected to the electrode terminals one by one. Since the terminal has a breaking strength of 40 g or more, the semiconductor element can be held only with bumps or lead terminals. Furthermore, for this reason, devices can be mounted by simply applying a thin protective coat to the surface of the semiconductor element, making it possible to implement thin,
Can be used as miniaturized packaging.
このようにフリップチップ、テープキャリヤ方式は信頼
性、小型、薄型のパッケージング、さらにテープキャリ
ヤ方式の場合は長尺のテープ状態で取扱うことができる
から、半導体素子を実装する生産現場では操作性が抜群
である等の数々の特徴を有するものである。しかしなが
ら、このフリップチップ、テープキャリヤ方式の問題点
は半導体素子の電極端子上への金属突起物の形成にある
。In this way, flip-chip and tape carrier methods offer reliability, small size, and thin packaging, and in the case of tape carrier methods, they can be handled in the form of long tapes, making them easy to operate at production sites where semiconductor devices are mounted. It has many characteristics such as being outstanding. However, a problem with this flip chip and tape carrier method is the formation of metal protrusions on the electrode terminals of the semiconductor device.
すなわち、小型、薄型化したポータプル化した機器を生
産するのはテレビ、ラジオ、ビデオ等のアセンブリ工場
である。これらアセンブリ工場では機器に組込むだめの
半導体素子を半導体メーカから購入しなければならない
。この時゛に問題になるのが一半導体メーカにおいて、
全ての半導体素子上に金属突起を形成できる実力あるい
は設備を必らずしも有していないという現実がある0せ
っかくの小型化、薄型化のパッケージング技術もアセン
ブリ工場における機器の商品的魅力を発揮することがで
きない。In other words, it is assembly factories for televisions, radios, videos, etc. that produce portable devices that are smaller and thinner. These assembly factories must purchase semiconductor elements from semiconductor manufacturers to be assembled into equipment. The problem at this time is that one semiconductor manufacturer
The reality is that we do not necessarily have the ability or equipment to form metal protrusions on all semiconductor devices.Packaging technology that allows for miniaturization and thinning also increases the product appeal of equipment in assembly factories. unable to perform.
また、仮に半導体メーカで金属突起物を形成することが
できたとしても次のような問題がある。Furthermore, even if a semiconductor manufacturer were able to form metal protrusions, there would be the following problems.
まず従来のフリップチップ、テープキャリヤ方式におけ
る半導体素子上に金属突起物を形成する通常の方法につ
いて第1図でのべる。半導体素子1上の保護膜2によっ
て被覆され、一部が開孔、露出している電極端子3上に
バリヤメタル4を形成させる(第1図a)。First, a conventional method for forming metal protrusions on a semiconductor element in a conventional flip-chip or tape carrier method will be described with reference to FIG. A barrier metal 4 is formed on the electrode terminal 3 which is covered with the protective film 2 on the semiconductor element 1 and is partially opened and exposed (FIG. 1a).
バリヤメタル4はOr −Cu 、 Ti −Pa 、
Ni −Cu等の多層蒸着膜からなり、高真空度中で
連続蒸着して形成するものであって、Or 、Ti 、
)iiの如き材料は電極端子3との接着力をもつ働きを
する。Barrier metal 4 is Or-Cu, Ti-Pa,
It consists of a multi-layered vapor deposited film such as Ni-Cu, which is formed by continuous vapor deposition in a high degree of vacuum, and includes Or, Ti,
) Materials such as ii function to have adhesive strength with the electrode terminal 3.
次に半導体素子1の表面に感光性樹脂を全面に塗布し、
電極端子3上のみを開孔6した感光性樹脂パターン6を
形成させる(第1図b)。多層蒸着膜からなるバリヤメ
タル4をマイナス電極として、電解メッキ処理(例えば
フリップチップ方式では半田材をフィルムキャリヤ方式
ではムU材)すれば、感光性樹脂パターン6の開孔した
領域6のみに第1図Cの如く金属突起子を所望の高さに
形成することができる。Next, a photosensitive resin is applied to the entire surface of the semiconductor element 1,
A photosensitive resin pattern 6 with holes 6 formed only on the electrode terminals 3 is formed (FIG. 1b). By using the barrier metal 4 made of a multilayer vapor deposited film as a negative electrode and performing electrolytic plating (for example, using a solder material in the flip-chip method and a mu-U material in the film carrier method), the first layer is applied only to the area 6 in which the photosensitive resin pattern 6 has holes. As shown in Figure C, the metal protrusions can be formed to a desired height.
次に感光性樹脂パターン6を除去し、新たに、第2の感
光性樹脂を塗布し、金属突起7の周辺のみに第2の感光
性樹脂パターン8を残存させ(第1図d)、第2の感光
性樹脂パターン8をエツチング用マスクとして露出して
いるバリヤメタルを除去し、不用となった第2の感光性
樹脂パターン8も除去すれば第1図eの構造を得ること
ができる。フリップチップ方式の場合は一第1図eの状
態で回路基板上の配線パターンと位置合せし、金属突起
と配線パターンとを半田リフローせしめ接合するもので
ある。Next, the photosensitive resin pattern 6 is removed, and a second photosensitive resin is newly applied, leaving the second photosensitive resin pattern 8 only around the metal protrusion 7 (Fig. 1d). The structure shown in FIG. 1e can be obtained by removing the exposed barrier metal using the second photosensitive resin pattern 8 as an etching mask and also removing the unnecessary second photosensitive resin pattern 8. In the case of the flip-chip method, the wiring pattern is aligned with the wiring pattern on the circuit board in the state shown in FIG.
フィルムキャリヤ方式の場合には、完成した半導体素子
1上の金属突起7に、ポリイミイド樹脂9上に形成した
金属リード10とを重ね合せ、治具11により12のご
とく加圧、加熱すれば両者を接合できる。金属突起Tが
ムU、金属リード1゜がSuメッキ処理されておれば、
加熱、加圧することにより人u −S nの共晶物を形
成し、接合することができる(第1図f)。In the case of the film carrier method, the metal protrusions 7 on the completed semiconductor element 1 are overlaid with the metal leads 10 formed on the polyimide resin 9, and both are bonded by pressing and heating with a jig 11 as shown in 12. Can be joined. If the metal protrusion T is U and the metal lead 1° is Su plated,
By applying heat and pressure, a eutectic of human u-Sn can be formed and bonded (FIG. 1f).
ところがこのような従来の工程では、次のようなことが
問題であった。However, such conventional processes have the following problems.
■ バリヤメタルが多層金属構造であるために、金属膜
相互間の付着力、さらに金属期間でのバリヤ抵抗の発生
に注意する必要がある。すなわち金属膜相互間の付着力
が弱いと金属リード10に外力を加えただけで、金属膜
間で剥離あるいはバリヤメタルと突起との剥離が発生し
、実用に期さない。まだ、同じようにバリヤ抵抗の増大
は半導体素子の本来の電気特性を損なうものである。(2) Since the barrier metal has a multilayer metal structure, it is necessary to pay attention to the adhesion between the metal films and the occurrence of barrier resistance in the metal layer. That is, if the adhesion between the metal films is weak, simply applying an external force to the metal lead 10 will cause separation between the metal films or separation between the barrier metal and the protrusion, making it impractical. However, an increase in barrier resistance similarly impairs the original electrical properties of the semiconductor device.
■ 従来のこのような工程を実施するにあたっては、金
属膜の形成工程、メノキ工程−金属膜のエツチング工程
、フォトエッチ工程と、広範囲の精度の高い工程を必要
とし、その分だけ金属突起を形成中るだめのコストが上
昇するばかりか、歩留り低下をまねいてしまう。■ In order to carry out such a conventional process, a wide range of highly precise processes are required, including a metal film formation process, an agate process - a metal film etching process, and a photoetch process. Not only does this increase the cost of filling, but it also causes a decrease in yield.
■ また、バリヤメタルをエツチングするのにかなりの
危険度の高い薬品を使用するために人体に対しても有害
であり、かつ公害防止にも投資する必要がある。例えば
、Orのエツチングにはフェリンアン化カリウム、カセ
イソーダ溶液を用いるし、TiのエツチングにはHF系
の溶液を使わなければならない。■ Also, since highly dangerous chemicals are used to etch the barrier metal, they are harmful to the human body and require investment in pollution prevention. For example, potassium ferrinanide and caustic soda solutions must be used for etching Or, and HF-based solutions must be used for etching Ti.
■ 第1図fの如くフィルムキャリヤ方式ニおいては一
金属リード10と金属突起7を接合する際に共晶物が発
生し、共晶物が半導体素子1の表面層にも落下し、高温
共晶物であるから保護膜2にクラックを生じせしめ、電
極端子3の保護効果を減少し、信頼度を低下さすもので
あった。■ In the film carrier method as shown in FIG. Since it is a eutectic, it causes cracks in the protective film 2, reducing the protective effect of the electrode terminal 3 and lowering reliability.
発明の目的
本発明は、半導体素子等の電極端子上に金属突起を一括
接合する方法に関し、電極端子上に何らの処理をするこ
となしに一金属突起を一括して接合するものであって、
著しるしく簡便な工程により、確実な接合を、高信頼度
で実現し、かつ実装コストを安価にすることを目的とす
る。OBJECTS OF THE INVENTION The present invention relates to a method for collectively bonding metal protrusions onto electrode terminals of semiconductor devices, etc., and is a method for bonding metal protrusions at once on electrode terminals without performing any treatment on the electrode terminals, the method comprising:
The purpose is to achieve reliable bonding with high reliability through a significantly simple process, and to reduce mounting costs.
発明の構成
本発明は、半導体素子の電極取出し領域上か、もしくは
転写するだめの基板上に形成した金属突起上に接着用有
機薄膜物質を形成しておき、前記半導体素子の電極取出
し領域への前記金属突起の転写、接合を効率よくしかも
確実に実施するものである。Structure of the Invention The present invention provides an adhesive organic thin film material that is formed on an electrode lead-out area of a semiconductor element or on a metal protrusion formed on a substrate to be transferred, and then is applied to the electrode lead-out area of the semiconductor element. The transfer and bonding of the metal protrusions is carried out efficiently and reliably.
実施例の説明
まず、半導体素子の電極取出し領域上に有機薄膜物質を
形成する場合の実施例について説明する。DESCRIPTION OF EMBODIMENTS First, an embodiment in which an organic thin film material is formed on an electrode lead-out region of a semiconductor element will be described.
第2図aにおいて半導体素子1の素子が形成されたシリ
コン基板2上にアルミニウム等で形成される電極取出し
領域3が形成され、少なくとも電極取出し領域3を含む
領域上に有機薄膜物質4が被着される。有機薄膜物質4
は、電極取出し領域3上に薄く例えば数100八〜数μ
mの厚さに形成され、物質4の材料は、ポリイミド系、
エポキシ系、アクリル系あるいはシリフン系の樹脂であ
って、常温もしくは数100℃の温度で若干の接着性を
有する事が望ましい。また有機薄膜物質40半導体素子
上への形成は、浸漬法、スピンナーによる回転塗布法、
スプレィ法あるいは、プラヅマ重合法による堆積法等の
手段が用いられる。In FIG. 2a, an electrode lead-out region 3 made of aluminum or the like is formed on a silicon substrate 2 on which a semiconductor element 1 is formed, and an organic thin film material 4 is deposited on at least a region including the electrode lead-out region 3. be done. Organic thin film material 4
is thinly placed on the electrode extraction area 3, for example, from several hundred to several micrometers.
The material of the substance 4 is polyimide,
It is preferably an epoxy-based, acrylic-based, or silicone-based resin that has some adhesiveness at room temperature or at a temperature of several 100°C. Further, the organic thin film material 40 can be formed on the semiconductor element by dipping method, spin coating method using a spinner,
A method such as a spray method or a deposition method using a plasma polymerization method is used.
第2図すは、電極取出し領域3上の有機薄膜物質4に開
孔部5を形成したもので、後述する金属突起を開孔部6
に押込みかつ接着せんとするもので、より効果的な転写
性を目的とした構造の例である。FIG. 2 shows a hole 5 formed in the organic thin film material 4 on the electrode extraction region 3, and a hole 6 formed on a metal protrusion, which will be described later.
This is an example of a structure aimed at more effective transferability.
次に第2図の構造の半導体素子上に金属突起を転写、接
合する方法について第3図で説明する。Next, a method for transferring and bonding metal protrusions onto the semiconductor element having the structure shown in FIG. 2 will be explained with reference to FIG. 3.
金属突起形成用基板6は、ガラス、セラミック等の絶縁
性基台7上に一メッキ用の導電膜(図示せず)を介して
導電膜上に金属突起8が形成されている。導電膜は、メ
ッキ性が良く、しかも剥離。The metal protrusion forming substrate 6 has metal protrusions 8 formed on an insulating base 7 made of glass, ceramic, etc., with a conductive film for plating (not shown) interposed therebetween. The conductive film has good plating properties and is not peelable.
転写性が良好な材質で構成されるもので、実験の結果、
Pt 、 ITO、SuS 、Mo 、Pd膜等が最適
であった。It is made of a material with good transferability, and as a result of experiments,
Pt, ITO, SuS, Mo, Pd films, etc. were optimal.
加圧、加熱できるツール9に半導体素子1を吸着固定し
、電極取出し領域3と、これと対応する位置に形成され
た、基板6上の金属突起8とを位置合せしく第3図a)
、矢印1oの方向に加圧すれば、金属突起8は、電極取
出し領域3上の有機薄膜物質4を介して電極取出し領域
3上に転写。The semiconductor element 1 is suctioned and fixed to a tool 9 that can be pressurized and heated, and the electrode extraction area 3 and the metal protrusion 8 on the substrate 6 formed at the corresponding position are aligned to align the electrode extraction area 3 and the metal protrusion 8 formed at the corresponding position as shown in FIG. 3a).
, when pressure is applied in the direction of arrow 1o, the metal protrusion 8 is transferred onto the electrode extraction area 3 via the organic thin film material 4 on the electrode extraction area 3.
接合される(第3図b)。are joined (Fig. 3b).
ツール9の加圧、加熱温度は、半導体素子上に形成した
有機薄膜物質4の性質に依存するが、比較的接着性を有
する物質であれば、単に1つの金属突起あたり数g〜数
10gの加圧のみで充分である。まだ、常温状態では接
着性がなく温度を上げることにより接着性を有する物質
であれば、物質が接着性を有する温度まで、ツール9の
温度を上げて加圧すれば良い。The pressure and heating temperature of the tool 9 depend on the properties of the organic thin film material 4 formed on the semiconductor element, but if the material has a relatively adhesive property, the pressure and heating temperature of the tool 9 will simply be several grams to several tens of grams per metal protrusion. Pressurization alone is sufficient. If the substance does not have adhesive properties at room temperature but becomes adhesive when the temperature is increased, the temperature of the tool 9 may be raised to a temperature at which the substance exhibits adhesive properties and pressure may be applied.
次に金属突起を形成した状態の他の例を第4図で説明す
る。この例は有機物質を半導体素子の電極取出し領域で
なく、金属突起の表面に形成するものである。金属突起
を形成するだめの基板6はガラス、セラミック、樹脂等
の絶縁物質7上にメッキ用の導電路膜11が形成され、
SiO2,Si3N4゜ガラス、有機物質膜で形成され
た半永久的メッキ用マスクパターン12が設けられてい
る。基板6上にはメッキ用マスクパターン12を介して
金属突起8が半導体素子の電極取出し領域に対応する位
置に複数個形成され、金属突起8上には前述した有機薄
膜物質4′が設けられている。基板6上の金属突起8を
半導体素子上の電極取出し領域に転写、接合する方法は
、第3図a、bで説明したとまったく同一である。Next, another example of a state in which metal protrusions are formed will be explained with reference to FIG. In this example, the organic material is formed on the surface of the metal protrusion rather than on the electrode extraction area of the semiconductor element. The substrate 6 on which the metal protrusions are formed has a conductive path film 11 for plating formed on an insulating material 7 such as glass, ceramic, or resin.
A semi-permanent plating mask pattern 12 made of SiO2, Si3N4° glass, and an organic material film is provided. A plurality of metal protrusions 8 are formed on the substrate 6 through a plating mask pattern 12 at positions corresponding to the electrode extraction areas of the semiconductor element, and the above-mentioned organic thin film material 4' is provided on the metal protrusions 8. There is. The method of transferring and bonding the metal protrusion 8 on the substrate 6 to the electrode lead-out area on the semiconductor element is exactly the same as that described in FIGS. 3a and 3b.
次に半導体素子上の電極取出し領域上に有機薄膜物質を
介して、金属突起を基板上から剥離、転写した後、フィ
ルムキャリヤのリードおよび回路基板に接合する状態を
第6.第6図で説明する。Next, the metal protrusions are peeled off and transferred from the substrate onto the electrode extraction area on the semiconductor element via the organic thin film material, and then bonded to the leads of the film carrier and the circuit board in the sixth step. This will be explained with reference to FIG.
開化部を有する長尺のポリイミド、エポキシ等のフィル
ム20上にSnメッキまたはムロメッキしたCuリード
21が形成されたフィルムキャリヤのCuリード21と
半導体素子1上の転写、接合して形成した金属突起8と
を位置合せしツール22で加圧、加熱する。この時、C
u1J−ド21と金属突起8とは、Cuリード21がS
nメッキ処理してあればムu*snの合金で、ムUメッ
キ処理してあればムU・ムUの熱圧着で接合される。ま
た半導体素子1の電極取出し領域3のアルミ電極と金属
突起8とはムU・ムEの合金で接合されるが、半導体素
子表面に形成した有機薄膜物質4はツール22の加圧。A metal protrusion 8 formed by transferring and bonding a Cu lead 21 on a semiconductor element 1 to a Cu lead 21 of a film carrier in which a Cu lead 21 plated with Sn or black plated is formed on a long film 20 of polyimide, epoxy, or the like having a dilated portion. and then pressurized and heated with the tool 22. At this time, C
The u1J-dead 21 and the metal protrusion 8 are
If it has been plated with n, it will be bonded with an alloy of mu*sn, and if it has been plated with mu, it will be bonded by thermocompression bonding of mu and mu. Further, the aluminum electrode in the electrode extraction region 3 of the semiconductor element 1 and the metal protrusion 8 are bonded with an alloy of MU and ME, and the organic thin film material 4 formed on the surface of the semiconductor element is pressed by the tool 22.
加熱により、仮に金属突起8と電極取出し領域3間に介
在していたとしても、この間から押し出され、ムU・ム
Eの良好な接続を得る事ができる。この状態を第5図に
示した。By heating, even if the metal protrusion 8 is interposed between the electrode extraction region 3, it is pushed out from between the metal protrusion 8 and the electrode extraction region 3, and a good connection between MU and E can be obtained. This state is shown in FIG.
第6図はガラス、セラミック等の絶縁基板23上に回路
配線パターン24を形成した回路基板25に金属突起8
を転写した半導体素子1を接合する状態を示している。FIG. 6 shows metal protrusions 8 on a circuit board 25 on which a circuit wiring pattern 24 is formed on an insulating substrate 23 made of glass, ceramic, etc.
This shows a state in which the semiconductor element 1 onto which the image is transferred is bonded.
半導体素子1上の金属突起8と回路基板26上の回路配
線パターン24とを位置合せし、ツール22′で加圧、
加熱し、金属突起8と回路配線パターン24とを接合せ
しめる。この時にツール22′に加圧、加熱と同時に超
音波振動を附加する事によって、更に高い接合が得られ
る。The metal protrusions 8 on the semiconductor element 1 and the circuit wiring pattern 24 on the circuit board 26 are aligned, and pressure is applied with the tool 22'.
The metal protrusion 8 and the circuit wiring pattern 24 are bonded together by heating. At this time, by applying ultrasonic vibration to the tool 22' at the same time as pressurizing and heating, even higher bonding can be obtained.
また、有機薄膜物質についてのべれば、半導体素子上の
電極取出し領域へ有機薄膜物質を介して金属突起を転写
接合する時には、単に加圧するかもしくは接着性が低温
度で得られる物質であれば、加圧と同時に低温度を与え
れば良い。Regarding organic thin film materials, when transferring and bonding metal protrusions to the electrode extraction area on a semiconductor element through an organic thin film material, it is possible to simply pressurize or use a material that can obtain adhesive properties at low temperatures. , it is sufficient to apply pressure and low temperature at the same time.
次にフィルムキャリヤのリードもしくは回路基板」二の
回路配線パターンと接合する時には前記転写時の加圧力
および加熱温度よりも高くなるから、前記接合時の温度
で昇華消滅する不接薄膜物質を用いても良い。この場合
、有機薄膜物質が昇華消滅すると同時に、転写時よりも
高い圧力と温度によって、金属突起と半導体素子上の電
極取出し領域とは更に強い接合を得る事になる。Next, when bonding to the leads of the film carrier or the circuit wiring pattern on the circuit board, the pressure and heating temperature will be higher than the pressure and heating temperature during the transfer process, so a non-contact thin film material that sublimates and disappears at the bonding temperature is used. Also good. In this case, at the same time as the organic thin film substance sublimates and disappears, the metal protrusion and the electrode lead-out region on the semiconductor element are bonded even more strongly due to higher pressure and temperature than during transfer.
あるいは−有機薄膜物質が接合時に軟化する物質で構成
されるならば、加熱により流動性が発生し、電極取出し
領域の附近および接合面を完全に覆う事になり、保護膜
の役割もほだす事になる。Alternatively, if the organic thin film material is composed of a material that softens during bonding, it will generate fluidity when heated and will completely cover the vicinity of the electrode extraction area and the bonding surface, and will also play a role as a protective film. become.
発明の効果 ■ 低温度での金属突起の転写ができる。Effect of the invention ■ Metal protrusions can be transferred at low temperatures.
金属突起を半導体素子側へ転写接合する際には、Au−
Alの合金を形成せしめて半導体素子側へ接合すること
が考えられる。この場合、Au−471!の合金を形成
するためには、少なくとも320℃以上の圧力と金属突
起当り30g以上の加圧が必要であり、かつ捷だ半導体
素子側へ転写、接合した金属突起とリードもしくは配線
基板とを接合する際に、再度加圧、加熱(約300℃以
上)を繰り返す必要がある。ところが本発明のであれば
、有機薄膜樹脂が軟化する程度の温度(2oO℃程度以
下)で充分に転写を実施できる。したがって、Au−A
7!の合金を必要以上に形成してしまって強度を低下せ
しめる事がない。また、加圧、加熱の度合が小さいので
一半導体素子に与える衝撃力、熱衝撃も小さくて済むの
で信頼性も高く維持できる。When transferring and bonding metal protrusions to the semiconductor element side, Au-
It is conceivable to form an alloy of Al and bond it to the semiconductor element side. In this case, Au-471! In order to form an alloy, it is necessary to apply a pressure of at least 320°C or more and a pressure of 30 g or more per metal protrusion, and to bond the metal protrusion transferred and bonded to the twisted semiconductor element side and the lead or wiring board. When doing so, it is necessary to repeat pressurization and heating (approximately 300° C. or higher) again. However, according to the present invention, sufficient transfer can be performed at a temperature that softens the organic thin film resin (approximately 200° C. or less). Therefore, Au-A
7! There is no need to form more alloy than necessary and reduce the strength. Further, since the degree of pressurization and heating is small, the impact force and thermal shock applied to one semiconductor element are also small, so reliability can be maintained high.
さらに寸だ、金属突起を形成するだめの基板に対しても
衝撃力、熱衝撃も小さいので、耐久性が増し、実装コス
トを安価にできるものである。Furthermore, since the impact force and thermal shock on the substrate on which the metal protrusions are formed are small, durability is increased and mounting costs can be reduced.
■ 半導体素子上に金属突起を転写接合せしめた後、リ
ードまたは配線基板上に接合する時の温度によって、有
機薄膜樹脂が流動し一半導体素子上の電極取出し領域を
覆うことになり−これが接合面を完全に保護するため、
信頼性を一段と向上せしめる事になる。■ After the metal protrusions are transferred and bonded onto the semiconductor element, the organic thin film resin flows due to the temperature at which it is bonded to the lead or wiring board and covers the electrode extraction area on one semiconductor element - this is the bonding surface. To fully protect the
This will further improve reliability.
第1図(a)〜(e)は、従来の半導体素子上に金属突
起を形成するだめの工程断面図、第1図(f)は従来の
フィルムキャリヤ方式でのリードと金属突起を接続した
断面図、第2図(a) (b)は、本発明に用いる半導
体素子の構成断面図、第3図(−) (blは本発明の
方法により金属突起を転写する工程の断面図、第4図は
本発明の転写用基板の構成断面図、第6図は転写した金
属突起をフィルムキャリヤのリードに接合した状態を示
す断面図、第6図は転写した金属突起を回路基板上に接
合した状態を示す断面図である。
1・・・・・・半導体素子、3・川・電極取出し領域−
4゜4′・・・・・・有機薄膜物質、6・・・・・・基
板、8・・印・金属突起、9・・・・・・ツール、21
・山・・リート、25・・・・・・回路基板。
代理人の氏名 弁理士 中 尾 敏 男 ほか1名第1
図Figures 1(a) to (e) are cross-sectional views of the process of forming metal protrusions on a conventional semiconductor element, and Figure 1(f) is a process cross-sectional view of a conventional film carrier method for connecting leads and metal protrusions. 2(a) and 2(b) are cross-sectional views of the structure of a semiconductor element used in the present invention, and FIG. Figure 4 is a cross-sectional view of the structure of the transfer substrate of the present invention, Figure 6 is a cross-sectional view showing the transferred metal protrusions bonded to the leads of the film carrier, and Figure 6 is the transferred metal protrusions bonded to the circuit board. 1. Semiconductor element, 3. River, electrode extraction area.
4゜4'...Organic thin film substance, 6...Substrate, 8...Mark/Metal protrusion, 9...Tool, 21
・Mountain...Leet, 25...Circuit board. Name of agent: Patent attorney Toshio Nakao and 1 other person No. 1
figure
Claims (2)
電極取出し領域と基板上に形成した金属突起とを圧接せ
しめ、前記基板上の金属突起を剥離し、前記電極取出し
領域に転写、接合する工程と、前記電極取出し領域上の
金属突起とフィルム状の導体リードもしくは回路配線を
有する回路基板のパターンとを接合する工程とを備えた
ことを特徴とする半導体装置の製造方法。(1) An electrode lead-out area on a semiconductor element with an organic thin film material formed on the surface is brought into pressure contact with a metal protrusion formed on a substrate, and the metal protrusion on the substrate is peeled off and transferred and bonded to the electrode lead-out area. and a step of bonding the metal protrusion on the electrode extraction area to a pattern of a circuit board having a film-like conductor lead or circuit wiring.
起と半導体素子上の電極取出し領域とを圧接せしめ、前
記基板上の金属突起を剥離し、前記電極取出し領域に転
写、接合する工程と、前記電極取出し領域上の金属突起
とフィルム状の導体リードもしくは回路配線を有する回
路基板のパターンとを接合する工程とを備えたことを特
徴とする半導体装置の製造方法。(2) A step of bringing the metal protrusions on the substrate on which the organic thin film material is formed into pressure contact with the electrode lead-out areas on the semiconductor element, peeling off the metal protrusions on the substrate, and transferring and bonding them to the electrode lead-out areas. and a step of bonding the metal protrusion on the electrode extraction area to a pattern of a circuit board having a film-like conductor lead or circuit wiring.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP58199369A JPS6091656A (en) | 1983-10-25 | 1983-10-25 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP58199369A JPS6091656A (en) | 1983-10-25 | 1983-10-25 | Manufacture of semiconductor device |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS6091656A true JPS6091656A (en) | 1985-05-23 |
JPS644342B2 JPS644342B2 (en) | 1989-01-25 |
Family
ID=16406607
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP58199369A Granted JPS6091656A (en) | 1983-10-25 | 1983-10-25 | Manufacture of semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6091656A (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6290937A (en) * | 1985-10-17 | 1987-04-25 | Matsushita Electric Ind Co Ltd | Manufacturing semiconductor device |
JPH01146337A (en) * | 1987-12-03 | 1989-06-08 | Matsushita Electric Ind Co Ltd | Assembling method for semiconductor |
US5456003A (en) * | 1992-06-18 | 1995-10-10 | Matsushita Electric Industrial Co., Ltd. | Method for packaging a semiconductor device having projected electrodes |
-
1983
- 1983-10-25 JP JP58199369A patent/JPS6091656A/en active Granted
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6290937A (en) * | 1985-10-17 | 1987-04-25 | Matsushita Electric Ind Co Ltd | Manufacturing semiconductor device |
JPH01146337A (en) * | 1987-12-03 | 1989-06-08 | Matsushita Electric Ind Co Ltd | Assembling method for semiconductor |
US5456003A (en) * | 1992-06-18 | 1995-10-10 | Matsushita Electric Industrial Co., Ltd. | Method for packaging a semiconductor device having projected electrodes |
Also Published As
Publication number | Publication date |
---|---|
JPS644342B2 (en) | 1989-01-25 |
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