JPH0758149A - Method for mounting chip part - Google Patents
Method for mounting chip partInfo
- Publication number
- JPH0758149A JPH0758149A JP5199411A JP19941193A JPH0758149A JP H0758149 A JPH0758149 A JP H0758149A JP 5199411 A JP5199411 A JP 5199411A JP 19941193 A JP19941193 A JP 19941193A JP H0758149 A JPH0758149 A JP H0758149A
- Authority
- JP
- Japan
- Prior art keywords
- optical element
- solder bump
- bumps
- sub
- solder
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
-
- G—PHYSICS
- G02—OPTICS
- G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
- G02B6/00—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings
- G02B6/24—Coupling light guides
- G02B6/42—Coupling light guides with opto-electronic elements
- G02B6/4201—Packages, e.g. shape, construction, internal or external details
- G02B6/4219—Mechanical fixtures for holding or positioning the elements relative to each other in the couplings; Alignment methods for the elements, e.g. measuring or observing methods especially used therefor
- G02B6/4228—Passive alignment, i.e. without a detection of the degree of coupling or the position of the elements
- G02B6/4232—Passive alignment, i.e. without a detection of the degree of coupling or the position of the elements using the surface tension of fluid solder to align the elements, e.g. solder bump techniques
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/12—Passive devices, e.g. 2 terminal devices
- H01L2924/1204—Optical Diode
- H01L2924/12041—LED
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、チップ部品の実装方法
に関し、特に光通信，電送装置に用いられる光素子をリ
フローによりサブ基板に接合する実装方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a mounting method for a chip component, and more particularly to a mounting method for bonding an optical element used in an optical communication or transmission device to a sub-board by reflow.
【０００２】[0002]
【従来の技術】光通信はこれまで主に幹線系の伝送に実
用化されていたが、近年、加入者系伝送や民生機器等へ
の広範な普及の兆しがある。これに応じて加入者向けの
光伝送用モジュールの開発において、小型化，低コスト
化，薄型化が進められている。これらを実現するための
技術として、光伝送用モジュールのパッケージングにお
いて、光素子をサブ基板にフリップチップ接合する方法
が有効である。2. Description of the Related Art Optical communication has hitherto been put to practical use mainly for main line transmission, but in recent years, there are signs that it will be widely spread to subscriber transmission and consumer equipment. Accordingly, in the development of optical transmission modules for subscribers, miniaturization, cost reduction, and thinning are being promoted. As a technique for realizing these, in packaging an optical transmission module, a method of flip-chip bonding an optical element to a sub-board is effective.
【０００３】フリップチップ接合は、素子とサブ基板と
を微小のバンプを介して接合する方法であり、モジュー
ルの小型化が可能である。このフリップチップ接合は、
バンプをリフロー時に溶融したバンプの表面張力に起因
するセルフアライメント効果によって、高精度の接合位
置精度が得られるという特徴がある。Flip-chip bonding is a method of bonding an element and a sub-board via minute bumps, and enables miniaturization of a module. This flip chip bonding is
It is characterized in that a highly accurate bonding position accuracy can be obtained by the self-alignment effect resulting from the surface tension of the bump melted during the reflow.
【０００４】この効果を利用することにより、光素子と
光導波路，光ファイバー等の光部品との光軸の無調整化
が可能であり、モジュールの実装コストの低減、さらに
はモジュールの低コスト化をはかることができる。ま
た、これらの特徴を利用して光素子のフリップチップ実
装が行われている。By utilizing this effect, the optical axes of the optical element and the optical parts such as the optical waveguide and the optical fiber can be made unadjusted, so that the mounting cost of the module and the cost of the module can be reduced. You can measure. Moreover, flip-chip mounting of an optical element is performed by utilizing these characteristics.
【０００５】[0005]
【発明が解決しようとする課題】バンプのセルフアライ
メント効果を利用して光素子の高精度位置決めを行うに
は、セルフアライメントに必要な溶融はんだの表面張力
が十分に得られることが重要である。光素子実装用サブ
基板にバンプを、光素子に電極パッドをそれぞれ設け、
セルフアライメント接合を行う場合、表面張力を得て光
素子を高精度に規定の接合位置に引き寄せるには、溶融
したバンプが光素子側の電極パッドに十分に濡れ広がる
ことが重要である。In order to perform high-precision positioning of an optical element by utilizing the self-alignment effect of bumps, it is important that the surface tension of the molten solder required for self-alignment be sufficiently obtained. Providing bumps on the optical element mounting sub-board and electrode pads on the optical element,
When performing self-alignment bonding, it is important that the melted bumps sufficiently spread on the electrode pad on the optical element side in order to obtain the surface tension and draw the optical element to the specified bonding position with high accuracy.
【０００６】この“濡れ”を確保するには、はんだバン
プの表面に存在する酸化膜を除去または破壊し、光素子
側の電極パッドに新鮮な溶融はんだを接触させる必要が
ある。これに対して、図２に示したように、溶融したは
んだバンプの酸化膜８の除去または破壊が不十分である
と、溶融はんだが電極に濡れ広がらず、セルフアライメ
ント効果が十分に得られない。In order to ensure this "wetting", it is necessary to remove or destroy the oxide film existing on the surface of the solder bump and bring fresh molten solder into contact with the electrode pad on the optical element side. On the other hand, as shown in FIG. 2, when the oxide film 8 of the melted solder bump is not sufficiently removed or destroyed, the melted solder does not spread to the electrodes and the self-alignment effect cannot be sufficiently obtained. .
【０００７】このように接合精度は、はんだバンプの表
面酸化状態に左右されるため、従来の技術では、はんだ
バンプの酸化の度合いが大きい場合には精度が得られな
いという欠点がある。As described above, since the joining accuracy depends on the surface oxidation state of the solder bump, the conventional technique has a drawback that the accuracy cannot be obtained when the degree of oxidation of the solder bump is large.
【０００８】また、このような酸化膜を除去するための
方法として、フラックスを用いる方法も考えられるが、
光素子の実装の場合には、フラックスの活性作用によっ
て長期信頼性が低下するため、光素子のセルフアライメ
ント接合はフラックスレスで行う必要がある。As a method for removing such an oxide film, a method using flux can be considered.
In the case of mounting an optical element, long-term reliability deteriorates due to the activation effect of the flux, and therefore self-alignment bonding of the optical element needs to be performed without flux.
【０００９】さらに、特開平２−２５６２９７号公報に
開示されたように、溶融したはんだバンプに超音波を印
加することによって酸化膜の破壊をはかる方法もある
が、光素子を実装する場合には、超音波によって光素子
が損傷を受けやすいという欠点がある。Further, as disclosed in Japanese Patent Laid-Open No. 2-256297, there is a method of destroying the oxide film by applying ultrasonic waves to the molten solder bumps, but when mounting an optical element However, there is a drawback that optical elements are easily damaged by ultrasonic waves.
【００１０】[0010]
【課題を解決するための手段】本発明は、チップ部品お
よびこのチップ部品を実装するサブ基板の少なくともい
ずれか一方に形成するはんだバンプをリフローにより前
記チップ部品と前記サブ基板とを接合するとともに、前
記はんだバンプのセルフアライメント効果により前記チ
ップ部品を位置決めするチップ部品の実装方法におい
て、前記リフロー時に前記チップ部品に荷重を加えて変
形させ、前記はんだバンプ表面の酸化膜を破壊する工程
を付加することを特徴とする。According to the present invention, a solder bump formed on at least one of a chip component and a sub-board on which the chip component is mounted is reflowed to bond the chip component and the sub-board together. In a chip component mounting method for positioning the chip component by the self-alignment effect of the solder bump, a step of destroying an oxide film on the surface of the solder bump by adding a load to the chip component during the reflow to deform the chip component is added. Is characterized by.
【００１１】[0011]
【作用】リフロー時に光素子に荷重を与えると、はんだ
バンプは変形し、はんだバンプの高さが減少すると同時
に、はんだバンプの表面積が変化する。ここで、はんだ
バンプの高さの減少量と表面積との相関を求めるため
に、図３に示すようなモデルを用いて解析する。When a load is applied to the optical element during reflow, the solder bump is deformed, the height of the solder bump is reduced, and at the same time, the surface area of the solder bump is changed. Here, in order to obtain the correlation between the reduction amount of the solder bump height and the surface area, analysis is performed using a model as shown in FIG.
【００１２】まず、図３に示すように、はんだバンプ形
状は、はんだバンプの表面積が最小となる球を平面で切
りとった形状とすると、はんだバンプの断面プロファイ
ル曲線は次のように仮定できる。First, as shown in FIG. 3, assuming that the solder bump has a shape in which a sphere having the smallest surface area of the solder bump is cut off by a plane, the sectional profile curve of the solder bump can be assumed as follows.
【００１３】 [0013]
【００１４】ここで、ｒは球面の曲率半径、ｂは球面の
中心となる点のｚ座標である。このプロファイルによる
はんだバンプの体積は電極パッド半径をｒp とすると、Here, r is the radius of curvature of the spherical surface, and b is the z coordinate of the point at the center of the spherical surface. If the electrode pad radius is r p , the volume of the solder bump based on this profile is
【００１５】 [0015]
【００１６】と表される。（２），（３）式より、
（１）式で仮定したはんだバンプのプロファイルはＶ，
ｈおよびｒp を用いて、次式のように表せる。It is expressed as From equations (2) and (3),
The solder bump profile assumed in equation (1) is V,
It can be expressed as the following equation using h and r p .
【００１７】 [0017]
【００１８】はんだバンプが光素子側電極パッドに接触
している部分の円の半径ｒc は（４）式にｚ＝ｈを代入
して、次式のように求められる。The radius r c of the circle where the solder bump is in contact with the electrode pad on the optical element side is obtained by the following equation by substituting z = h into the equation (4).
【００１９】 [0019]
【００２０】よって、はんだバンプの表面積は次式によ
り求めることができる。Therefore, the surface area of the solder bump can be obtained by the following equation.
【００２１】 [0021]
【００２２】（６）式において、はんだバンプ体積Ｖを
電極パッド半径ｒp とをそれぞれＶ＝１２３７０００μ
ｍ３，ｒｐ＝７５μｍとしたときの、はんだバンプの高
さｈと表面積Ｓとの相関を求めた解析結果を図４に示
す。この図から判るように、はんだバンプ溶融時に光素
子に荷重を印加し、はんだバンプ高さを減少させること
によって、はんだバンプ表面積は増加する。これによ
り、はんだバンプ表面の酸化膜が分断破壊され、溶融は
んだの新鮮面が拡大するため、溶融はんだが光素子側の
電極パッドに対して十分に濡れるとともに、セルフアラ
イメントに必要な溶融はんだの表面張力が得られる。In the equation (6), the solder bump volume V and the electrode pad radius r p are V = 1237000 μ, respectively.
FIG. 4 shows the analysis result of the correlation between the solder bump height h and the surface area S when m 3 and r p = 75 μm. As can be seen from this figure, a load is applied to the optical element when the solder bumps are melted and the solder bump height is reduced, so that the solder bump surface area is increased. As a result, the oxide film on the solder bump surface is broken and broken, and the fresh surface of the molten solder expands, so that the molten solder sufficiently wets the electrode pad on the optical element side and the surface of the molten solder required for self-alignment. Tension is obtained.
【００２３】従って、高精度なセルフアライメント接合
が実現できる。また、はんだバンプ高さ減少量が大きい
ほど表面積の増加の割合は大きくなり、酸化膜破壊の効
果も大きくなる。Therefore, highly accurate self-alignment bonding can be realized. Further, the larger the reduction amount of the solder bump height, the larger the increase rate of the surface area, and the greater the effect of oxide film destruction.
【００２４】[0024]
【実施例】次に、本発明について図面を参照して説明す
る。なお、本実施例では、チップ部品として、特に光通
信，伝送装置等に用いられる光素子をサブ基板に接合す
る場合を例に挙げて説明する。DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings. In this embodiment, as a chip component, an optical element used particularly in optical communication, a transmission device or the like is bonded to a sub-board, as an example.
【００２５】図１は、本発明の一実施例を実現する光素
子のセルフアライメント接合による工程を示す図であ
り、具体的には面発光型の発光ダイオードチップをＡｕ
Ｓｎ共晶合金はんだバンプを介して実装用のサブ基板に
セルフアライメント接合する工程を示している。FIG. 1 is a diagram showing a process of self-alignment bonding of an optical element for realizing an embodiment of the present invention. Specifically, a surface emitting type light emitting diode chip is Au.
It shows a process of performing self-alignment bonding to a mounting sub-board via Sn eutectic alloy solder bumps.
【００２６】まず、ＡｕＳｎはんだバンプ３をＳｉ製サ
ブ基板１上に設けられたＡｕ電極パッド２上にプレス打
ち抜き法で形成する。プレス打ち抜き法によるバンプの
形成方法は、図５に示すように、微小なポンチ５１とダ
イ５２とを用いてＡｕＳｎ共晶合金箔５３を打ち抜き、
そのままサブ基板１上の所望の位置にＡｕＳｎ打ち抜き
型５４を仮固定する。First, AuSn solder bumps 3 are formed on the Au electrode pads 2 provided on the Si sub-substrate 1 by a press punching method. As shown in FIG. 5, the bump forming method by the press punching method punches the AuSn eutectic alloy foil 53 using a minute punch 51 and a die 52.
The AuSn punching die 54 is temporarily fixed at a desired position on the sub-board 1 as it is.
【００２７】次に、これにフラックス５５を塗布し、加
熱ステージ６を用いてＡｕＳｎ共晶合金の融点である２
８０℃よりも高く３００℃程度にまで加熱し、ウェット
バック、すなわちＡｕＳｎ打ち抜き片５４を電極バッド
２上で溶融することによってＡｕＳｎはんだバンプ３を
形成する。Next, flux 55 is applied to this, and the melting point of the AuSn eutectic alloy, which is the melting point of the AuSn eutectic alloy, is 2 using the heating stage 6.
The AuSn solder bumps 3 are formed by heating to a temperature of about 300 ° C. higher than 80 ° C. and then wet back, that is, the AuSn punched pieces 54 are melted on the electrode pads 2.
【００２８】ここで、ポンチの直径は１４０μｍ、ダイ
の内径は１５０μｍ、ＡｕＳｎ箔の厚さは７０μｍと
し、電極パッド２は直径１５０μｍとする。この条件に
より、ウェットバック後のＡｕＳｎはんだバンプ３は高
さ約８０μｍとなる。また、ＡｕＳｎはんだバンプの個
数，形成位置，間隔等は接合する発光ダイオードチップ
の寸法や形状に適したものとする。The punch has a diameter of 140 μm, the die has an inner diameter of 150 μm, the AuSn foil has a thickness of 70 μm, and the electrode pad 2 has a diameter of 150 μm. Under these conditions, the height of the AuSn solder bump 3 after wet back is about 80 μm. Further, the number of AuSn solder bumps, formation positions, intervals and the like are suitable for the size and shape of the light emitting diode chip to be joined.
【００２９】次に、図１（ａ）に示すように、ＡｕＳｎ
はんだバンプに発光ダイオードチップ５を仮搭載する。
このとき、仮搭載位置のずれ量は正規の位置から１０μ
ｍ以内とする。これを図１（ｂ）に示すように加熱ステ
ージ６上で加熱し、ＡｕＳｎはんだバンプ３をリフロー
するとともに、図中、上方から加圧治具７を用いて荷重
を加えると、与えた荷重および発光ダイオードチップ５
自身の重量によりＡｕＳｎはんだバンプ３が溶融し、変
形することによりＡｕＳｎはんだバンプ３表面の酸化膜
８が破壊される。これにより光素子側電極パッド４に濡
れ広がる。Next, as shown in FIG. 1A, AuSn
The light emitting diode chip 5 is temporarily mounted on the solder bump.
At this time, the deviation amount of the temporary mounting position is 10 μ from the normal position.
Within m. This is heated on a heating stage 6 as shown in FIG. 1B to reflow the AuSn solder bumps 3 and, when a load is applied from above in the figure using a pressure jig 7, the applied load and Light emitting diode chip 5
Due to its own weight, the AuSn solder bump 3 is melted and deformed, so that the oxide film 8 on the surface of the AuSn solder bump 3 is destroyed. This wets and spreads on the optical element side electrode pad 4.
【００３０】最後に、図１（ｃ）に示すように荷重を除
去すると、溶融したＡｕＳｎはんだバンプ３のセルフア
ライメント作用によって発光ダイオードチップ５が正規
の実装位置に引き寄せられ、図１（ｄ）に示すように高
精度に接合される。Finally, when the load is removed as shown in FIG. 1 (c), the self-alignment action of the melted AuSn solder bumps 3 pulls the light emitting diode chip 5 to the regular mounting position, and as shown in FIG. 1 (d). As shown, it is joined with high precision.
【００３１】なお、以上に述べた本発明の実施例におい
て、バンプの形成方法としてプレス打ち抜き法を用いた
が、蒸着，スパッタリング，メッキ等，他のバンプ形成
方法を用いてもよく、はんだバンプ材料としてＰｂＳｎ
等、ＡｕＳｎ以外の材料、また、基板材料としてＳｉ以
外の材料を用いてもよい。In the above-described embodiments of the present invention, the press punching method is used as the bump forming method. However, other bump forming methods such as vapor deposition, sputtering and plating may be used. As PbSn
For example, a material other than AuSn and a material other than Si may be used as the substrate material.
【００３２】加熱手段としては加熱ステージを用いた
が、赤外線加熱装置等の放射加熱や高温ガスの対流によ
る方法など、他の加熱手段を用いてもよい。また、はん
だバンプ溶融時に加圧ツールを発光ダイオードチップに
溶融させることにより、溶融したはんだが固化するのを
加圧治具を加熱することによって防ぐことができる。Although the heating stage was used as the heating means, other heating means such as radiant heating using an infrared heating device or a method using convection of high temperature gas may be used. Further, by melting the pressure tool into the light emitting diode chip when melting the solder bump, it is possible to prevent the melted solder from solidifying by heating the pressure jig.
【００３３】さらに、加熱された加圧ツールをはんだバ
ンプ溶融のための加熱手段としてもよく、酸化防止のた
めに窒素や他の非酸化性ガス，水素等の還元性ガス雰囲
気、もしくは真空リフロー等を用いてもよい。また、光
素子として発光ダイオードを例に挙げたが、本発明は半
導体レーザやフォトダイオードと光ファイバや光導波路
との光結合にも応用可能である。Further, a heated pressurizing tool may be used as a heating means for melting the solder bumps, and nitrogen or other non-oxidizing gas, reducing gas atmosphere such as hydrogen, or vacuum reflowing may be used to prevent oxidation. May be used. Further, although the light emitting diode is taken as an example of the optical element, the present invention can be applied to optical coupling between a semiconductor laser or a photodiode and an optical fiber or an optical waveguide.
【００３４】[0034]
【発明の効果】以上説明したように本発明は、光素子の
セルフアライメント接合において、はんだバンプに荷重
を加えてはんだバンプ表面の酸化膜を破壊することによ
り、リフロー時に溶融したはんだの光素子に設けた電極
パッドに対する濡れが十分に確保できるため、光素子の
セルフアライメント接合に必要な溶融はんだの表面張力
が得られ、光素子が高精度に位置決めされるという効果
を有する。As described above, according to the present invention, in self-alignment bonding of an optical element, a load is applied to the solder bumps to destroy an oxide film on the surface of the solder bumps, so that an optical element of a solder melted during reflow is formed. Since the provided electrode pad can be sufficiently wetted, the surface tension of the molten solder necessary for self-alignment joining of the optical element can be obtained, and the optical element can be positioned with high accuracy.
【図１】本発明の一実施例を実現する光素子のセルフア
ライメント接合の工程を示す図である。FIG. 1 is a diagram showing a process of self-alignment bonding of an optical element that realizes an embodiment of the present invention.
【図２】従来のセルフアライメント接合において、はん
だバンプ表面の酸化膜破壊が不十分な状態を示す図であ
る。FIG. 2 is a diagram showing a state in which oxide film destruction on a surface of a solder bump is insufficient in conventional self-alignment bonding.
【図３】はんだバンプの変形量とはんだバンプの表面積
との相関を求めるためのモデルを示す図である。FIG. 3 is a diagram showing a model for obtaining a correlation between a deformation amount of a solder bump and a surface area of the solder bump.
【図４】光素子に加える荷重によるはんだバンプの高さ
とはんだバンプの表面積との相関を示す図である。FIG. 4 is a diagram showing the correlation between the height of the solder bump and the surface area of the solder bump due to the load applied to the optical element.
【図５】プレス打ち抜き法によりはんだバンプを形成す
る工程を示す図である。FIG. 5 is a diagram showing a step of forming solder bumps by a press punching method.
１ 光素子実装用サブ基板 ２ サブ基板側電極パッド ３ ＡｕＳｎはんだバンプ ４ 光素子側電極パッド ５ 発光ダイオードチップ ６ 加熱ステージ ７ 加圧治具 ８ 酸化膜 ５１ ポンチ ５２ ダイ ５３ ＡｕＳｎ箔 ５４ ＡｕＳｎ打ち抜き片 ５５ フラックス 1 Sub-Substrate for Mounting Optical Element 2 Sub-electrode Side Electrode Pad 3 AuSn Solder Bump 4 Photo-element Side Electrode Pad 5 Light Emitting Diode Chip 6 Heating Stage 7 Pressing Fixture 8 Oxide Film 51 Punch 52 Die 53 AuSn Foil 54 AuSn Punched Piece 55 flux
───────────────────────────────────────────────────── フロントページの続き (72)発明者 金山 義信 東京都港区芝五丁目７番１号 日本電気株 式会社内 ─────────────────────────────────────────────────── --Continued front page (72) Inventor Yoshinobu Kanayama 5-7-1, Shiba, Minato-ku, Tokyo NEC Corporation
Claims (1)
するサブ基板の少なくともいずれか一方に形成するはん
だバンプをリフローにより前記チップ部品と前記サブ基
板とを接合するとともに、前記はんだバンプのセルフア
ライメント効果により前記チップ部品を位置決めするチ
ップ部品の実装方法において、前記リフロー時に前記チ
ップ部品に荷重を加えて変形させ、前記はんだバンプ表
面の酸化膜を破壊する工程を付加することを特徴とする
チップ部品の実装方法。1. A solder bump formed on at least one of a chip component and a sub-board on which the chip component is mounted is reflowed to bond the chip component and the sub-substrate, and a self-alignment effect of the solder bump is used. In a chip component mounting method for positioning the chip component, a step of adding a load to the chip component during the reflow to deform the chip component and destroying an oxide film on the surface of the solder bump is added. Method.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5199411A JPH0758149A (en) | 1993-08-11 | 1993-08-11 | Method for mounting chip part |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5199411A JPH0758149A (en) | 1993-08-11 | 1993-08-11 | Method for mounting chip part |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0758149A true JPH0758149A (en) | 1995-03-03 |
Family
ID=16407361
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP5199411A Pending JPH0758149A (en) | 1993-08-11 | 1993-08-11 | Method for mounting chip part |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0758149A (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1997002596A1 (en) * | 1995-06-30 | 1997-01-23 | Kabushiki Kaisha Toshiba | Electronic component and method of production thereof |
| JPH1056039A (en) * | 1996-08-08 | 1998-02-24 | Matsushita Electric Ind Co Ltd | Bonding method for work with bump |
| JP2009010430A (en) * | 2008-10-15 | 2009-01-15 | Renesas Technology Corp | Method of mounting semiconductor element |
| JP2011077193A (en) * | 2009-09-29 | 2011-04-14 | Toshiba Corp | Method for manufacturing semiconductor device |
| US8403202B1 (en) * | 2012-03-30 | 2013-03-26 | Hon Hai Precision Industry Co., Ltd. | Method for soldering surface mounting LED to circuit board |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6356922A (en) * | 1986-08-28 | 1988-03-11 | Yokogawa Electric Corp | Mounting method to substrate of ic chip |
| JPH03241755A (en) * | 1990-02-19 | 1991-10-28 | Hitachi Ltd | Manufacture of electronic circuit device |
| JPH03276750A (en) * | 1990-03-27 | 1991-12-06 | Nec Corp | Hybrid element and manufacture thereof |
-
1993
- 1993-08-11 JP JP5199411A patent/JPH0758149A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6356922A (en) * | 1986-08-28 | 1988-03-11 | Yokogawa Electric Corp | Mounting method to substrate of ic chip |
| JPH03241755A (en) * | 1990-02-19 | 1991-10-28 | Hitachi Ltd | Manufacture of electronic circuit device |
| JPH03276750A (en) * | 1990-03-27 | 1991-12-06 | Nec Corp | Hybrid element and manufacture thereof |
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1997002596A1 (en) * | 1995-06-30 | 1997-01-23 | Kabushiki Kaisha Toshiba | Electronic component and method of production thereof |
| US6262513B1 (en) | 1995-06-30 | 2001-07-17 | Kabushiki Kaisha Toshiba | Electronic component and method of production thereof |
| US6628043B2 (en) | 1995-06-30 | 2003-09-30 | Kabushiki Kaisha Toshiba | Electronic component and method of production thereof |
| US6754950B2 (en) | 1995-06-30 | 2004-06-29 | Kabushiki Kaisha Toshiba | Electronic component and method of production thereof |
| JPH1056039A (en) * | 1996-08-08 | 1998-02-24 | Matsushita Electric Ind Co Ltd | Bonding method for work with bump |
| JP2009010430A (en) * | 2008-10-15 | 2009-01-15 | Renesas Technology Corp | Method of mounting semiconductor element |
| JP2011077193A (en) * | 2009-09-29 | 2011-04-14 | Toshiba Corp | Method for manufacturing semiconductor device |
| US8403202B1 (en) * | 2012-03-30 | 2013-03-26 | Hon Hai Precision Industry Co., Ltd. | Method for soldering surface mounting LED to circuit board |
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