JPH08115947A - Bonding structure for semiconductor device - Google Patents
Bonding structure for semiconductor deviceInfo
- Publication number
- JPH08115947A JPH08115947A JP6250373A JP25037394A JPH08115947A JP H08115947 A JPH08115947 A JP H08115947A JP 6250373 A JP6250373 A JP 6250373A JP 25037394 A JP25037394 A JP 25037394A JP H08115947 A JPH08115947 A JP H08115947A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor element
- semiconductor device
- circuit board
- bump
- solder
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は半導体装置に係り、特
に、フリップチップ接続の熱抵抗低減に好適な接合構造
に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a bonding structure suitable for reducing the thermal resistance of flip chip connection.
【０００２】[0002]
【従来の技術】従来の装置は、特開平6−45401号公報に
記載のように半導体素子と回路基板の間を電気的に接続
する半田バンプと低融点ろう材が設けられていた。低融
点ろう材は電気的に接地電位または電源電位に保持され
ていた。これによりクロストークノイズなどが低減され
る効果があった。そして半田バンプと低融点ろう材によ
って熱抵抗の減少をはかっていた。しかし、半田バンプ
と低融点ろう材を絶縁するための空隙を設ける必要があ
った。2. Description of the Related Art A conventional device is provided with a solder bump and a low melting point brazing material for electrically connecting a semiconductor element and a circuit board as described in JP-A-6-45401. The low melting point brazing material was electrically held at the ground potential or the power supply potential. This has the effect of reducing crosstalk noise and the like. The solder bumps and low melting point brazing material were used to reduce the thermal resistance. However, it is necessary to provide a space for insulating the solder bump and the low melting point brazing material.
【０００３】[0003]
【発明が解決しようとする課題】上記従来技術は前述の
ように、空隙があるために熱抵抗が高くなる。このた
め、半導体素子の動作時に、半導体素子の温度が正常動
作温度範囲を超える問題があった。As described above, the above-mentioned conventional technique has a high thermal resistance because of the voids. Therefore, there is a problem that the temperature of the semiconductor element exceeds the normal operating temperature range during the operation of the semiconductor element.
【０００４】本発明の目的は半導体素子と回路基板間の
熱抵抗を減少し、素子の動作時に正常動作温度範囲内に
収めることにある。An object of the present invention is to reduce the thermal resistance between a semiconductor device and a circuit board so that the device operates within a normal operating temperature range during operation.
【０００５】[0005]
【課題を解決するための手段】上記目的はバンプ表面に
絶縁膜を形成し、半導体素子と回路基板間の空隙に導電
性材料をすき間なく充填することによって達成される。The above object can be achieved by forming an insulating film on the surface of a bump and filling a gap between a semiconductor element and a circuit board with a conductive material without any gap.
【０００６】導電性材料の形成方法には、異方性導電材
料の充填やディップ法による低融点半田の形成，鍍金法
によるメタライズなどが考えられる。また、絶縁膜の形
成には酸化炉中に高温放置することにより半田バンプ表
面に厚い酸化膜を形成する方法や、金バンプ表面にＣＶ
Ｄ装置を用いてＳｉＯ2 膜や、Ｓｉ3Ｏ4膜を形成する方
法がある。As a method of forming the conductive material, it is considered that the conductive material is filled with anisotropic conductive material, low melting point solder is formed by the dip method, or metallization is performed by the plating method. For forming the insulating film, a method of forming a thick oxide film on the surface of the solder bump by leaving it in an oxidizing furnace at a high temperature, or a method of forming CV on the surface of the gold bump is used.
There is a method of forming a SiO 2 film or a Si 3 O 4 film using a D device.
【０００７】[0007]
【作用】バンプ周囲に形成した絶縁膜はバンプと充填材
を電気的に絶縁するので、充填材をバンプ周囲の空隙に
すき間なく充填することができる。その結果、半導体素
子と回路基板の間の熱抵抗が改善され、半導体素子の温
度上昇を低減することができる。また、充填材を接地電
位に保持することにより、信号線間に起こっていたクロ
ストークノイズを低減できる。さらに接続部のバンプと
充填材の熱膨張率を整合することにより、接続部に応力
集中が起こりづらくなり接続信頼性が増加する。同様に
接続部分が密閉されているために簡易な封止構造だけで
済み、低コストで作成できる。Since the insulating film formed around the bumps electrically insulates the bumps from the filling material, the filling material can be filled into the voids around the bumps without any gap. As a result, the thermal resistance between the semiconductor element and the circuit board is improved, and the temperature rise of the semiconductor element can be reduced. Further, by holding the filling material at the ground potential, it is possible to reduce crosstalk noise that has occurred between the signal lines. Furthermore, by matching the thermal expansion coefficients of the bumps of the connection portion and the filler, stress concentration is less likely to occur at the connection portion, and the connection reliability is increased. Similarly, since the connecting portion is hermetically sealed, only a simple sealing structure is required and it can be manufactured at low cost.
【０００８】[0008]
【実施例】以下、本発明の第１の実施例を図１および図
２より説明する。図１は本発明の第１の実施例の全体図
である。図２は図１の要部拡大図である。半導体装置10
1は半導体素子１１と，半導体素子１１を搭載する回路
基板１５と，半導体素子１１と回路基板１５の対向する
電極パッド１２と，電極パッド１２の間に形成された半
田バンプ１３と，半導体素子１１と回路基板１５の対抗
する電極パッド１２を囲むように配置されたメタライズ
１６と，メタライズ１６の間に充填した低融点金属１７
と，低融点金属１７と半田バンプ１３を電気的に絶縁す
る絶縁膜１４から構成されている。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A first embodiment of the present invention will be described below with reference to FIGS. FIG. 1 is an overall view of the first embodiment of the present invention. FIG. 2 is an enlarged view of a main part of FIG. Semiconductor device 10
Reference numeral 1 denotes a semiconductor element 11, a circuit board 15 on which the semiconductor element 11 is mounted, electrode pads 12 facing each other between the semiconductor element 11 and the circuit board 15, solder bumps 13 formed between the electrode pads 12, and the semiconductor element 11 And the metallization 16 arranged so as to surround the opposing electrode pad 12 of the circuit board 15, and the low melting point metal 17 filled between the metallization 16.
And an insulating film 14 for electrically insulating the low melting point metal 17 and the solder bump 13.
【０００９】低融点金属１７はメタライズ１６と固着す
ることですき間に保持されている。半田バンプ１３周囲
に形成した絶縁膜１４はバンプ１３と充填材１７を電気
的に絶縁するので、充填材１７を半田バンプ１３周囲の
空隙にすき間なく充填することができる。その結果、半
導体素子１１と回路基板１５の間の熱抵抗が改善され、
半導体素子１１の温度上昇を低減することができる。The low melting point metal 17 is held in the gap by being fixed to the metallization 16. Since the insulating film 14 formed around the solder bumps 13 electrically insulates the bumps 13 and the filling material 17, the filling material 17 can be filled in the voids around the solder bumps 13 without any gap. As a result, the thermal resistance between the semiconductor element 11 and the circuit board 15 is improved,
The temperature rise of the semiconductor element 11 can be reduced.
【００１０】さらに充填材１７は導電性材料を用いてい
るため、接地電位に保持することができ、バンプ１３等
の信号線間に発生していたクロストークノイズを低減す
る効果がある。また導電性材料を電源電位に保持するこ
とによっても効果を得ることができる。またバンプ１
３，絶縁膜１４，低融点金属１７の接続部分の熱膨張係
数がほぼ同一であるため、それぞれの部位に応力が加わ
ることがない。このことから接続信頼性では、従来起っ
ていた半田のクラックが発生しないため接続信頼性が増
した。さらに充填材が接続部分を密封していることによ
り、半導体装置１０１は簡易な封止で長期間の接続信頼
性を保つことができる。Further, since the filling material 17 is made of a conductive material, it can be held at the ground potential, and has an effect of reducing crosstalk noise generated between signal lines such as the bumps 13. The effect can also be obtained by holding the conductive material at the power supply potential. Bump 1
3, the insulating film 14 and the low melting point metal 17 have substantially the same thermal expansion coefficient at the connection portion, and therefore no stress is applied to the respective portions. As a result, in terms of connection reliability, the solder cracks that have conventionally occurred do not occur, so that the connection reliability is increased. Further, since the filler seals the connection portion, the semiconductor device 101 can maintain the connection reliability for a long period of time with simple sealing.
【００１１】次に半導体装置１０１の作成プロセスを述
べる。まず、半導体素子１１と回路基板１５の両方の電
極パッド１２上に半田バンプ１３を形成する。電極パッ
ド１２は半田バンプ１３の形成を容易にするために、表
面に金を形成し、金の下に半田をバリアするためのニッ
ケルを形成し、その下に下地の回路基板１５や半導体素
子１１との被着性を高めるためのチタンが形成してあ
る。Next, a manufacturing process of the semiconductor device 101 will be described. First, the solder bumps 13 are formed on the electrode pads 12 of both the semiconductor element 11 and the circuit board 15. In order to facilitate the formation of the solder bumps 13, the electrode pads 12 have gold formed on the surface thereof, and nickel for barriering the solder is formed under the gold, and the underlying circuit board 15 and the semiconductor element 11 are formed under the gold. Titanium is formed to enhance the adherence with the.
【００１２】次に半導体素子１１と回路基板１５上の対
向した電極パッド１２同士を位置合わせする。その後、
半導体素子１１と回路基板１５は、電極パッド１２上に
形成された半田バンプ１３を、フラックスを用いて溶融
することにより半田バンプ１３のセルフアライメントに
より、精度良く位置合わせが行われ接続される。接続後
にフラックスは有機溶剤によって洗浄，除去され、残渣
等が無いようにする。Next, the semiconductor element 11 and the electrode pads 12 on the circuit board 15 facing each other are aligned with each other. afterwards,
The semiconductor element 11 and the circuit board 15 are accurately aligned and connected by self-alignment of the solder bumps 13 formed by melting the solder bumps 13 formed on the electrode pads 12 using flux. After connection, the flux is washed and removed with an organic solvent so that there is no residue.
【００１３】フラックスの洗浄後、半導体素子１１と回
路基板１５を接続している半田バンプ１３は酸素雰囲気
の電気炉を使用して周囲に酸化膜１４を適当な厚さに形
成する。酸化膜１４は４００℃の酸素雰囲気中に２時
間、放置することによって、約０.１μｍ の厚さに形成
した。After cleaning the flux, the solder bumps 13 connecting the semiconductor element 11 and the circuit board 15 are formed with an oxide film 14 at an appropriate thickness on the periphery thereof using an electric furnace in an oxygen atmosphere. The oxide film 14 was formed in a thickness of about 0.1 μm by leaving it in an oxygen atmosphere at 400 ° C. for 2 hours.
【００１４】酸化膜１４を形成した後、半田バンプ１３
の融点より低い低融点半田を溶かした半田浴に投入し、
半導体素子１１と回路基板１５の対向したメタライズ１
６の間に低融点金属１７を形成する。メタライズ１６は
低融点金属１７である半田が濡れやすいように表面に金
が形成されており、中間層にバリア金属としてのニッケ
ル，下地との接続を良好にするためにチタンを用いて形
成してある。After forming the oxide film 14, the solder bumps 13 are formed.
Pour into a solder bath in which low melting point solder lower than
Metallization 1 in which semiconductor element 11 and circuit board 15 face each other
A low melting point metal 17 is formed between 6 and 6. Gold is formed on the surface of the metallization 16 so that the solder, which is the low melting point metal 17, can be easily wetted, and nickel is used as a barrier metal in the intermediate layer, and titanium is used to make a good connection with the base. is there.
【００１５】このようにして形成した半導体装置１０１
は半導体素子１１と回路基板１５の間の熱伝導経路が大
きくなり、熱伝導率の高い材料を用いることにより熱抵
抗が減少した。さらに低融点金属１７を接地電位に保持
することにより信号線から発生するクロストークノイズ
を減少させることができる。前述のように、低融点金属
１７には低融点の半田を用いたが、異方導電材料の充
填、または鍍金による金属を析出，堆積することによっ
ても同様の効果が得られる。The semiconductor device 101 thus formed
Has a large heat conduction path between the semiconductor element 11 and the circuit board 15, and the heat resistance is reduced by using a material having high heat conductivity. Further, by holding the low melting point metal 17 at the ground potential, the crosstalk noise generated from the signal line can be reduced. As described above, the low-melting-point solder is used as the low-melting-point metal 17, but the same effect can be obtained by filling the anisotropic conductive material or depositing and depositing the metal by plating.
【００１６】図３に図１のＡ−Ａ断面図を示す。回路基
板１５上には対向電極１２（図示せず）があり、対向電
極１２上に半田バンプ１３が接続されている。半田バン
プ１３はその上面に半導体素子１１（図示せず）を接続
している。半田バンプ１３の周囲は絶縁層である酸化膜
１４によって周囲と絶縁されている。酸化膜１４の周囲
は低融点金属１７がすき間無く充填されている。この充
填された低融点金属１７により、半導体素子１１（図示
せず）と回路基板１５間の熱抵抗を減少する効果があ
り、さらに外低融点金属１７を接地電位に保持すること
により半田バンプ１３等の信号線から出るクロストーク
ノイズを減少する効果がある。FIG. 3 is a sectional view taken along line AA of FIG. A counter electrode 12 (not shown) is provided on the circuit board 15, and solder bumps 13 are connected to the counter electrode 12. The semiconductor element 11 (not shown) is connected to the upper surface of the solder bump 13. The periphery of the solder bump 13 is insulated from the periphery by an oxide film 14 which is an insulating layer. The periphery of the oxide film 14 is filled with a low melting point metal 17 without any gap. The filled low melting point metal 17 has an effect of reducing the thermal resistance between the semiconductor element 11 (not shown) and the circuit board 15. Further, by holding the outer low melting point metal 17 at the ground potential, the solder bump 13 This has the effect of reducing crosstalk noise generated from signal lines such as.
【００１７】次に本発明の第２の実施例を図４および図
５を用いて説明する。図４は本発明の第２の実施例の全
体図である。図５は図４の要部の拡大図である。半導体
装置１０２は半導体素子１１と，半導体素子１１を搭載
する回路基板１５と，半導体素子１１と回路基板１５の
対向する電極パッド１２と，電極パッド１２の間に形成
された金バンプ１８と，金バンプ１８を周囲と絶縁する
絶縁膜２０と，絶縁膜２０上に形成されたメタライズ層
１９と，メタライズ層１９上に形成した低融点金属１７
から構成されている。Next, a second embodiment of the present invention will be described with reference to FIGS. FIG. 4 is an overall view of the second embodiment of the present invention. FIG. 5 is an enlarged view of the main part of FIG. The semiconductor device 102 includes a semiconductor element 11, a circuit board 15 on which the semiconductor element 11 is mounted, electrode pads 12 facing the semiconductor element 11 and the circuit board 15, gold bumps 18 formed between the electrode pads 12, and a gold bump 18. An insulating film 20 that insulates the bumps 18 from the surroundings, a metallization layer 19 formed on the insulating film 20, and a low melting point metal 17 formed on the metallization layer 19.
It consists of
【００１８】金バンプ１８の周囲に形成する絶縁膜２０
はＣＶＤ装置により形成されるため、金バンプ１８の周
囲だけでなく、半導体素子１１および回路基板１５の表
面にも同様に被着する。絶縁膜２０の表面にはメタライ
ズ層１９が形成される。これは半導体素子１１と回路基
板１５の間に充填材１７を形成する際に形成し易くする
ためである。Insulating film 20 formed around gold bumps 18
Is formed by a CVD apparatus, so that not only the gold bumps 18 but also the surfaces of the semiconductor elements 11 and the circuit board 15 are similarly deposited. A metallization layer 19 is formed on the surface of the insulating film 20. This is to facilitate the formation of the filling material 17 between the semiconductor element 11 and the circuit board 15.
【００１９】このようにして形成された半導体装置２０
１は半導体素子１１と回路基板１５の間の熱抵抗が低減
されており、より高速で発熱量の大きい半導体素子１１
を使用することができる。また第１の実施例と同様に充
填材２０を接地電位に保持することにより、信号線から
発生するクロストークノイズを減少させる効果がある。
また機械的には接続部分に従来起こっていた応力の集中
の問題は充填材によってバンプが保持されていることに
より、応力の緩和がなされた。さらに充填材が接続部分
を密封していることにより、半導体装置は簡易な封止で
長期間の接続信頼性を保つことができる。The semiconductor device 20 formed in this way
No. 1 has a reduced thermal resistance between the semiconductor element 11 and the circuit board 15, and has a higher speed and a larger heat generation amount.
Can be used. Further, as in the first embodiment, holding the filler 20 at the ground potential has an effect of reducing crosstalk noise generated from the signal line.
Further, mechanically, the problem of stress concentration that has conventionally occurred at the connecting portion was relieved by the fact that the bumps were held by the filler. Further, since the filler seals the connection portion, the semiconductor device can maintain the connection reliability for a long period of time with simple sealing.
【００２０】次に第２の実施例の半導体装置１０２を形
成するプロセスを述べる。半導体素子１１または回路基
板１５上の電極パッド１２上に金めっきすることによ
り、金バンプ１８を形成する。金バンプ１８を形成した
後、電極パッド１２同士の位置合わせを行い金接合を行
う。または、予め半導体素子１１上の電極パッド１２と
回路基板１５上の電極パッド１２の位置合わせを行い、
金の選択めっきを行い金バンプ１８を形成する。金バン
プ１８は上下方向から次第に形成されてきて中間部分で
自動的に接合される。Next, a process of forming the semiconductor device 102 of the second embodiment will be described. Gold bumps 18 are formed by gold plating on the electrode pads 12 on the semiconductor element 11 or the circuit board 15. After forming the gold bumps 18, the electrode pads 12 are aligned with each other and gold bonding is performed. Alternatively, the electrode pads 12 on the semiconductor element 11 and the electrode pads 12 on the circuit board 15 are aligned in advance,
Selective gold plating is performed to form gold bumps 18. The gold bumps 18 are gradually formed in the vertical direction and are automatically joined at the intermediate portion.
【００２１】このようにして接続が終わった半導体素子
１１と回路基板１５を接合している金バンプ１８の周囲
に絶縁膜２０を形成するために、ＣＶＤ装置に投入し、
450℃にて酸化膜ＳｉＯ2 を形成する。ＣＶＤ装置によ
って作成される酸化膜は半導体素子１１および回路基板
１５の裏面にも被着する。余分な部分の酸化膜はマスク
をしてからＣＶＤ装置で被着する、または酸化膜のエッ
チングによって不必要な部分の酸化膜を取り去る。In order to form the insulating film 20 around the gold bumps 18 joining the semiconductor element 11 and the circuit board 15 which have been connected in this way, they are put into a CVD apparatus,
An oxide film SiO 2 is formed at 450 ° C. The oxide film formed by the CVD device is also deposited on the back surfaces of the semiconductor element 11 and the circuit board 15. The oxide film in the excess portion is masked and then deposited by a CVD apparatus, or the oxide film in the unnecessary portion is removed by etching the oxide film.
【００２２】次に酸化膜ＳｉＯ2 上に無電解鍍金を用い
てメタライズ１９を形成する。不必要な部分には酸化膜
の形成時に使用したマスクを用いて鍍金膜形成後にマス
クを取り去る。次に低融点半田を溶融した半田浴に半導
体装置２０１を投入し、低融点半田によって半導体素子
１１と回路基板１５の空隙に充填した。前述のプロセス
中で、バンプ１８には金を用いたが高融点金属で接続し
易い金属ならば同様のプロセスを用いて形成することが
可能である。また低融点金属１７の形成には半田を用い
たが、異方導電材料の充填、または鍍金による金属を析
出することによっても同様の効果が得られる。また絶縁
膜には酸化膜ＳｉＯ2 を使用したが、同様に絶縁性があ
る窒化膜Ｓｉ3Ｎ4の形成によっても熱抵抗やクロストー
クノイズに対して同様の効果が得られる。Next, a metallization 19 is formed on the oxide film SiO 2 by using electroless plating. The unnecessary portion is removed by using the mask used for forming the oxide film after forming the plating film. Next, the semiconductor device 201 was put into a solder bath in which the low melting point solder was melted, and the gap between the semiconductor element 11 and the circuit board 15 was filled with the low melting point solder. In the above-described process, the bump 18 is made of gold, but a metal having a high melting point that facilitates connection can be used to form the bump 18. Although solder is used to form the low melting point metal 17, the same effect can be obtained by filling the anisotropic conductive material or depositing the metal by plating. Further, although the oxide film SiO 2 is used as the insulating film, the same effect can be obtained with respect to the thermal resistance and the crosstalk noise by forming the nitride film Si 3 N 4 which also has an insulating property.
【００２３】図６に以上のように作成した半導体装置の
熱抵抗を比較した結果を示す。図６はチップ面積Ａ０と
接続面積の合計Ａ１の比を横軸に、熱抵抗の比を縦軸に
表示した。実施例に示す半導体装置の熱抵抗を１とした
とき半導体素子の接続面積の比は９５％であった。従来
の接続方法では接続面積比が１２％となり、熱抵抗は本
実施例と比較して８倍あった。このことから本実施例の
接続方法では従来の半導体素子より８倍の発熱量を持つ
半導体素子を使用することが可能になる。FIG. 6 shows the result of comparison of the thermal resistances of the semiconductor devices manufactured as described above. In FIG. 6, the horizontal axis represents the ratio of the chip area A0 to the total connection area A1, and the vertical axis represents the thermal resistance ratio. When the thermal resistance of the semiconductor device shown in the example was set to 1, the ratio of the connection areas of the semiconductor elements was 95%. In the conventional connection method, the connection area ratio was 12%, and the thermal resistance was 8 times that of this example. For this reason, the connection method of the present embodiment makes it possible to use a semiconductor element having a heat generation amount eight times that of the conventional semiconductor element.
【００２４】[0024]
【発明の効果】接続面積を増加させたことにより、従来
と比較して１／８の熱抵抗にすることができた。By increasing the connection area, the thermal resistance can be reduced to 1/8 of that of the conventional one.
【００２５】低融点金属部を接地電位にすることにより
従来発生していたクロストークノイズを減少することが
できた。By setting the low melting point metal portion to the ground potential, the crosstalk noise that has been conventionally generated can be reduced.
【００２６】熱膨張係数の近い材料を充填材に用いるこ
とにより、応力の集中が起きづらくなり接続信頼性が増
した。By using a material having a thermal expansion coefficient close to that of the filler, stress concentration is less likely to occur and the connection reliability is increased.
【００２７】充填材を入れた半導体装置は接続部分が密
封されていることになるため、簡易な封止構造で長期間
の信頼性が保たれる。Since the connecting portion of the semiconductor device containing the filler is hermetically sealed, the reliability is maintained for a long time with a simple sealing structure.
【図１】本発明第１の実施例の断面図。FIG. 1 is a sectional view of a first embodiment of the present invention.
【図２】第１の実施例である図１の要部の拡大図。FIG. 2 is an enlarged view of a main part of FIG. 1 which is a first embodiment.
【図３】本発明の第１の実施例の図１におけるＡ−Ａ断
面図。FIG. 3 is a sectional view taken along line AA in FIG. 1 of the first embodiment of the present invention.
【図４】本発明第２の実施例の断面図。FIG. 4 is a sectional view of a second embodiment of the present invention.
【図５】第２の実施例である図４の要部の拡大図。FIG. 5 is an enlarged view of a main part of FIG. 4 which is a second embodiment.
【図６】接続面積比と熱抵抗比の関係のグラフ。FIG. 6 is a graph showing the relationship between the connection area ratio and the thermal resistance ratio.
１１…半導体素子、１２…電極パッド、１３…半田バン
プ、１４…酸化膜、１５…回路基板、１６…メタライ
ズ、１７…低融点金属。11 ... Semiconductor element, 12 ... Electrode pad, 13 ... Solder bump, 14 ... Oxide film, 15 ... Circuit board, 16 ... Metallization, 17 ... Low melting point metal.
Claims (8)
る回路基板と，前記基板と前記半導体素子の対向する電
極端子間に形成されたバンプと，前記バンプ周囲の空隙
部を充填する充填材からなる半導体装置において、前記
充填材は導電性材料からなり、前記バンプの表面に絶縁
膜が形成されており、前記バンプと前記充填材は前記絶
縁膜により電気的に絶縁されていることを特徴とする半
導体装置。1. A semiconductor element, a circuit board on which the semiconductor element is mounted, bumps formed between opposing electrode terminals of the board and the semiconductor element, and a filling material for filling a void portion around the bump. In the semiconductor device including, the filling material is made of a conductive material, an insulating film is formed on the surface of the bump, and the bump and the filling material are electrically insulated by the insulating film. Semiconductor device.
らなる半導体装置。2. A semiconductor device in which the filling material according to claim 1 is made of a metal material.
または電解鍍金で形成される半導体装置。3. A semiconductor device in which the filling material according to claim 2 is formed by electroless plating or electrolytic plating.
漬されることにより形成されている半導体装置。4. A semiconductor device formed by immersing the filling material according to claim 2 in a solder bath.
絶縁膜が酸素雰囲気中に保持されることによって形成さ
れた酸化膜からなる半導体装置。5. A semiconductor device according to claim 1, 2, 3, or 4, wherein the insulating film is an oxide film formed by being kept in an oxygen atmosphere.
形成されている半導体装置。6. A semiconductor device in which the bump according to claim 5 is formed of solder.
絶縁膜がＣＶＤ装置で形成される半導体装置。7. A semiconductor device according to claim 1, 2, 3 or 4, wherein the insulating film is formed by a CVD device.
れる半導体装置。8. A semiconductor device in which the bump according to claim 7 is formed of gold.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6250373A JPH08115947A (en) | 1994-10-17 | 1994-10-17 | Bonding structure for semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6250373A JPH08115947A (en) | 1994-10-17 | 1994-10-17 | Bonding structure for semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH08115947A true JPH08115947A (en) | 1996-05-07 |
Family
ID=17206960
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP6250373A Pending JPH08115947A (en) | 1994-10-17 | 1994-10-17 | Bonding structure for semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH08115947A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPWO2008015731A1 (en) * | 2006-07-31 | 2009-12-17 | 富士通株式会社 | Soldering method and apparatus for mounting components on a printed wiring board |
| US9412712B2 (en) | 2014-09-22 | 2016-08-09 | Samsung Electronics, Co., Ltd | Semiconductor package and method of manufacturing the same |
-
1994
- 1994-10-17 JP JP6250373A patent/JPH08115947A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPWO2008015731A1 (en) * | 2006-07-31 | 2009-12-17 | 富士通株式会社 | Soldering method and apparatus for mounting components on a printed wiring board |
| JP5071386B2 (en) * | 2006-07-31 | 2012-11-14 | 富士通株式会社 | Soldering method and apparatus for mounting components on a printed wiring board |
| US9412712B2 (en) | 2014-09-22 | 2016-08-09 | Samsung Electronics, Co., Ltd | Semiconductor package and method of manufacturing the same |
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