JP2770041B2 - Bump forming method and semiconductor element connecting method - Google Patents

Bump forming method and semiconductor element connecting method

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Publication number
JP2770041B2
JP2770041B2 JP2730089A JP2730089A JP2770041B2 JP 2770041 B2 JP2770041 B2 JP 2770041B2 JP 2730089 A JP2730089 A JP 2730089A JP 2730089 A JP2730089 A JP 2730089A JP 2770041 B2 JP2770041 B2 JP 2770041B2
Authority
JP
Japan
Prior art keywords
semiconductor element
bump
superelastic
bumps
electrode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2730089A
Other languages
Japanese (ja)
Other versions
JPH02206125A (en
Inventor
恭秀 大野
広明 大塚
芳雄 大関
敬介 渡辺
孝史 金森
泰男 井口
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Steel Corp
Oki Electric Industry Co Ltd
Original Assignee
Nippon Steel Corp
Oki Electric Industry Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Steel Corp, Oki Electric Industry Co Ltd filed Critical Nippon Steel Corp
Priority to JP2730089A priority Critical patent/JP2770041B2/en
Publication of JPH02206125A publication Critical patent/JPH02206125A/en
Application granted granted Critical
Publication of JP2770041B2 publication Critical patent/JP2770041B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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Description

【発明の詳細な説明】 [産業上の利用分野] 本発明は、半導体チップに代表される半導体素子と実
装基板の接続方法に関するものである。
Description: TECHNICAL FIELD The present invention relates to a method for connecting a semiconductor element represented by a semiconductor chip to a mounting board.

[従来の技術] 従来の半導体素子のバンプによる接続方法の概略構造
を第4図に示す。1は半導体素子、2は実装基板、3は
半導体素子または実装基板に構成されたはんだバンプ、
4は半導体素子1と実装基板2の電極であり、A−A′
は半導体素子の中心を示している。
[Prior Art] FIG. 4 shows a schematic structure of a conventional method of connecting a semiconductor element by bumps. 1 is a semiconductor element, 2 is a mounting board, 3 is a semiconductor element or a solder bump formed on the mounting board,
Reference numeral 4 denotes electrodes of the semiconductor element 1 and the mounting substrate 2, which are AA '.
Indicates the center of the semiconductor element.

接続は、はんだバンプ3を加熱溶融することにより行
われ、一括接続であるため、ワイヤー接続方法に比べて
作業性に優れ、またワイヤ接続及びTAB(Tape Automate
d Bonding)方法の如く、電極配置がICチップの周辺に
限定されるものと比較して、大幅に接続端子数を増やす
ことができるという特徴を持っている。
The connection is performed by heating and melting the solder bumps 3 and is a batch connection, so that the workability is superior to the wire connection method, and the wire connection and TAB (Tape Automate) are performed.
It has the feature that the number of connection terminals can be greatly increased as compared with the case where the electrode arrangement is limited to the periphery of the IC chip as in the d bonding method.

しかしながら、この方法では、温度変化により、第5
図に示すような半導体素子1と実装基板2との熱膨張差
による寸法ずれBが起こりはんだバンプ3にせん断歪が
生じ、接続信頼性が低下する。せん断歪は、はんだバン
プ3と半導体素子1の中心との距離の増加とともに増大
するため、はんだバンプ3の許容し得るせん断歪量から
はんだバンプ3を配置できる領域が制限され多端子化な
らびに大面積の半導体素子への適用が困難であった。
However, in this method, due to the temperature change, the fifth
As shown in the figure, a dimensional deviation B due to a difference in thermal expansion between the semiconductor element 1 and the mounting substrate 2 occurs, causing a shear strain in the solder bump 3 and lowering the connection reliability. Since the shear strain increases with an increase in the distance between the solder bump 3 and the center of the semiconductor element 1, the area where the solder bump 3 can be arranged is limited due to the allowable shear strain of the solder bump 3, so that the number of terminals is increased and the area is increased. Is difficult to apply to semiconductor devices.

このはんだバンプのせん断歪を低減させる手段とし
て、半導体素子と熱膨張係数の近い配線基板を用いる方
法が考えられるが、実装基板材料が限定されてしまうた
め、熱膨張係数の異なる材質の半導体素子を混載するこ
とができない等の欠点がある。一方はんだバンプの高さ
を高くしてせん断歪を低減させる手段が提案されてい
る。この手段としては、ポリイミドフィルムで支持した
はんだバンプを重ねることにより、多段バンプを形成す
る方法(特開昭62−293730号公報)があるが、この方法
では、はんだバンプを積み重ねるため、必要部材の増
加、製造工数増加に伴うう価格上昇という欠点がある。
As a means for reducing the shear strain of the solder bumps, a method using a wiring board having a thermal expansion coefficient close to that of the semiconductor element can be considered. However, since the material of the mounting substrate is limited, a semiconductor element having a different thermal expansion coefficient is used. There are drawbacks such as the inability to mix. On the other hand, means for increasing the height of the solder bump to reduce shear strain has been proposed. As this means, there is a method of forming a multi-stage bump by laminating solder bumps supported by a polyimide film (Japanese Patent Application Laid-Open No. 62-293730). There is a disadvantage that the price increases due to an increase in the number of manufacturing steps.

また、第6図は、はんだバンプを圧力で接触させて電
気的接続を得る半導体素子構造である。第6図におい
て、半導体素子1と実装基板2のそれぞれの電極4上に
は、はんだバンプ3が形成されている。このはんだバン
プ3には、樹脂5の硬化時の収縮力により圧力が加わ
り、はんだバンプ3が機械的に接触し電気的な接続が得
られている。
FIG. 6 shows a semiconductor element structure in which solder bumps are brought into contact with each other by pressure to obtain electrical connection. In FIG. 6, solder bumps 3 are formed on respective electrodes 4 of the semiconductor element 1 and the mounting substrate 2. Pressure is applied to the solder bumps 3 by the shrinkage force of the resin 5 at the time of curing, and the solder bumps 3 are brought into mechanical contact to establish electrical connection.

しかしながら、この接続構造でははんだバンプ3の高
さがばらつくと電気的接続が得られない箇所が生ずる。
また、樹脂5の膨張係数ははんだバンプに比べて大きい
ため、温度変化が生じると圧力が弱まり、はんだバンプ
3の接触が不安定になるので、接続信頼性に欠けるとい
う問題点があった。
However, in this connection structure, if the height of the solder bumps 3 varies, there are places where electrical connection cannot be obtained.
In addition, since the expansion coefficient of the resin 5 is larger than that of the solder bumps, when a temperature change occurs, the pressure is weakened, and the contact of the solder bumps 3 becomes unstable.

[発明が解決しようとする課題] 本発明では、上記の如き熱変形歪が発生しても信頼性
が高く、しかも微細な接続が可能なバンプ接続方法を提
供することを目的とし、特に、はんだ等接続媒体を使わ
ずに接続を容易に確実に行うことを目的とする。
[Problems to be Solved by the Invention] It is an object of the present invention to provide a bump connection method which is highly reliable even when the thermal deformation strain as described above is generated and which enables fine connection. An object of the present invention is to easily and surely connect without using an equal connection medium.

[課題を解決するための手段および作用] 本発明は、半導体素子の電極、実装基板の電極の少な
くとも一方に、超弾性合金からなる突起電極(バンプ)
を加熱超音波法により形成することを特徴とするバンプ
形成方法、および前述の方法により形成した超弾性合金
からなる突起電極(バンプ)を介して半導体素子の電極
と実装基板の電極とを加熱超音波法により接合すること
を特徴とする半導体素子の接続方法である。
Means and Action for Solving the Problems According to the present invention, at least one of an electrode of a semiconductor element and an electrode of a mounting substrate is provided with a protruding electrode (bump) made of a superelastic alloy.
Forming a bump by heating ultrasonic method, and heating the electrode of the semiconductor element and the electrode of the mounting board via the protruding electrode (bump) made of the superelastic alloy formed by the above-described method. This is a method for connecting semiconductor elements, which is joined by an acoustic method.

なお、半導体素子と実装基板の接続にあたっては、半
導体素子の電極、実装基板の電極の一方に超弾性合金か
らなる突起電極(バンプ)を形成させておいてもよい
し、両方に超弾性合金からなる突起電極(バンプ)を形
成させておいてから両者を接合させてもよい。
In connecting the semiconductor element and the mounting board, a protruding electrode (bump) made of a superelastic alloy may be formed on one of the electrode of the semiconductor element and the electrode of the mounting board, or both may be made of a superelastic alloy. After the projection electrodes (bumps) are formed, they may be joined together.

加熱超音波法は以下のように行う。 The heating ultrasonic method is performed as follows.

超音波の入力は円柱状のセラミックス等を入力媒体と
し、実装基板または半導体素子に接触させる。加熱炉中
において電極とバンプおよび、バンプ同士が接触するよ
うに圧力をかけて超音波を入力すると、超音波は実装基
板または半導体素子、電極を通って超弾性バンプに伝わ
っていく。超音波の振動エネルギーは電極とバンプおよ
びバンプ同士の接合界面で摩擦エネルギーに変換され、
それぞれが超音波圧接される。加熱炉中で超音波を入力
することにより、バンプ同士または、バンプと金属電極
の界面で加熱炉の設定温度以上に温度を上げることがで
き接合の効率を上げることができる。バンプ同士を接合
するとき、バンプの組成は同じものでもよいが、異なる
組成のものでもよい。特に、相手側のバンプの成分にも
う一方の側のバンプ中で拡散しやすい元素が含まれる場
合には超音波接合がさらに容易になることもある。
Ultrasonic waves are input into a mounting substrate or a semiconductor element using a columnar ceramic or the like as an input medium. In a heating furnace, when an ultrasonic wave is input by applying pressure so that the electrode and the bump and the bump contact each other, the ultrasonic wave is transmitted to the superelastic bump through the mounting substrate or the semiconductor element and the electrode. Ultrasonic vibration energy is converted to friction energy at the interface between the electrode and the bump and between the bumps,
Each is ultrasonically pressed. By inputting ultrasonic waves in a heating furnace, the temperature can be raised to a temperature equal to or higher than the temperature set in the heating furnace at the bumps or at the interface between the bumps and the metal electrodes, and the joining efficiency can be increased. When joining the bumps, the bumps may have the same composition or different compositions. In particular, when the component of the bump on the other side contains an element that easily diffuses in the bump on the other side, the ultrasonic bonding may be further facilitated.

本発明で用いる加熱超音波法による接続が可能な超弾
性合金としては、Au−Cd,Au−Cu−Zn,Cu−Zn−Snのよう
な融点の比較的低い(500〜800℃)合金が適している
が、Ti−Ni、Cu−Al−Ni合金等高融点(1000℃以上)の
超弾性合金,また、In−Tl,In−Cd,In−Pb等の低融点
(300℃以下)の超弾性合金も適用できる。
As the superelastic alloy that can be connected by the heating ultrasonic method used in the present invention, an alloy having a relatively low melting point (500 to 800 ° C.) such as Au—Cd, Au—Cu—Zn, or Cu—Zn—Sn is used. Suitable, but high melting point (1000 ℃ or higher) superelastic alloy such as Ti-Ni, Cu-Al-Ni alloy, or low melting point (300 ℃ or lower) such as In-Tl, In-Cd, In-Pb Can also be used.

このように、半導体素子または、実装基板の電極に超
弾性合金からなる突起電極(バンプ)を加熱超音波法に
より形成し、バンプ同士または、一方のバンプともう一
方の電極を加熱超音波法で接合する接続構造を実施する
ことにより、はんだ等接続媒体を使わずに容易に接続を
行うことができる。また超弾性合金を使っているため、
熱変形歪に対しても超弾性変形を含めた弾性変形のみで
補うことができ、外部歪に柔軟に追従してバンプ材が破
断しない信頼性の高い接続が実現できる。
As described above, the protruding electrodes (bumps) made of a superelastic alloy are formed on the electrodes of the semiconductor element or the mounting board by the heating ultrasonic method, and the bumps or one bump and the other electrode are formed by the heating ultrasonic method. By implementing the connection structure for joining, connection can be easily performed without using a connection medium such as solder. Also, because it uses a superelastic alloy,
Thermal deformation distortion can be compensated only by elastic deformation including superelastic deformation, and a highly reliable connection in which the bump material is not broken by flexibly following external distortion can be realized.

[実施例] 次に、本発明を図面に示す実施例に基づいて説明す
る。
[Examples] Next, the present invention will be described based on examples shown in the drawings.

実施例1 第1図は、接続バンプが構成された半導体素子の断面
を示す。図中の1は半導体素子,2は実装基板,4はAl電
極,6は超弾性バンプを示す。
Example 1 FIG. 1 shows a cross section of a semiconductor device having connection bumps. In the figure, 1 is a semiconductor element, 2 is a mounting substrate, 4 is an Al electrode, and 6 is a superelastic bump.

本発明の接続バンプ構成法を説明する。 The connection bump forming method of the present invention will be described.

半導体素子のAl電極4の上に柱状のAu−Cd合金からな
る超弾性バンプ6を加熱超音波法により接合する。200
℃の加熱炉中で半導体素子に垂直方向に圧力を加えなが
ら超音波(出力0.2W)をセラミックスチップ10を通じて
超弾性バンプ側から入力し、半導体素子のAl電極4とAu
−Cd合金超弾性バンプを接合する。その後、実装基板2
の電極4と前記半導体素子1の上に形成された超弾性バ
ンプ6との位置合わせを行い、200℃の加熱炉中で、実
装基板及び半導体素子に垂直な方向に圧力を加えなが
ら、実装基板側からセラミックスチップ10を通じて超音
波(0.2W)を入力し、超弾性バンプ6と実装基板2の電
極4を接合する。なお、Au−Cd合金の組成は、室温以上
の温度で超弾性を示すAu−49.5at%Cdを選んでいる。こ
のような構造にすることにより、本実施例の超弾性バン
プは、7%の弾性歪みを有し、0〜150℃の温度サイク
ルを1000回繰り返しても電気的接触は維持された。
A columnar super-elastic bump 6 made of a Au-Cd alloy is bonded on the Al electrode 4 of the semiconductor element by a heating ultrasonic method. 200
Ultrasonic waves (output: 0.2 W) are input from the superelastic bump side through the ceramic chip 10 while applying pressure to the semiconductor element in the vertical direction in a heating furnace at ℃, and the Al electrode 4 of the semiconductor element and Au
-Join the Cd alloy superelastic bump. Then, the mounting substrate 2
The electrodes 4 are aligned with the superelastic bumps 6 formed on the semiconductor element 1, and the mounting substrate and the semiconductor element are pressed in a heating furnace at 200 ° C. in a direction perpendicular to the mounting substrate. Ultrasonic waves (0.2 W) are input from the side through the ceramic chip 10 to join the superelastic bumps 6 and the electrodes 4 of the mounting substrate 2. The composition of the Au-Cd alloy is selected to be Au-49.5 at% Cd which exhibits superelasticity at a temperature higher than room temperature. With such a structure, the superelastic bump of this example had an elastic strain of 7%, and the electrical contact was maintained even when the temperature cycle of 0 to 150 ° C. was repeated 1,000 times.

実施例2 第2図に、接続バンプを半導体素子の電極上及び、実
装基板の電極上の両方に構成した場合の実施例を示す。
1は半導体素子,2は実装基板,4はAl電極,7は超弾性バン
プである。半導体素子1のAl電極4上に、球状のAu−Cu
−Zn合金からなる超弾性バンプ7を合わせ180℃の加熱
炉中で、半導体素子に垂直な方向に圧力を加えながら、
セラミックスチップ10を通じて超弾性バンプ側から超音
波(0.3W)を入力し、半導体素子の電極4とAu−Cu−Zn
超弾性バンプを接合、形成する。Au−Cu−Zn合金の組成
は、室温以上の温度で超弾性を示すAu−27at%Cu−47at
%Znを選んでいる。また、実装基板2のAl電極4上にも
同じ成分の超弾性バンプ7を実装基板側から超音波を入
力して同様の方法で接合、形成した後、両超弾性バンプ
同士を実装基板側から超音波(0.2W)をセラミックスチ
ップ10を通じて入力することにより接合する。このよう
な構造にすることにより、本超弾性バンプは6%の弾性
歪みを有し、0〜150℃の温度サイクルを1000回繰り返
しても電気的接触が維持された。
Embodiment 2 FIG. 2 shows an embodiment in which connection bumps are formed on both electrodes of a semiconductor element and electrodes of a mounting substrate.
1 is a semiconductor element, 2 is a mounting substrate, 4 is an Al electrode, and 7 is a superelastic bump. On the Al electrode 4 of the semiconductor element 1, a spherical Au-Cu
The superelastic bump 7 made of -Zn alloy is put together in a heating furnace at 180 ° C. while applying pressure in a direction perpendicular to the semiconductor element.
Ultrasonic waves (0.3 W) are input from the superelastic bump side through the ceramic chip 10, and the electrode 4 of the semiconductor element and the Au-Cu-Zn
Join and form super elastic bumps. The composition of Au-Cu-Zn alloy is Au-27at% Cu-47at which shows superelasticity at room temperature or higher.
% Zn is selected. Also, the superelastic bumps 7 of the same component are bonded and formed on the Al electrode 4 of the mounting substrate 2 in the same manner by inputting ultrasonic waves from the mounting substrate side, and then the two superelastic bumps are connected to each other from the mounting substrate side. Bonding is performed by inputting ultrasonic waves (0.2 W) through the ceramic chip 10. With such a structure, the present superelastic bump has an elastic strain of 6%, and the electrical contact is maintained even when the temperature cycle of 0 to 150 ° C. is repeated 1000 times.

実施例3 第3図に、異なる種類の超弾性バンプを半導体素子の
電極上及び、実装基板の電極上にそれぞれ構成した場合
の実施例を示す。1は半導体素子、2は実装基板、4は
Al電極、8,9は超弾性バンプである。半導体素子1のAl
電極4上に、柱状のCu−Zn−Sn合金からなる超弾性バン
プ8を200℃の加熱炉中で半導体素子に垂直な方向に圧
力をかけながら超弾性バンプ側からセラミックスチップ
10を通じて超音波(0.2W)を入力し、半導体素子1の電
極4と接合する。Cu−Zn−Sn合金の組成は、室温以上の
温度で超弾性を示すCu−34.7wt%Zn−3.0wt%Snを選ん
でいる。また、実装基板2のAl電極4上には、実装基板
側から超音波(0.2W)を入力することにより同様の方法
で柱状のAu−Cu−Zn合金超弾性バンプ9を接合、形成し
た後、両超弾性バンプを実装基板側からセラミックスチ
ップ10を通じて超音波(0.3W)を入力することにより接
合する。Au−Cu−Zn合金の組成は、室温以上の温度で超
弾性効果を示すAu−27at%Cu−47at%Znを選んでいる。
Third Embodiment FIG. 3 shows an embodiment in which different types of superelastic bumps are respectively formed on electrodes of a semiconductor element and electrodes of a mounting substrate. 1 is a semiconductor element, 2 is a mounting board, 4 is
Al electrodes 8, 9 are superelastic bumps. Al of semiconductor element 1
A superelastic bump 8 made of a columnar Cu-Zn-Sn alloy is placed on the electrode 4 in a heating furnace at 200 ° C while applying pressure in a direction perpendicular to the semiconductor element from the superelastic bump side to the ceramic chip.
Ultrasonic waves (0.2 W) are input through 10 and joined to the electrodes 4 of the semiconductor element 1. As the composition of the Cu-Zn-Sn alloy, Cu-34.7wt% Zn-3.0wt% Sn which exhibits superelasticity at a temperature higher than room temperature is selected. Also, a columnar Au-Cu-Zn alloy superelastic bump 9 is bonded and formed on the Al electrode 4 of the mounting substrate 2 in the same manner by inputting ultrasonic waves (0.2 W) from the mounting substrate side. The two superelastic bumps are joined by inputting ultrasonic waves (0.3 W) through the ceramic chip 10 from the mounting substrate side. As the composition of the Au-Cu-Zn alloy, Au-27at% Cu-47at% Zn, which exhibits a superelastic effect at a temperature higher than room temperature, is selected.

このような構造にすることにより、Cu−Zn−Sn超弾性
バンプは2%の弾性歪,Au−Cu−Zn超弾性バンプは6%
の弾性歪を有し、0〜150℃の温度サイクルを1000回繰
り返しても電気的接続は維持された。
With such a structure, the Cu-Zn-Sn superelastic bump has 2% elastic strain, and the Au-Cu-Zn superelastic bump has 6% elastic strain.
The electrical connection was maintained even when the temperature cycle of 0 to 150 ° C. was repeated 1000 times.

[発明の効果] 以上の如く本発明は、半導体素子接続用バンプとし
て、超弾性合金を使用し、実装基板と超弾性バンプ、半
導体素子と超弾性バンプ、また、超弾性バンプ同士の接
合に加熱超音波法を用いたことを特徴としている。本超
弾性バンプを用いて、半導体素子と実装基板との接合に
加熱と超音波を併用することにより、半導体素子に熱影
響を及ぼさない程度の低温での接合が可能であり、温度
変化で生じる熱応力による歪やバンプ高さのばらつきに
対して信頼性の高いフリップチップ接合が容易に実現で
きた。
[Effects of the Invention] As described above, the present invention uses a superelastic alloy as a bump for connecting a semiconductor element, and heats the bonding between the mounting substrate and the superelastic bump, the semiconductor element and the superelastic bump, and the bonding between the superelastic bumps. It is characterized by using an ultrasonic method. By using this superelastic bump, heating and ultrasonic waves are jointly used to join the semiconductor element and the mounting board, it is possible to join at a low temperature that does not have a thermal effect on the semiconductor element, and it is caused by a temperature change Flip-chip bonding with high reliability against distortion and variations in bump height due to thermal stress was easily realized.

【図面の簡単な説明】[Brief description of the drawings]

第1図は、柱状のAu−Cd超弾性バンプを介して半導体素
子と実装基板の電極同志を加熱超音波法により接続させ
る様子を示す断面図である。 第2図は、半導体素子の電極と実装基板の電極のそれぞ
れに構成した球状のAu−Cu−Zn超弾性バンプ同士を加熱
超音波法により接続させた断面図である。 第3図は、半導体素子の電極に構成した柱状のCu−Zn−
Sn超弾性バンプと実装基板の電極上に構成したAu−Cu−
Zn超弾性バンプを加熱超音波法により接続させた断面図
である。 第4図〜第6図は、従来のはんだバンプにより接続され
た半導体素子と実装基板の断面図であり、第4図は、正
常な状態を示す図、第5図は、温度変化により実装基板
が膨張し、バンプにせん断歪みが導入された様子を示す
図、第6図は、はんだバンプを圧力で接触させて、樹脂
で固めた場合の半導体素子構造を示す図である。 1…半導体素子、2…実装基板、3…はんだバンプ、4
…金属電極、5…樹脂、6…Au−Cd超弾性バンプ(柱
状)、7…Au−Cu−Zn超弾性バンプ(球状)、8…Cu−
Zn−Sn超弾性バンプ(柱状)、9…Au−Cu−Zn超弾性バ
ンプ(柱状)、10…セラミックスチップ。
FIG. 1 is a cross-sectional view showing a state in which a semiconductor element and electrodes of a mounting board are connected by a heating ultrasonic method via columnar Au-Cd superelastic bumps. FIG. 2 is a cross-sectional view in which spherical Au—Cu—Zn superelastic bumps formed on the electrodes of the semiconductor element and the electrodes of the mounting board are connected by a heating ultrasonic method. FIG. 3 shows a columnar Cu—Zn—
Au-Cu- composed of Sn superelastic bumps and electrodes on the mounting board
It is sectional drawing which connected Zn super elastic bump by the heating ultrasonic method. 4 to 6 are cross-sectional views of a conventional semiconductor device and a mounting board connected by solder bumps. FIG. 4 shows a normal state, and FIG. 5 shows a mounting board due to a temperature change. FIG. 6 is a view showing a state in which the solder bumps are expanded and shear strain is introduced into the bumps. FIG. 6 is a view showing a semiconductor element structure in a case where the solder bumps are brought into contact with each other by pressure and solidified with a resin. DESCRIPTION OF SYMBOLS 1 ... Semiconductor element, 2 ... Mounting board, 3 ... Solder bump, 4
... Metal electrode, 5 ... Resin, 6 ... Au-Cd superelastic bump (columnar), 7 ... Au-Cu-Zn superelastic bump (spherical), 8 ... Cu-
Zn-Sn superelastic bump (columnar), 9 ... Au-Cu-Zn superelastic bump (columnar), 10 ... ceramic chip.

───────────────────────────────────────────────────── フロントページの続き (72)発明者 大関 芳雄 神奈川県川崎市中原区井田1618番地 新 日本製鐵株式會社第1技術研究所内 (72)発明者 渡辺 敬介 東京都港区虎ノ門1丁目7番12号 沖電 気工業株式会社内 (72)発明者 金森 孝史 東京都港区虎ノ門1丁目7番12号 沖電 気工業株式会社内 (72)発明者 井口 泰男 東京都港区虎ノ門1丁目7番12号 沖電 気工業株式会社内 (56)参考文献 特開 平2−58346(JP,A) 特開 昭64−81264(JP,A) 特開 昭63−106979(JP,A) 特開 昭62−258675(JP,A) (58)調査した分野(Int.Cl.6,DB名) H01L 21/60 H01L 21/321──────────────────────────────────────────────────続 き Continuing from the front page (72) Inventor Yoshio Ozeki 1618 Ida, Nakahara-ku, Kawasaki-shi, Kanagawa Prefecture New Nippon Steel Corporation 1st Technical Research Institute (72) Inventor Keisuke Watanabe 1-7-7 Toranomon, Minato-ku, Tokyo No. 12 Oki Electric Industry Co., Ltd. (72) Inventor Takashi Kanamori 1-7-1, Toranomon, Minato-ku, Tokyo Oki Electric Industry Co., Ltd. (72) Inventor Yasuo Iguchi 1-7-7 Toranomon, Minato-ku, Tokyo No. 12 Oki Electric Industry Co., Ltd. (56) Reference JP-A-2-58346 (JP, A) JP-A 64-81264 (JP, A) JP-A 63-106979 (JP, A) JP 62-258675 (JP, A) (58) Fields investigated (Int. Cl. 6 , DB name) H01L 21/60 H01L 21/321

Claims (2)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】半導体素子の電極、実装基板表面の電極の
少なくとも一方に、超弾性合金からなる突起電極(バン
プ)を加熱超音波法により形成することを特徴とするバ
ンプ形成方法。
2. A bump forming method, comprising: forming a projecting electrode (bump) made of a superelastic alloy on at least one of an electrode of a semiconductor element and an electrode on a surface of a mounting substrate by a heating ultrasonic method.
【請求項2】請求項1記載の方法により形成した超弾性
合金からなる突起電極(バンプ)を介して半導体素子の
電極と実装基板の電極とを加熱超音波法により接合する
ことを特徴とする半導体素子の接続方法。
2. The method according to claim 1, wherein the electrodes of the semiconductor element and the electrodes of the mounting board are joined by a heating ultrasonic method via bumps (bumps) made of a superelastic alloy formed by the method of claim 1. How to connect semiconductor elements.
JP2730089A 1989-02-06 1989-02-06 Bump forming method and semiconductor element connecting method Expired - Fee Related JP2770041B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2730089A JP2770041B2 (en) 1989-02-06 1989-02-06 Bump forming method and semiconductor element connecting method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2730089A JP2770041B2 (en) 1989-02-06 1989-02-06 Bump forming method and semiconductor element connecting method

Publications (2)

Publication Number Publication Date
JPH02206125A JPH02206125A (en) 1990-08-15
JP2770041B2 true JP2770041B2 (en) 1998-06-25

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3243956B2 (en) * 1995-02-03 2002-01-07 松下電器産業株式会社 Semiconductor device and manufacturing method thereof
JP3307145B2 (en) * 1995-03-27 2002-07-24 株式会社日立製作所 Power chip carrier and power semiconductor device using the same
JP2001015553A (en) * 1999-06-29 2001-01-19 Rohm Co Ltd Manufacture of semiconductor device
US7402509B2 (en) * 2005-03-16 2008-07-22 Intel Corporation Method of forming self-passivating interconnects and resulting devices

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