JPS6016432A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS6016432A
JPS6016432A JP10457984A JP10457984A JPS6016432A JP S6016432 A JPS6016432 A JP S6016432A JP 10457984 A JP10457984 A JP 10457984A JP 10457984 A JP10457984 A JP 10457984A JP S6016432 A JPS6016432 A JP S6016432A
Authority
JP
Japan
Prior art keywords
semiconductor
tab
bonding
layer
pellet
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10457984A
Other languages
Japanese (ja)
Inventor
Yoshiaki Wakashima
若島　喜昭
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP10457984A priority Critical patent/JPS6016432A/en
Publication of JPS6016432A publication Critical patent/JPS6016432A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/27—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/27—Manufacturing methods
    • H01L2224/274—Manufacturing methods by blanket deposition of the material of the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29298—Fillers
    • H01L2224/29299—Base material
    • H01L2224/293—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29338—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/29339—Silver [Ag] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83191—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/8385—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01015—Phosphorus [P]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01047—Silver [Ag]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/06—Polymers
    • H01L2924/078—Adhesive characteristics other than chemical
    • H01L2924/07802—Adhesive characteristics other than chemical not being an ohmic electrical conductor

Abstract

PURPOSE:To obtain a device having no bonding failure, crack of pellet and contamination by forming a bonding material layer with a material containing an organic resin which melts when heated on the occasion of forming a semiconductor device by bonding semiconductor pellet to the specified region on the tab through a bonding material layer. CONSTITUTION:A bonding material layer 2 which is a solid under a normal temperature but melts when heated such as Ag paste is formed at the rear surface of a semiconductor wafer 1 having a large area wherein the specified P-N junction is formed. The wafer 1 is then divided into the pellets 11 of the specified shape and the side of bonding layer 2 is placed on the tab 3. Thereafter, it is heated up to a temperature wherein the layer 2 melts and is bonded. Thereby, the layer 2 can be formed in the specified thickness easily and bonding failure, generation of crack and deterioration of characteristic can be eliminated.

Description

【発明の詳細な説明】 本発明は半導体ペレットをタブにダイボンディングした
半導体装置に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device in which a semiconductor pellet is die-bonded to a tab.

半導体ペレットのダイボンディング法としては、通常次
の２通りの方法が行なわれている。その１つは、タブ表
面に予かじめ金めっき層を形成しておき、タブ上に半導
体ペレットを載置して両者を金と半導体との共晶温度以
上に加熱して接着する方法であり、もう１つは、タブ表
面に液状のＡｇペーストを塗布し、タブ上へＡｇペース
トを挾むように半導体ペレットを載置して接着する方法
である。前者の方法では、（１）接着時に半導体ペレッ
トとタブとを金と半導体との共晶温度以上に加熱する必
要がある。（２１半導体ペレットとタブとの間に発生す
る熱膨張係数の差に基づく応力を吸収できず、半導体ペ
レットの特性の劣化、更には半導体ペレットにクラック
が生じるおそれがある。（３１作業工数がかかる等の欠
点があり、後者の方法では、（１１Ａｇペーストの塗布
工数がかかる、（２１Ａｇペーストの塗布量がばらつき
易く、量が少いときは接着不良及び半導体ペレットにク
ラックを招き、量が多いときは半導体ペレットを汚染し
特性の低下を招く、等の欠点がある。The following two methods are generally used for die bonding semiconductor pellets. One method is to form a gold plating layer on the tab surface in advance, place a semiconductor pellet on the tab, and heat the two to a temperature higher than the eutectic temperature of gold and semiconductor to bond them together. The other method is to apply a liquid Ag paste to the tab surface, and then place a semiconductor pellet on the tab so as to sandwich the Ag paste, and then bond the tab. In the former method, (1) it is necessary to heat the semiconductor pellet and tab to a temperature higher than the eutectic temperature of gold and semiconductor during bonding. (21 Stress caused by the difference in thermal expansion coefficient that occurs between the semiconductor pellet and the tab cannot be absorbed, leading to deterioration of the properties of the semiconductor pellet and even cracks in the semiconductor pellet. (31 It takes a lot of work. The latter method has disadvantages such as (requires a lot of man-hours for applying 11Ag paste, (21Ag paste application amount tends to vary, and when the amount is small, it may lead to poor adhesion and cracks in the semiconductor pellet, and when the amount is large, has disadvantages such as contaminating the semiconductor pellet and causing deterioration of its characteristics.

本発明の目的は、上述の如き欠点を除去した改良された
半導体ペレットのダイボンディング法を用いた半導体装
置を提供することにある。本発明の半導体装置の半導体
ペレットのダイボンディング法の特徴とするところは、
予かじめ接着材層を硬化状態となるように形成しておき
、それをタブ面上に載置して加熱接着するようにした点
にある。An object of the present invention is to provide a semiconductor device using an improved semiconductor pellet die bonding method that eliminates the above-mentioned drawbacks. The features of the die bonding method for semiconductor pellets for semiconductor devices of the present invention are as follows:
The adhesive layer is formed in advance to be in a hardened state, and then placed on the tab surface and bonded by heating.

以下本発明の実施例図面により詳細に説明する。DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be explained in detail below with reference to the drawings.

図において、１は周知の方法により所定のｐｎ接合を形
成した大面積の半導体ウェハで、本発明の実施に当って
は、このウェハ１の一方の面に接着材層２を形成する（
第１図）。接着材層２は塗布、印刷等により所望の厚さ
で一様にウニ八表面に被着し硬化せしめる。接着材層２
としては、例えばＡｇペーストなどの常温で固体で且つ
加熱により溶融するものを使用する。第１図に示した半
導体ウェハ１は一方の面に接着材層２が被着された状態
で所望の大きさの半導体ペレット１１に分割される（第
２図）。半導体ベレット１１はその接着材層２が被着さ
れた側をタブ３側にしてタブ３上に載置する（第３図）
。半導体ペレット１１をタブ３上に載置した状態で、両
者を接着材層２が溶融する温度に加熱し、接着する（第
４図）。In the figure, 1 is a large-area semiconductor wafer on which a predetermined pn junction is formed by a well-known method. In carrying out the present invention, an adhesive layer 2 is formed on one surface of this wafer 1 (
Figure 1). The adhesive layer 2 is uniformly applied to the surface of the sea urchin to a desired thickness by coating, printing, etc., and is then hardened. Adhesive layer 2
For example, a material such as Ag paste that is solid at room temperature and melts when heated is used. The semiconductor wafer 1 shown in FIG. 1 is divided into semiconductor pellets 11 of a desired size with an adhesive layer 2 adhered to one side (FIG. 2). The semiconductor pellet 11 is placed on the tab 3 with the side on which the adhesive layer 2 is applied facing the tab 3 (FIG. 3).
. With the semiconductor pellet 11 placed on the tab 3, both are heated to a temperature at which the adhesive layer 2 melts and are bonded together (FIG. 4).

図面では接着材層２は大面積のウェハの状態において形
成する場合を示しているが、半導体ペレットに分割した
後に形成してもよい。しかしながら、ウェハの状態で形
成する方法が量産性の点で優れている。Although the drawings show a case in which the adhesive layer 2 is formed on a large-area wafer, it may be formed after the wafer is divided into semiconductor pellets. However, the method of forming in a wafer state is superior in terms of mass productivity.

以上のような本発明のダイボンディング法によれば、接
着材層を半導体ベレット面に予かじめ塗布印刷等により
所定の厚さに形成しであるため、接着材層の厚さ不足或
いは過剰による問題、即ち接着不良、クラック発生成い
は特性低下等の生じるおそれは一掃される。また接着材
層は接着処理直前の状態では液状でないため接着処理時
にベレットの取扱いが容易になる効果もある。According to the die bonding method of the present invention as described above, since the adhesive layer is formed on the surface of the semiconductor pellet in advance to a predetermined thickness by coating and printing, etc., The possibility of problems such as poor adhesion, cracking, or deterioration of properties is eliminated. Furthermore, since the adhesive layer is not in a liquid state immediately before the adhesive treatment, the pellet can be easily handled during the adhesive treatment.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図から第４図は本発明ダイボンディング法を説明す
るための概略工程図である。 １・・・半導体ウェハ、２・・・接着材層、３・・・タ
ブ、１１・・・半導体ペレット。1 to 4 are schematic process diagrams for explaining the die bonding method of the present invention. DESCRIPTION OF SYMBOLS 1... Semiconductor wafer, 2... Adhesive material layer, 3... Tab, 11... Semiconductor pellet.

Claims (1)

【特許請求の範囲】[Claims] １、少なくとも所定位置に半導体ペレットが載置される
タブと、前記タブ上に接着材層を介して接着された半導
体ペレットとからなる半導体装置において、前記接着材
層は加熱すると溶融する性質を有する有機樹脂を含む部
材であることを特徴とする半導体装置。1. In a semiconductor device comprising a tab on which a semiconductor pellet is placed at least in a predetermined position, and a semiconductor pellet bonded onto the tab via an adhesive layer, the adhesive layer has a property of melting when heated. A semiconductor device characterized by being a member containing an organic resin.
JP10457984A 1984-05-25 1984-05-25 Semiconductor device Pending JPS6016432A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10457984A JPS6016432A (en) 1984-05-25 1984-05-25 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10457984A JPS6016432A (en) 1984-05-25 1984-05-25 Semiconductor device

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
JP1981878A Division JPS54113253A (en) 1978-02-24 1978-02-24 Bonding method of semiconductor pellet

Publications (1)

Publication Number Publication Date
JPS6016432A true JPS6016432A (en) 1985-01-28

Family

ID=14384343

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10457984A Pending JPS6016432A (en) 1984-05-25 1984-05-25 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS6016432A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0413583U (en) * 1990-05-25 1992-02-04
US7407084B2 (en) 2004-12-06 2008-08-05 Unaxis Trading Ltd Method for mounting a semiconductor chip onto a substrate

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0413583U (en) * 1990-05-25 1992-02-04
US7407084B2 (en) 2004-12-06 2008-08-05 Unaxis Trading Ltd Method for mounting a semiconductor chip onto a substrate

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