JPH06151912A - Optical semiconductor device and its manufacture - Google Patents

Optical semiconductor device and its manufacture

Info

Publication number
JPH06151912A
JPH06151912A JP4304213A JP30421392A JPH06151912A JP H06151912 A JPH06151912 A JP H06151912A JP 4304213 A JP4304213 A JP 4304213A JP 30421392 A JP30421392 A JP 30421392A JP H06151912 A JPH06151912 A JP H06151912A
Authority
JP
Japan
Prior art keywords
semiconductor layer
type semiconductor
film
transparent conductive
chromium
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP4304213A
Other languages
Japanese (ja)
Inventor
Teruhiko Ichimura
照彦 市村
Yasuhiro Nasu
安宏 那須
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP4304213A priority Critical patent/JPH06151912A/en
Publication of JPH06151912A publication Critical patent/JPH06151912A/en
Withdrawn legal-status Critical Current

Links

Classifications

    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02EREDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00Energy generation through renewable energy sources
    • Y02E10/50Photovoltaic [PV] energy

Abstract

PURPOSE:To shorten the manufacturing time by simplifying the process thereby saving manufacturing facility, concerning an optical semiconductor device and its manufacture. CONSTITUTION:This optical semiconductor device has a one-conductivity-type semiconductor layer 3, an intrinsic semiconductor layer 3, an opposite-conductivity-type semiconductor layer 5, and a transparent conductive film 7 stacked in order on a substrate, and a chromium electrode 9 arranged on the transparent conductive film 7, and the transparent conductive film 7 contains phosphorus and chromium. Moreover, this includes a process of stacking the one-conductivity-type semiconductor layer 3, the intrinsic semiconductor layer 4, and the opposite-conductivity-type semiconductor layer 5 in order on the substrate 1, a process of accumulating a chromium film 8, after sticking phosphorus to the surface of the opposite- conductivity-type semiconductor layer 5, and further, forming the transparent conductive film 7 including phosphorus and chromium between the opposite-conductivity-type semiconductor layer 5 and the chromium film 8 by heat treatment, and a process of selectively etching the chromium film 8, using a mask, thereby forming a window 10 to expose the transparent conductive film 7. Moreover, the stacking of the one-conductivity-type semiconductor layer 3, the intrinsic semiconductor layer 4, and the opposite-conductivity-type semiconductor layer 5 and the sticking of phosphorus to the surface of the opposite-conductivity-type semiconductor layer 5 are performed in the continuous process by plasma CVD method.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は光半導体装置及びその製
造方法に係り,特に太陽電池及びその製造方法に関す
る。近年,太陽電池は高効率のものが要求され,さらに
低コストのものが要求されている。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an optical semiconductor device and its manufacturing method, and more particularly to a solar cell and its manufacturing method. In recent years, solar cells have been required to have high efficiency and low cost.

【0002】[0002]

【従来の技術】図2(a) 〜(c) は従来例を示す工程順断
面図である。以下, これらの図を参照しながら, 従来の
製造工程を説明する。
2. Description of the Related Art FIGS. 2A to 2C are sectional views in order of steps showing a conventional example. The conventional manufacturing process will be described below with reference to these drawings.

【0003】図2(a) 参照 基板1は例えばガラス基板であり,その上に例えば厚さ
800ÅのCr膜2を堆積する。Cr膜2は下部電極とな
る。その上に例えばプラズマCVD法により,厚さ 100
Åのn型半導体層3,厚さ5000Åの真性半導体層4,厚
さ 100Åのp型半導体層5を連続成膜する。
Referring to FIG. 2 (a), a substrate 1 is, for example, a glass substrate, on which a thickness of
Deposit 800Å Cr film 2. The Cr film 2 becomes the lower electrode. On top of that, a thickness of 100
A Å n-type semiconductor layer 3, a 5000 Å-thick intrinsic semiconductor layer 4, and a 100 Å-thick p-type semiconductor layer 5 are continuously formed.

【0004】図2(b) 参照 透明導電膜となる例えば厚さ1000ÅのITO膜11をスパ
ッタ法により形成し,次いで,低抵抗化のために不透明
電極膜となる例えばCr膜8をスパッタ法により形成す
る。
See FIG. 2 (b). For example, an ITO film 11 having a thickness of 1000 Å to be a transparent conductive film is formed by a sputtering method, and then a Cr film 8 to be an opaque electrode film for reducing resistance is formed by a sputtering method. Form.

【0005】図2(c) 参照 マスクを用いてCr膜8をエッチングし,格子状にCr
膜8を残してCr電極9を形成すると同時にITO膜11
を露出する窓10を形成する。Cr電極9は上部電極であ
る。このようにして,太陽電池が完成する。
Referring to FIG. 2 (c), the Cr film 8 is etched using a mask to form Cr in a lattice pattern.
At the same time as forming the Cr electrode 9 while leaving the film 8, the ITO film 11 is formed.
A window 10 is formed to expose the. The Cr electrode 9 is an upper electrode. In this way, the solar cell is completed.

【0006】[0006]

【発明が解決しようとする課題】上記の従来例では,透
明導電膜となるITO膜11の形成と不透明電極膜となる
Cr膜8の形成は,それぞれ,異なるスパッタ装置によ
り別々に行うのが一般であり,そのため製造設備の費用
がかさみ,製造時間が長くなる。
In the above-described conventional example, it is general that the formation of the ITO film 11 serving as the transparent conductive film and the formation of the Cr film 8 serving as the opaque electrode film are separately performed by different sputtering devices. Therefore, the cost of the manufacturing equipment is increased and the manufacturing time becomes long.

【0007】本発明は上記の問題に鑑み,製造設備の費
用を節約し,かつ製造時間を短縮できる方法を提供する
ものである。
In view of the above problems, the present invention provides a method for saving the cost of manufacturing equipment and shortening the manufacturing time.

【0008】[0008]

【課題を解決するための手段】図1(a) 〜(c) は本発明
の実施例を示す工程順断面図である。上記課題は,基板
1上に順に積層された一導電型半導体層3,真性半導体
層4,反対導電型半導体層5,透明導電膜7と,該透明
導電膜7上に配置されたクロム電極9を有し,該透明導
電膜7はリンとクロムを含む光半導体装置によって解決
される。
1 (a) to 1 (c) are sectional views in order of the steps, showing an embodiment of the present invention. The above-mentioned problem is solved by one conductive type semiconductor layer 3, an intrinsic semiconductor layer 4, an opposite conductive type semiconductor layer 5, a transparent conductive film 7, and a chromium electrode 9 arranged on the transparent conductive film 7, which are sequentially stacked on the substrate 1. And the transparent conductive film 7 is solved by an optical semiconductor device containing phosphorus and chromium.

【0009】また,基板1上に一導電型半導体層3,真
性半導体層4,反対導電型半導体層5を順に積層する工
程と,該反対導電型半導体層5表面にリンを付着した後
クロム膜8を堆積し, 熱処理により該反対導電型半導体
層5と該クロム膜8の間にリンとクロムを含む透明導電
膜7を形成する工程と,マスクを用いて該クロム膜8を
選択的にエッチングして該透明導電膜7を露出する窓10
を形成する工程とを有する光半導体装置の製造方法によ
って解決される。
Further, a step of sequentially laminating the one conductivity type semiconductor layer 3, the intrinsic semiconductor layer 4, and the opposite conductivity type semiconductor layer 5 on the substrate 1, and a chromium film after phosphorus is attached to the surface of the opposite conductivity type semiconductor layer 5. 8 and deposit a transparent conductive film 7 containing phosphorus and chromium between the opposite conductivity type semiconductor layer 5 and the chromium film 8 by heat treatment, and selectively etch the chromium film 8 using a mask. And the window 10 exposing the transparent conductive film 7
And a method of manufacturing an optical semiconductor device, the method including:

【0010】また,前記一導電型半導体層3,前記真性
半導体層4,前記反対導電型半導体層5の積層と該反対
導電型半導体層5表面へのリンの付着はプラズマCVD
法による連続工程で行う前記の光半導体装置の製造方法
によって解決される。
In addition, the lamination of the one conductivity type semiconductor layer 3, the intrinsic semiconductor layer 4, and the opposite conductivity type semiconductor layer 5 and the deposition of phosphorus on the surface of the opposite conductivity type semiconductor layer 5 are performed by plasma CVD.
This is solved by the above-described method for manufacturing an optical semiconductor device, which is performed in successive steps.

【0011】[0011]

【作用】本発明では,透明導電膜となるリン(P)層の
形成に一導電型半導体層3,真性半導体層4,反対導電
型半導体層5の積層に使用する装置をそのまま使用でき
るから,従来例のITO膜形成に使用する装置,例えば
スパッタ装置を必要としない。
In the present invention, the device used for laminating the one conductivity type semiconductor layer 3, the intrinsic semiconductor layer 4, and the opposite conductivity type semiconductor layer 5 for forming the phosphorus (P) layer which becomes the transparent conductive film can be used as it is. The apparatus used for forming the ITO film in the conventional example, for example, the sputtering apparatus is not required.

【0012】また,透明導電膜となるP層の形成は,一
導電型半導体層3,真性半導体層4,反対導電型半導体
層5の積層につづいて連続して行うことができるから,
従来例に比べて製造時間が短縮できる。
Further, since the P layer to be the transparent conductive film can be formed continuously after the lamination of the one conductivity type semiconductor layer 3, the intrinsic semiconductor layer 4 and the opposite conductivity type semiconductor layer 5,
The manufacturing time can be shortened as compared with the conventional example.

【0013】また,クロム膜8を選択的にエッチングす
ることにより,リンとクロムを含む透明導電膜7はエッ
チングせずに残すことができる。
Further, by selectively etching the chromium film 8, the transparent conductive film 7 containing phosphorus and chromium can be left without being etched.

【0014】[0014]

【実施例】図1(a) 〜(c) は実施例を示す工程順断面図
であり,1はガラス基板,2はCr膜であって下部電
極,3はn型a−Si層,4は真性a−Si層,5はp
型a−Si層,6はP(リン)層,7は透明導電膜,8
はCr膜,9はCr電極であって上部電極,10は窓を表
す。以下,これらの図を参照しながら,実施例について
説明する。
1 (a) to 1 (c) are sectional views in order of steps showing an embodiment, in which 1 is a glass substrate, 2 is a Cr film and a lower electrode, 3 is an n-type a-Si layer, 4 Is an intrinsic a-Si layer, 5 is p
Type a-Si layer, 6 is a P (phosphorus) layer, 7 is a transparent conductive film, 8
Is a Cr film, 9 is a Cr electrode and is an upper electrode, and 10 is a window. Examples will be described below with reference to these drawings.

【0015】図1(a) 参照 基板1は例えばガラス基板であり,その上に例えば厚さ
800ÅのCr膜2をスパッタ法により堆積する。Cr膜
2は下部電極となる。その上に例えばプラズマCVD法
により,厚さ 100Åのn型半導体層3,厚さ5000Åの真
性半導体層4,厚さ 100Åのp型半導体層5,厚さ 100
Å以下のP層6を連続成膜する。n型半導体層3は例え
ばPをドープした非晶質シリコン(a−Si)層,真性
半導体層4は例えばノンドープのa−Si層,p型半導
体層5は例えばB(ほう素)をドープしたa−Si層で
ある。P層6はn型半導体層3を成膜したチャンバかま
たは別のチャンバでPH3 ガスを導入してプラズマをた
て,そのプラズマにガラス基板1を曝して,Pをp型半
導体層5表面に付着させることにより形成する。付着厚
さは例えば50Åであり,そのための条件は例えばPH
3 ガスの圧力1Torr,流量 200sccm,電力 200W,成膜
時間10分である。
Referring to FIG. 1 (a), the substrate 1 is, for example, a glass substrate, on which, for example, a thickness is set.
A 800 Å Cr film 2 is deposited by sputtering. The Cr film 2 becomes the lower electrode. Further, for example, by plasma CVD, an n-type semiconductor layer with a thickness of 100Å 3, an intrinsic semiconductor layer with a thickness of 5000Å 4, a p-type semiconductor layer with a thickness of 100Å 5, a thickness of 100
Å The following P layer 6 is continuously formed. The n-type semiconductor layer 3 is, for example, a P-doped amorphous silicon (a-Si) layer, the intrinsic semiconductor layer 4 is, for example, a non-doped a-Si layer, and the p-type semiconductor layer 5 is, for example, B (boron) -doped. It is an a-Si layer. For the P layer 6, PH 3 gas is introduced into the chamber where the n-type semiconductor layer 3 is deposited or another chamber is ignited to generate plasma, and the glass substrate 1 is exposed to the plasma to expose P to the surface of the p-type semiconductor layer 5. It is formed by attaching to. The adhesion thickness is, for example, 50Å, and the conditions therefor are, for example, PH.
The pressure of the three gases is 1 Torr, the flow rate is 200 sccm, the power is 200 W, and the film formation time is 10 minutes.

【0016】図1(b) 参照 次いで,不透明電極膜となる例えば厚さ2000ÅのCr膜
8を例えばスパッタ法により形成する。約 200℃で加熱
することにより,P層6は上下に存在するCr及びSi
と反応して,透明導電膜7が形成される。
Next, as shown in FIG. 1B, a Cr film 8 having a thickness of 2000 Å, which will be an opaque electrode film, is formed by, for example, a sputtering method. By heating at about 200 ° C, the P layer 6 has Cr and Si existing above and below.
And the transparent conductive film 7 is formed.

【0017】図1(c) 参照 全面にフォトレジストを塗布し,露光・現像により格子
状のレジストパターンを形成する。このレジストパター
ンをマスクにしてCr膜8を硝酸セリウム第二アンモン
を主成分とする水溶液で選択的にエッチングして,格子
状にCr膜8を残してCr電極9を形成する。それと同
時に透明導電膜7を露出する窓10を形成する。Cr電極
9は上部電極である。このようにして,太陽電池が完成
する。
Referring to FIG. 1C, a photoresist is applied on the entire surface, and a grid-shaped resist pattern is formed by exposure and development. Using this resist pattern as a mask, the Cr film 8 is selectively etched with an aqueous solution containing cerium nitrate second ammonium as a main component to form a Cr electrode 9 while leaving the Cr film 8 in a grid pattern. At the same time, a window 10 exposing the transparent conductive film 7 is formed. The Cr electrode 9 is an upper electrode. In this way, the solar cell is completed.

【0018】なお,上記の実施例では基板1としてガラ
ス基板を用いたが,Si基板を用いることもできる。要
は絶縁性基板か半導体基板であればよい。また,上記の
実施例では,n型半導体層,i型半導体層,p型半導体
層の順に積層したが,p型半導体層,i型半導体層,n
型半導体層の順に積層してもよい。
Although a glass substrate is used as the substrate 1 in the above embodiment, a Si substrate can also be used. The point is that it may be an insulating substrate or a semiconductor substrate. Further, in the above embodiment, the n-type semiconductor layer, the i-type semiconductor layer, and the p-type semiconductor layer are stacked in this order, but the p-type semiconductor layer, the i-type semiconductor layer, and the n-type semiconductor layer are stacked.
The type semiconductor layers may be stacked in this order.

【0019】[0019]

【発明の効果】以上説明したように,本発明によれば,
従来のITO膜による透明導電膜に替えてCrとPを含
む透明導電膜を形成することにより,ITO膜形成に用
いていた製造設備を必要としなくなる。また,製造時間
を短縮できる。
As described above, according to the present invention,
By forming the transparent conductive film containing Cr and P in place of the conventional transparent conductive film made of the ITO film, the manufacturing equipment used for forming the ITO film becomes unnecessary. In addition, the manufacturing time can be shortened.

【0020】本発明は,太陽電池の低コスト化に寄与す
るものである。
The present invention contributes to cost reduction of solar cells.

【図面の簡単な説明】[Brief description of drawings]

【図1】(a) 〜(c) は実施例を示す工程順断面図であ
る。
1A to 1C are sectional views in order of the processes, showing an embodiment.

【図2】(a) 〜(c) は従来例を示す工程順断面図であ
る。
2A to 2C are cross-sectional views in order of the processes, showing a conventional example.

【符号の説明】[Explanation of symbols]

1は基板であってガラス基板 2はCr膜であって下部電極 3はn型半導体層であってn型a−Si層 4は真性半導体層であってi型a−Si層 5はp型半導体層であってp型a−Si層 6はP層 7は透明導電膜であってCrとPを含む透明導電膜 8はCr膜 9はCr電極であって上部電極 10は窓 11はITO膜 1 is a substrate, glass substrate 2 is a Cr film, lower electrode 3 is an n-type semiconductor layer, n-type a-Si layer 4 is an intrinsic semiconductor layer, and i-type a-Si layer 5 is a p-type The semiconductor layer is a p-type a-Si layer 6, the P layer 7 is a transparent conductive film, and the transparent conductive film containing Cr and P is 8. The Cr film 9 is the Cr electrode, and the upper electrode 10 is the window 11 is ITO. film

Claims (3)

【特許請求の範囲】[Claims] 【請求項1】 基板(1) 上に順に積層された一導電型半
導体層(3) ,真性半導体層(4) ,反対導電型半導体層
(5) ,透明導電膜(7) と,該透明導電膜(7) 上に配置さ
れたクロム電極(9) を有し,該透明導電膜(7) はリンと
クロムを含むことを特徴とする光半導体装置。
1. A one-conductivity-type semiconductor layer (3), an intrinsic semiconductor layer (4), and an opposite-conductivity-type semiconductor layer, which are sequentially stacked on a substrate (1).
(5) having a transparent conductive film (7) and a chromium electrode (9) disposed on the transparent conductive film (7), wherein the transparent conductive film (7) contains phosphorus and chromium. Optical semiconductor device.
【請求項2】 基板(1) 上に一導電型半導体層(3) ,真
性半導体層(4) ,反対導電型半導体層(5) を順に積層す
る工程と,該反対導電型半導体層(5) 表面にリンを付着
した後クロム膜(8) を堆積し, 熱処理により該反対導電
型半導体層(5) と該クロム膜(8) の間にリンとクロムを
含む透明導電膜(7) を形成する工程と,マスクを用いて
該クロム膜(8) を選択的にエッチングして該透明導電膜
(7) を露出する窓(10)を形成する工程とを有することを
特徴とする光半導体装置の製造方法。
2. A step of sequentially laminating a one conductivity type semiconductor layer (3), an intrinsic semiconductor layer (4) and an opposite conductivity type semiconductor layer (5) on a substrate (1), and the opposite conductivity type semiconductor layer (5). ) After depositing phosphorus on the surface, a chromium film (8) is deposited, and a heat treatment is performed to form a transparent conductive film (7) containing phosphorus and chromium between the opposite conductivity type semiconductor layer (5) and the chromium film (8). The step of forming and the transparent conductive film by selectively etching the chromium film (8) using a mask
And (7) a step of forming a window (10) exposing the optical semiconductor device.
【請求項3】 前記一導電型半導体層(3) ,前記真性半
導体層(4) ,前記反対導電型半導体層(5) の積層と該反
対導電型半導体層(5) 表面へのリンの付着はプラズマC
VD法による連続工程で行うことを特徴とする請求項2
記載の光半導体装置の製造方法。
3. A stack of the one conductivity type semiconductor layer (3), the intrinsic semiconductor layer (4), and the opposite conductivity type semiconductor layer (5) and deposition of phosphorus on the surface of the opposite conductivity type semiconductor layer (5). Is plasma C
3. The continuous process according to the VD method is performed.
A method for manufacturing the optical semiconductor device described.
JP4304213A 1992-11-16 1992-11-16 Optical semiconductor device and its manufacture Withdrawn JPH06151912A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4304213A JPH06151912A (en) 1992-11-16 1992-11-16 Optical semiconductor device and its manufacture

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4304213A JPH06151912A (en) 1992-11-16 1992-11-16 Optical semiconductor device and its manufacture

Publications (1)

Publication Number Publication Date
JPH06151912A true JPH06151912A (en) 1994-05-31

Family

ID=17930372

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4304213A Withdrawn JPH06151912A (en) 1992-11-16 1992-11-16 Optical semiconductor device and its manufacture

Country Status (1)

Country Link
JP (1) JPH06151912A (en)

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