JPH0228906B2 - - Google Patents

Description

[Detailed description of the invention]

The present invention relates to a method for manufacturing a photovoltaic device. Photovoltaic devices such as solar cells and photodetectors can directly convert sunlight into electrical energy, but the biggest problem with these devices is that they are expensive compared to other means of generating electrical energy. It is said to be extremely large. The main reasons for this are the low utilization efficiency of semiconductor materials that constitute the main body of the device, and the large amount of energy required to manufacture such materials. However, recently, the use of amorphous silicon as the semiconductor material has been proposed as a technique to solve these drawbacks all at once. In other words, amorphous silicon can be formed cheaply and in large quantities by glow discharge in an atmosphere of silicon compounds such as silane or fluorosilicon (that is, the atmosphere becomes a plasma state). In crystalline silicon (hereinafter abbreviated as GD-aSi), the average localized state density within the width of the forbidden band is as small as 10 ¹⁷ cm ^-3 or less, making it possible to control P-type and N-type impurities in the same way as crystalline silicon. This is the result. FIG. 1 shows a typical conventional solar cell using GD-aSi, in which 1 is a glass substrate that transmits visible light, 2 is a transparent electrode formed on the substrate, 3 and 4 are
and 5 are GDs formed sequentially on the transparent electrode 2, respectively.
-aSi P-type layer, GD-aSi non-doped (no impurity added) layer, and GD-aSi N-type layer, and 6 is an ohmic contact electrode provided on the N-type layer. In the above solar cell, when entering the P-type layer 3, non-doped layer 4 and N-type layer 5 made of GD-aSi via the glass substrate 1 and transparent electrode 2, free state electrons and/or positive electrons mainly exist in the non-doped layer 4. Holes are generated, and after these are attracted and moved by the PIN junction electric field created by the above-mentioned layers, a voltage is generated between the two electrodes collected on the transparent electrode 2 and the ohmic contact electrode 6. By the way, since the photovoltaic voltage of such a solar cell is about 0.8 V, the solar cell cannot be used as is as a power source for equipment that requires a larger power supply voltage. Fig. 2 shows a photovoltaic device that has already been proposed in view of the above points, where 7 is a flat insulating substrate made of glass or the like that can transmit visible light, and 8, 9, and 10 are films on the insulating substrate. These are the first, second, and third power generation areas formed. Each of the power generation areas is composed of a GD-aSi layer 11 and a first electrode 12 and a second electrode 13 facing each other with the layer sandwiched therebetween. Although the GD-aSi layer 1 is not shown, it is a P-type layer deposited sequentially from the substrate 7 side, similar to the structure shown in FIG.
It consists of three layers: a non-doped layer and an N-type layer.
The GD-aSi layer 11 extends continuously from the first to third power generation areas. In each of the above layers constituting the GD-aSi layer 11, the P-type layer has a thickness of 40 to 1000 Å and a doping amount of 0.01 to 1%, the non-doped layer has a thickness of 0.5 to 2 μm,
The N-type layer has a thickness of 200 to 1000 Å, a doping amount of 0.1 to 3%, and the formation temperature of each layer is 200 to 400°C. The first electrode 12 has visible light transmittance and is made of tin oxide,
Indium oxide, Idium oxide/tin oxide (In ₂ O ₃ +
xSnO ₂ , x≦0.1), etc., but indium tin oxide is particularly preferable. The second electrode 13 is made of aluminum, chromium, or the like. The first electrode 12 and the second electrode 13 of each of the first to third power generation zones 8 to 10 have extensions 14 and 15 extending outside the respective power generation zones on the substrate 7, Extension portion 14 of second electrode 13
and the extension 14 of the first electrode 12 of the second power generation zone 2, and the extension 1 of the second electrode 13 of the second power generation zone 9.
5 and an extension 1 of the first electrode 12 of the third power generation zone 10
4 are overlapped and electrically connected to each other. That is, the adjacent first to third power generation areas 8 to 10
are the extensions 14, 1 of the first and second electrodes 12, 13.
5 are electrically connected to each other in a series relationship outside the GD-aSi layer 11 except for the adjacent spacing portions of each of the power generating zones 8 to 10. Also, the first power generation area 8
A connecting portion 16 made of the same material as the second electrode 13 is superimposed on the extension portion 14 of the first electrode 12 . Briefly explaining the manufacturing method of the above device, in the first step each of the first electrodes 12 including the extension portions 14 are formed on the substrate 7 by selective etching or selective sputter deposition, and in the second step the first electrodes 12 are formed on the substrate 7 by selective etching or selective sputter deposition. 1~
A GD-aSi layer 11 is formed continuously in the third power generation area. At this time, the layer is
Therefore, after forming the GD-aSi layer consisting of the above three layers on the entire surface of the substrate 7, the desired portions are removed by selective etching or by using a mask to cover the unnecessary portions. GD-aSi consisting of the above three layers is formed only on the surface.
In the subsequent final step, the second electrode 13 including the extension portion 15 and the connection portion 16 are formed by selective vapor deposition or the like. In the above device, when light enters the GD-aSi layer 11 via the substrate 7 and the first electrode 12, an electromotive voltage is generated in each of the first to third power generation areas 8 to 10 as in the case of FIG. , the first and second electrodes 12 and 13 in each area are connected alternately at their extensions, so the electromotive force in each area is added in series,
The connection part 16 connected to the first power generation area 8 is connected to the + pole, and the third
An extension 15 connected to the second electrode 13 of the power generation area 10
An added voltage is generated between the two poles as described above. In the above device, it is difficult to connect an external lead wire to the extension part 14 connected to the first electrode 12 by ultrasonic bonding or the like due to the properties of the electrode material, but the existence of the connection part 16 makes this easy. It is. According to the above-described device, a plurality of power generation areas are connected in series on the same substrate using amorphous silicon, and a device can be made compact and generate any desired electromotive voltage. The device was realized because it uses amorphous silicon, and its manufacturing process is almost the same as the conventional manufacturing process shown in Figure 1, with only a simple film formation process, making mass production possible. It is also extremely excellent. By the way, in the above device, if the adjacent intervals between the respective power generation areas are small, the first electrodes 12 of the adjacent areas
Although it is recognized that a current flows directly between the second electrodes 13 or between the second electrodes 13, that is, the occurrence of leakage current, the present invention provides a method for obtaining a structure that can substantially suppress such leakage current with high productivity. It is something to do. Embodiments of the manufacturing method of the present invention will be described below in detail with reference to FIGS. 3A and 3B, which are enlarged views of adjacent intervals between adjacent power generation areas, and cross-sectional views of main parts according to steps. Note that the same parts as in FIG. 2 are given the same numbers. FIG. 3A shows the first step, in which the first electrode 12 and the GD-aSi layer 11 are sequentially formed on the substrate 7. That is, a plurality of first electrodes 12, 12, . . . are formed on one surface by a selective etching method or a selective sputter deposition method.
A substrate 7 on which are dividedly arranged in advance is prepared, and this substrate 7 is placed in a glow discharge device, a silicon compound gas is supplied, and a glow discharge is excited.
The gas to be supplied is a silicon compound gas such as silane or fluorosilicone, and as in this embodiment, the gas is
If there is a PIN junction when viewed from the surface side, the P
First, a P-type layer 3 is formed by adding a type impurity gas. Thereafter, a non-doped layer 4 is formed without adding an impurity gas, and finally an N-type layer 5 is deposited by adding an N-type impurity gas. In this way, the P type layer 3, the non-doped layer 4 and the N
The GD-aSi layer 11 consisting of a laminated structure of the mold layer 5 is
The plurality of first electrodes 12, 12, . . . are formed uniformly, ie, continuously, on the exposed surface of the substrate 7 at intervals adjacent to the first electrodes 12, 12, . FIG. 3B shows the second step, in which at least a part of the GD-aSi layer 11 between each power generation area is covered.
Grooves 20 are formed by removing from the surface of the GD-aSi layer 11. A preferred embodiment of this groove formation is performed in the same type of plasma atmosphere as the immediately preceding formation step of the GD-aSi layer 11. A specific example of groove formation carried out in such a plasma atmosphere is to use a reverse sputtering method. That is, as shown in FIG. 3A, a plurality of power generation areas 8, 9, 10
was formed continuously and uniformly across the planned location.
When the substrate 7 provided with the GD-aSi layer 11 is placed in a high-frequency electric field in an argon atmosphere and a glow discharge is excited, the atmosphere becomes a plasma state, and the ionized argon atoms attack the exposed surface of the GD-aSi layer 11. do. Therefore, by positioning and placing a mask, for example a molybdenum mask, on the GD-aSi layer 11 in advance to expose only between adjacent power generation areas, the GD-aSi layer 1 to be exposed can be removed.
1 is sputtered and removed from its surface to form grooves 20. The conditions for reverse sputtering of the GD-aSi layer 11 in which the grooves 20 are to be formed are shown below. -High frequency frequency: 13.56MHz -High frequency output: 1KW -Atmosphere gas: Argon -Standard gas flow rate ratio: 40sccm -Gas pressure: 3×10 ^-3 Torr -Substrate temperature: 100℃ GD-aSi layer 11 under these reverse sputtering conditions
The removal rate (etching rate) is approximately 500
Å/min, and the time is controlled to obtain the desired depth of the groove 20. Another example of groove formation performed in a plasma atmosphere is to use a plasma etch method. That is, as shown in FIG. 3A, a substrate 7 on which a GD-aSi layer 11 is continuously formed uniformly over the planned locations of a plurality of power generation areas 8, 9, and 10 is placed in a fluorocarbon atmosphere. Active ionized fluorine is generated when the atmosphere is made into a plasma state by applying a high frequency electric field, etc. Therefore, by placing a mask similar to the one used in the case of reverse sputtering in advance, the ionized fluorine can be exposed. The GD-aSi layer is etched away from its surface to form grooves 20. The basic conditions of the plasma etching method are described below. -High frequency frequency: 13.56MHz -High frequency output: 300W -Atmosphere gas: CF ₄ +5% _O2 -Standard gas flow rate ratio: 100sccm -Gas pressure: 10 ^-1 Torr -Substrate temperature: 60℃ -Etching rate: 2000Å/min As shown in Figure 3B The depth of the grooves 20 formed in the sections adjacent to each of the power generation areas 8, 9, and 10 is determined as necessary, and the sputtering time and etching time based on the above-mentioned etching rate are required to obtain the grooves 20 of the predetermined depth. Set. The depth of the groove 20 may be set to reach the substrate 7 depending on the case, but the impurity concentration of the N-type layer 5 forming the GD-aSi layer 11 is high, in other words, the resistance value is low, and the Even if the depth is such that the N-type layer 5 is cut off, what remains is a non-doped layer 4 which is not doped with impurities and has an extremely high resistance, and a thin P-type layer 3 with a low impurity concentration, so it is not sufficiently effective. be. FIG. 3C shows the final step, in which a second electrode 13 facing the first electrode 12 is deposited by selective vapor deposition or the like. Note that since FIGS. 3A to 3C show an enlarged view of one adjacent gap where the groove 20 is formed, FIGS.
Although the form of electrical connection between the divided second electrode 13 and the first electrode 12 of the adjacent power generation areas 9 and 10 is not specified, as shown in FIG. power generation areas 8, which extend from the areas 8, 9, and 10 to the side edges other than the adjacent spacing portions, and are adjacent to each other by overlapping at those points;
9 and 10 are connected in series. A comparison is made between a photovoltaic device having grooves 20 at adjacent intervals of each power generation area 8, 9, and 10 manufactured by the manufacturing method of the present invention in this manner and a conventional photovoltaic device having no grooves 20. When the leakage current value was measured for this purpose, it was confirmed that the leakage current value of the conventional photovoltaic device was 13nA or less, which was 1/100th of the conventional value of 1.5nA. The common specifications of the GD-aSi layer 11 used for such comparison are as follows.

[Table] In addition to the above-mentioned common specifications, in the photovoltaic device of the present invention, grooves 20 are formed that penetrate the N-type layer 5 and reach the non-doped layer 4 at adjacent intervals. As is clear from the above description, in the manufacturing method of the present invention, at least a portion of the semiconductor layer located at adjacent intervals between a plurality of power generation areas is removed from the surface thereof, so that an arbitrary electromotive voltage can be obtained. First, leakage current can be effectively suppressed, and the power generation effect can be improved. In addition, if the semiconductor layer is successively formed in a plurality of power generation areas in a plasma atmosphere, and then the semiconductor layer in the adjacent spaced areas is removed in the plasma atmosphere, the process of using the plasma atmosphere can be removed from the previous semiconductor layer. Since this process is the same as the layer forming process, both processes can be carried out consistently, and therefore a leakage current suppression structure between each power generation area can be obtained with extremely high mass production and precision.

[Brief explanation of drawings]

Fig. 1 is a side view showing a conventional device, Fig. 2 A is a plan view showing an already proposed device, Fig. 2 B and C
2A are sectional views taken along lines BB and CC in FIG. 2A, respectively, and FIG. 3 is a sectional view showing a main part of each step showing a method according to an embodiment of the present invention. 7... Insulating substrate, 8, 9, 10... First, second, third power generation areas, 11... Amorphous silicon layer.

Claims (1)

[Scope of Claims] 1. A semiconductor layer on an insulating substrate that includes amorphous silicon that generates electrons and/or holes that contribute to power generation when irradiated with light, and a semiconductor layer on the substrate side that faces the semiconductor layer with the semiconductor layer in between. the semiconductor layer, comprising a plurality of membrane-like power generation areas consisting of one electrode and a second electrode on the front side, wherein the first and second electrodes of the plurality of adjacent membrane-like power generation areas exclude the adjacent interval portions of each power generation area; A method for manufacturing a photovoltaic device in which a plurality of first electrodes are electrically connected to each other in series outside the substrate, the method comprising: dividing and arranging a plurality of first electrodes on a surface of a substrate; a step of uniformly and continuously forming a plurality of first electrodes and their adjacent spaces on the exposed insulating substrate; A photovoltaic device comprising the steps of removing the second electrode from the surface, and dividing and arranging the second electrode to electrically connect adjacent membrane power generation areas at locations other than the adjacent spacing. manufacturing method. 2. The semiconductor layer forming step is performed in a plasma atmosphere, and the semiconductor layer removal step in the adjacent space portion is performed in the same plasma atmosphere following the semiconductor layer forming step. A method for manufacturing a photovoltaic device according to scope 1.