JPH06149702A - Data communication controller - Google Patents

Abstract

PURPOSE:To enable a communication between respective information processors and respective external devices by one controller for small computer system interfaces by controlling data communication requests from the respective external devices with the controller for the small computer system interfaces. CONSTITUTION:The respective information processors DEV1-DEV3 and a core part 10 are connected by optional local lines and an optional communication method is employed. Thus, while a communication means process the communication between the respective information processing means DEV1-DEV3 and one controller (SCSI controller CONT) for the small computer system interfaces through optional local buses, the SCSI controller CONT controls the data communication requests from the respective external device. Therefore, the communication can be processed by the respective information processors and external devices which have small computer system interfaces and one SCSI controller CONT.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data communication control device for controlling data communication between a plurality of information processing devices connected via a SCSI interface and a plurality of external devices.

[0002]

2. Description of the Related Art As OA equipment, a facsimile, a copying machine, a laser beam printer, a file device and the like are independent equipments, and are widely used in offices. Due to improvements in communication processing speed, technological advances in digital copying machines, space saving in offices, etc., a device incorporating a copying machine and a facsimile has appeared in the world.

By the way, SCSI (Small Computation) is used as an interface between this type of device and a host computer.
er System) interface is drawing attention.

[0004]

However, when connecting a host computer and various information processing devices by a SCSI interface, as shown in FIG. 11, each information processing device DEV1 to DEV3 requires SCSI controllers CONT1 to CONT3, respectively. And

FIG. 11 is a block diagram for explaining the interface configuration between the host computer and various information processing devices.

In the figure, HOST1 to HOST3 are host computers, and TM1 and TM2 are terminals.

[0007] Each information processing device DE configured in this way
V1 to DEV3 and host computers HOST1 to HO
In ST3, communication with the host computer is not always performed simultaneously. For example, after the information processing device DEV1 and one of the host computers HOST1 to HOST3 communicate with each other, the information processing device DEV2 and one host computer are communicated with each other. In many cases, serial communication is performed such that one of HOST1 to HOST3 performs communication and, after the communication is completed, communicates with another information processing device.

For this reason, when a plurality of information processing devices are combined, if a SCSI controller must be provided in accordance with the number of connected information processing devices, the cost for the combination is very high. There was a problem that it became expensive.

The present invention has been made to solve the above-mentioned problems, and an inexpensive SCSI system is obtained by integrating SCSI interfaces between a plurality of information processing devices and a plurality of external devices such as host computers. It is an object of the present invention to provide a data communication control device capable of constructing.

[0010]

A data communication control device according to the present invention provides a plurality of information processing means and an arbitrary local bus between the information processing means and the small computer system interface controller. A small computer system interface controller, and a plurality of external devices can be connected to the network.

[0011]

According to the present invention, the communication means performs communication processing between each information processing means and one small computer system interface controller via an arbitrary local bus while the small computer.
Since the system interface controller controls the data communication request from each external device, each information processing device having a small computer system interface and the external device are combined into one small computer.
Communication can be processed by the system interface controller.

[0012]

1 is a block diagram for explaining the structure of an image forming apparatus to which the present invention is applied.

In the figure, 1 is an image input device for converting an original into image data (hereinafter referred to as a reader unit), 2 is a plurality of recording paper cassettes, and image data is recorded on recording paper by a print command. An image output device (hereinafter referred to as a printer unit) for outputting a visible image, 3 is the reader unit 1
It is an external device electrically connected to and has various functions. The external device 3 has a facsimile unit 4, a file unit 5, a man-machine interface unit 6 connected to the file unit 5, a computer interface unit 7 for connecting to a computer, and information from the computer as a visible image. A formatter unit 8 for storing the information, an image memory unit 9 for storing the information from the reader unit 1 or a temporary storage of the information sent from the computer, and a core unit 10 for controlling each function of the above 1 to 8 And so on.

FIG. 2 is a block diagram for explaining the configuration of a data communication control device showing an embodiment of the present invention. The same parts as those in FIG. 1 are designated by the same reference numerals. The core portion 10
1 is connected to a facsimile unit 4, a file unit 5, a computer interface unit 7, a formatter unit 8, an image memory unit 9, a reader unit 1, a printer unit 2, etc., as shown in FIG. A CPU 1003 (details of which will be described later) for controlling

In the figure, COM is a communication device, which is an information processing device DEV1 to DEV1 connected through an arbitrary bus line.
The DEV 3 (any one of the facsimile unit 4, file unit 5, computer interface unit 7, formatter unit 8, image memory unit 9, reader unit 1, printer unit 2, etc.) and the SCSI controller CONT communicate with each other.
The respective information processing devices DEV1 to DEV3 and the core unit 10 are connected by an arbitrary local line and an arbitrary communication method is used.

The CPU 1003 of the core unit 10 communicates with each of the information processing devices DEV1 to DEV3, and the SCSI controller CONT transmits / receives data between the information processing device requiring the SCSI controller CONT and the host computers HOST1 to HOST3. . The CPU 1003 of the core unit 10 and each information processing device DEV1 to DEV3
Data is transmitted / received between each information processing device and the SCSI controller CONT by communication with each other.

In the data communication control device configured as described above, an arbitrary local bus is provided between each of the information processing means DEV1 to DEV3 and one small computer system interface controller (SCSI controller CONT). While the communication means (communication means COM provided in the core unit 10 in this embodiment) performs communication processing, the small computer system interface controller receives data communication requests from the external devices (host computers HOST1 to HOST3). Since the control is performed, each information processing device having the small computer system interface and the external device can be subjected to communication processing by one small computer system interface controller.

The functions of the respective units 1 to 9 will be described in detail below with reference to FIGS.

FIG. 3 is a sectional view showing the construction of the reader unit 1 and the printer unit 2 shown in FIG. The configuration and operation will be described below.

The originals stacked on the original feeding device 101 are sequentially conveyed one by one onto the original table glass surface 102. When the document is conveyed, the lamp 103 of the scanner unit is turned on and the scanner unit 104 moves to irradiate the document. The reflected light of the document is reflected by the mirrors 105, 106, 1
After passing through the lens 108, the light is input to the CCD image sensor unit 109 (hereinafter referred to as CCD).

FIG. 4 is a circuit block diagram showing a signal processing configuration of the reader unit 1 shown in FIG. The configuration and operation will be described below.

The image information input to the CCD 109 is photoelectrically converted here and converted into an electric signal. CCD109
The color information from the following amplifiers 110R, 110G,
At 110B, the signal is amplified according to the input signal level of the A / D converter 111. The output signal from the A / D converter 111 is
Input to the shading circuit 112, where the lamp 1
The light distribution unevenness of No. 03 and the sensitivity unevenness of the CCD 109 are corrected. The signal from the shading circuit 112 is the Y signal generation / color detection circuit 113 and the external I / F switching circuit 11
9 is input. The Y signal generation / color detection circuit 113 calculates the signal from the shading circuit 112 based on the following equation (1) to obtain the Y signal.

Y = 0.3R + 0.6G + 0.1B (1) Further, it has a color detection circuit for separating the R, G, B signals into seven colors and outputting the signals for the respective colors. The output signal from the Y signal generation / color detection circuit 113 is input to the scaling / repeat circuit 114. The scaling in the sub-scanning direction is performed according to the scanning speed of the scanner unit 104, and the scaling / repeat circuit 114 performs scaling in the main scanning direction. Further, the scaling / repeat circuit 114 can output a plurality of identical images. The contour / edge emphasis circuit 115 obtains edge emphasis and contour information by emphasizing a high frequency component of the signal from the scaling / repeat circuit 104. The signal from the contour / edge emphasis circuit 115 is input to the marker area determination / contour generation circuit 116 and the patterning / thickening / masking / trimming circuit 117.

Marker area determination / contour generation circuit 116
Reads the portion of the manuscript written with a marker pen of a specified color and generates the contour information of the marker, and the next patterning / thickening / masking / trimming circuit 117 thickens, masks or trims the contour information. I do. Further, patterning is performed by the color detection signal from the Y signal generation / color detection circuit 113. The output signal from the patterning / thickening / masking / trimming circuit 117 is input to the laser driver circuit 118 and variously processed signals are converted into signals for driving a laser. The signal of the laser driver circuit 118 is input to the printer unit 2 and image formation is performed as a visible image.

Next, the external I / F switching circuit 119 for interfacing with the external device 3 will be described.

When the reader unit 1 outputs image information to the external device 3, the external I / F switching circuit 119 outputs the image information from the patterning / thickening / masking / trimming circuit 117 to the connector 120. When the reader unit 1 inputs image information from the external device 3, the external I
The / F switching circuit 119 inputs the image information from the connector 120 to the Y signal generation / color detection circuit 113.

The above-mentioned respective image information is performed according to the instruction of the CPU 122, and the area generation circuit 121 generates various timing signals necessary for the above-mentioned image processing from the values set by the CPU 122. In addition, communication with the external device 3 is performed using the communication function built in the CPU 122. The sub CPU 123 controls the operation unit 124 and communicates with the external device 3 by using the communication function built in the sub CPU 123.

The configuration and operation of the printer unit 2 will be described below with reference to FIG.

The signal input to the printer unit 2 is converted into an optical signal by the exposure control unit 201 and converted into an image signal by the photosensitive member 2.
02 is irradiated. The latent image formed on the photoconductor 202 by the irradiation light is developed by the developing device 203. The transfer paper is conveyed from the transfer paper 204 or the transfer paper stacking unit 205 at the same timing as the latent image, and the developed image is transferred to the transfer unit 206. The transferred image is
After being fixed on the transfer paper by the fixing unit 207, the paper discharge unit 208
Is discharged to the outside of the device. The transfer paper output from the paper output unit 208 is discharged to each bin when the sort function is working in the sorter 220 or to the highest bin of the sorter when the sort function is not working. .

Next, a method for outputting sequentially read images on both sides of one output sheet will be described.

After the output paper sheet fixed by the fixing section 207 is once conveyed to the paper discharge section 208, the conveyance direction of the paper sheet is reversed, and the re-feeding transfer sheet stacking section 210 is conveyed through the conveyance direction switching member 209. Transport to. When the next manuscript is prepared,
The original image is read in the same manner as in the above process, but since the transfer paper is fed from the re-feed transfer paper stacking unit 210, it is possible to output two original images on the front surface and the back surface of the same sheet. .

The system configuration operation of the external device 3 shown in FIG. 1 will be described below.

The external device 3 is connected to the reader unit 1 by a cable, and the core unit 10 in the external device 3 controls signals and functions. In the external device 3, there are provided an interface between the computer and a facsimile unit 4 for performing facsimile transmission / reception, a file unit 5 for converting various document information into electric signals and storing the same, and a formatter unit 8 for developing code information from the computer into image information. Computer
It comprises an interface section 7, an image memory section 9 for accumulating information from the reader section 1 and temporarily accumulating information sent from a computer, and a core section 10 for controlling the above functions.

The configuration and operation of the core section 10 of the external device 3 will be described below with reference to the block diagram shown in FIG.

FIG. 5 is a block diagram showing a detailed structure of the core portion 10 shown in FIG.

The connector 1001 of the core section 10 is connected to the connector 120 of the reader section 1 by a cable. The connector 1001 contains four types of signals, and the signal 1057 is an 8-bit multilevel video signal. Signal 1
Reference numeral 055 is a control signal for controlling the video signal. The signal 1051 communicates with the CPU 122 in the reader unit 1. The signal 1052 is the sub CPU 123 in the reader unit 1.
Communicate with. Signal 1051 and signal 1052 are communication I
Communication protocol processing is performed in C1002, and CPU bus 10
Communication information is transmitted to the CPU 1003 via 53.

The signal 1057 is a bidirectional video signal line, which enables the core unit 10 to receive information from the reader unit 1 and output the information from the core unit 10 to the reader unit 1. The signal 1057 is the buffer 101.
0, where bidirectional to unidirectional signal 1
058 and signal 1070 are separated. The signal 1058 is
It is an 8-bit multivalued video signal from the reader unit 1 and is input to the LUT 1011 in the next stage. The LUT 1011 converts the image information from the reader unit 1 into a desired value using a look-up table. The output signal 1059 from the LUT 1011 is the binarization circuit 1012 or the selector 1
Input to 013. The binarization circuit 1012 has a simple binarization function for binarizing a multi-valued signal 1059 at a fixed slice level, a binarization function for a variable slice level in which the slice level varies from pixels around a target pixel, and It has a binarization function by the error diffusion method. The binarized information is "00H" when it is "0" and "FFH" when it is "1".
Is converted into a multi-valued signal and input to the selector 1013 at the next stage. The selector 1013 selects the signal from the LUT 1011 or the output signal of the binarization circuit 1012. The output signal 1060 from the selector 1013 is input to the selector 1014. The selector 1014 outputs the output video signals from the facsimile unit 4, the file unit 5, the computer interface unit 7, the formatter unit 8 and the image memory unit 9 to the connectors 1005 and 100, respectively.
6,1007,1008,1009 through the core portion 10
The signal 1064 input to the selector 1013 and the output signal 1060 of the selector 1013 are selected by the instruction of the CPU 1003.
The output signal 1061 of the selector 1014 is the rotation circuit 10
15 or selector 1016. Rotation circuit 1
015 is the input image signal +90 degrees, -90 degrees, +1
It has the function of rotating at 80 degrees.

The rotating circuit 1015 converts the information output from the reader unit 1 into a binary signal by the binarizing circuit 1012, and then stores it in the rotating circuit 1015 as information from the reader unit 1. Next, according to an instruction from the CPU 1003, the rotation circuit 1015 rotates and reads the stored information.
The selector 1016 controls the output signal 10 of the rotation circuit 1015.
62 or the input signal 1061 of the rotating circuit 1015 is selected, and as the signal 1063, the connector 5 with the facsimile unit 4, the connector 100 with the file unit 5, the connector 1007 with the computer interface unit 7,
It outputs to the connector 1008 with the formatter unit 8, the connector 1009 with the image memory unit 9 and the selector 1017.

The signal 1063 is a synchronous 8-bit unidirectional video bus for transferring image information from the core unit 10 to the facsimile unit 4, file unit 5, computer interface unit 7, formatter unit 8 and image memory unit 9. The signal 1064 is a synchronous 8-bit unidirectional video bus for transferring image information from the facsimile unit 4, file unit 5, computer interface unit 7, formatter unit 8 and image memory unit 9. Signal 106
It is the video control circuit 1004 that controls the synchronous bus of the signal 3 and the signal 1064.
The control is performed by the output signal 1056 from the No. 4.

Further, the connectors 1005 to 1009 are provided with
Other signals 1054 are connected respectively. Signal 1054
Is a bidirectional 16-bit CPU bus for exchanging data commands asynchronously. Facsimile section 4, file section 5, computer interface section 7,
To transfer information between the formatter unit 8, the image memory unit 9 and the core unit 10, the above two signals 1063 and 1064 are used.
And the CPU bus 1054.

The signal 1064 from the facsimile unit 4, file unit 5, computer interface unit 7, formatter unit 8 and image memory unit 9 is sent to the selector 1014.
Is input to the selector 1017. Selector 1016
Inputs the signal 1064 to the rotation circuit 1015 at the next stage according to the instruction from the CPU 1003.

The selector 1017 selects the signal 1063 and the signal 1064 according to an instruction from the CPU 1003. The output signal 1065 of the selector 1017 is input to the pattern matching 1 unit 1018 and the selector 1019. The pattern matching 1018 pattern-matches the input signal 1065 with a predetermined pattern, and when the patterns match, outputs a predetermined multi-valued signal to the signal line 1066. If they do not match in the pattern matching processing of the pattern matching 1018, the input signal 1065 is output as the signal 1066.

The selector 1019 outputs the signals 1065 and 1
066 is selected by the instruction of the CPU 1003. The output signal 1067 of the selector 1019 is the LUT 102 of the next stage.
Input to 0. The LUT 1020 converts the input signal 1067 according to the characteristics of the printer when the image information is output to the printer unit 2.

The selector 1021 selects the output signal 1068 and the signal 1065 of the LUT 1020 according to an instruction from the CPU 1003. The output signal of the selector 1021 is input to the expansion circuit 1022 at the next stage. Enlargement circuit 1022
In accordance with an instruction from the CPU 1003, the enlargement ratio can be set independently in the X and Y directions. The expansion method is a first-order linear interpolation method. The output signal 1070 of the expansion circuit 1022 is input to the buffer 1010.

The signal 107 input to the buffer 1010
0 indicates a bidirectional signal 1057 according to an instruction from the CPU 1003.
Then, it is sent to the printer unit 2 via the connector 1001 and printed out.

The signal flow of the core section 10 and each section will be described below. [Processing of Core Unit 10 Based on Information from Facsimile Unit 4] A case of outputting information to the facsimile unit 4 will be described. The CPU 1003 communicates with the CPU 122 of the reader unit 1 via the communication IC 1002 and issues a document scan command. The reader unit 1 outputs image information to the connector 120 when the scanner unit 104 scans a document according to this document scan command. The reader unit 1 and the external device 3 are connected by a cable, and the information from the reader unit 1 is input to the connector 1001 of the core unit 10. Further, the image information input to the connector 1001 is input to the buffer 1010 through the multi-level 8-bit signal line 1057. Buffer 1010 is CP
The unidirectional signal 1058 based on the bidirectional signal 1057 is input to the LUT 1011 according to the instruction of U1003. LUT
At 1011 the image information from the reader unit 1 is converted into a desired value using a look-up table. For example, the background of the original can be skipped. The output signal 1059 of the LUT 1011 is input to the binarization circuit 1012 at the next stage. The binarization circuit 1012 converts the 8-bit multilevel signal 1059 into a binarized signal. The binarization circuit 1012 converts “00H” when the binarized signal is “0” and “FFH” when the binarized signal is “1” into two multilevel signals. The output signal of the binarization circuit 1012 is the selectors 1013, 101.
4 to the rotation circuit 1015 or the selector 1016.

The output signal 1062 of the rotating circuit 1015 is also input to the selector 1016, and the selector 1016 selects either the signal 1061 or the signal 1062. The signal selection is determined by the CPU 1003 communicating with the facsimile section 4 via the CPU bus 1054. The output signal 1063 from the selector 1016 is the connector 1
It is sent to the facsimile unit 4 via 005.

Next, a case of receiving information from the facsimile section 4 will be described.

The image information from the facsimile section 4 is transmitted to the signal line 1064 via the connector 1005. The signal 1064 is generated by the selector 1014 and the selector 10
17 is input. When the image upon facsimile reception is rotated and output to the printer unit 2 according to an instruction from the CPU 1003, the rotation circuit 1015 rotates the signal 1064 input to the selector 1014. The output signal 1062 from the rotation circuit 1015 is the selector 1016, selector 1
It is input to the pattern matching 1018 via 017.

When the image at the time of facsimile reception is output to the printer 2 as it is according to the instruction of the CPU 1003, the signal 1064 input to the selector 1017 is input to the pattern matching 1018.

The pattern matching 1018 has a function (smoothing function) for smoothing the jaggedness of an image when received by facsimile. The pattern-matched signal is sent to the LUT 1020 via the selector 1019.
Entered in. The LUT 1020 can change the table of the LUT 1020 by the CPU 1003 in order to output the image received by facsimile to the printer unit 2 at a desired density. Output signal 1068 of LUT 1020
Is input to the expansion circuit 1022 via the selector 1021. The expansion circuit 1022 has two values (“00H”,
8-bit multi-value data having "FFH") is expanded by a linear interpolation method of the first order. An 8-bit multi-valued signal having many values from the expansion circuit 1022 is sent to the reader unit 1 via the buffer 1010 and the connector 1001. The reader unit 1 sends this signal to the external I / F via the connector 120.
Input to the switching circuit 119. External I / F switching circuit 1
Reference numeral 19 inputs the signal from the facsimile section 4 to the Y signal generation / color detection circuit 113. Y signal generation / color detection circuit 1
The output signal from 13 is subjected to the above-mentioned processing and then output to the printer unit 2 to form an image on an output sheet. [Processing of Core Unit 10 Based on Information from File Unit 5] A case of outputting information to the file unit 5 will be described.

The CPU 1003 communicates with the CPU 122 of the reader unit 1 via the communication IC 1002 and sends a document scan command. The reader unit 1 outputs the image information to the connector 120 when the scanner unit 104 scans the document according to this command. Reader unit 1
The external device 3 and the external device 3 are connected by a cable, and the reader unit 1
Information is input to the connector 1001 of the core unit 10. The image information input to the connector 1001 becomes a unidirectional signal 1058 by the buffer 1010. The signal 1058 which is a multi-valued 8-bit signal is the LUT 1011.
Is converted into a desired signal by. The output signal 1059 of the LUT 1011 is output to the selectors 1013, 1014, 1
It is input to the connector 1006 via 016.

That is, the 8-bit multi-value data is transferred to the file unit 5 as it is without using the functions of the binarization circuit 1012 and the rotation circuit 1015. CPU bus 10 of CPU 1003
When filing the binarized signal by communicating with the file unit 5 via 54, the functions of the binarization circuit 1012 and the rotation circuit 1015 are used. The binarization process and the rotation process are the same as those in the above-mentioned facsimile unit 4, and thus the description thereof will be omitted.

Next, the case of receiving information from the file section 5 will be described.

The image information from the file section 5 is the connector 1
The signal 1064 is input to either the selector 1014 or the selector 1017 via 006. For 8-bit multi-valued filing, to selector 1017; for binary filing, selector 1014 or selector 101
It is possible to input in 7. In the case of binary filing, since the processing is the same as that of the facsimile unit 4, description thereof will be omitted.

In the case of multi-value filing, the selector 10
The output signal 1065 from 17 is input to the LUT 1020 via the selector 1019. In the LUT 1020, a look-up table is created according to the instruction of the CPU 1003 according to the desired print density. The output signal 1068 from the LUT 1020 is input to the expansion circuit 1022 via the selector 1021. 8-bit multilevel signal 1070 expanded to a desired expansion ratio by the expansion circuit 1022
Are sent to the reader unit 1 via the buffer 1010 and the connector 1001. The information of the file section sent to the reader section 1 is output to the printer section 2 and image formation is performed on the output paper, similarly to the operation of the facsimile section 4 described above. [Processing of Core Unit 10 Based on Information from Computer Interface Unit 7] The computer interface unit 7
It interfaces with a computer connected to the external device 3. The computer interface unit 7 is an SCS.
I, RS232C, and a plurality of interfaces for communicating with Centronics system. The computer interface unit 7 has three types of interfaces as described above, and information from each interface is stored in the connector 10
11 to the CPU 1003 via the data bus 1053. The CPU 1003 performs various controls based on the contents sent. [Processing of Core Unit 10 Based on Information from Formatter Unit 8] The formatter unit 8 has a function of expanding command data such as a document file sent from the computer interface unit 7 into image data. C
When the PU 1003 determines that the data sent from the computer interface unit 7 via the data bus 1053 is data regarding the formatter unit 8, the PU 1003 transfers the data to the formatter unit 8 via the connector 1012.
The formatter unit 8 develops the transferred data in the memory as a meaningful image such as characters and figures.

Next, a procedure for receiving information from the formatter unit 8 and forming an image on an output sheet will be described.

The image information from the formatter unit 8 is transmitted as a multi-valued signal having two values ("00H", "FFH") on the signal line 1064 via the connector 1008. The signal 1064 is input to the selector 1014 and the selector 1017. The selectors 1014 and 1017 are controlled by the instruction of the CPU 1003. After that, the operation of is the same as that of the facsimile unit 4, and the description thereof is omitted. [Processing of Core Unit 10 Based on Information from Image Memory Unit 9] A case of outputting information to the image memory unit 9 will be described.

The CPU 1003 communicates with the CPU 122 of the reader unit 1 via the communication IC 1002 to issue a document scan command. The reader unit 1 outputs the image information to the connector 120 when the scanner unit 104 scans the document according to this command. Reader unit 1
The external device 3 and the external device 3 are connected by a cable, and the information from the reader unit 1 is input to the connector 1001 of the core unit 10. The image information input to the connector 1001 is sent to the LUT 1011 via the multilevel 8-bit signal line 1057 and the buffer 1010. The output signal 1059 of the LUT 1011 is output to the selectors 1013, 1014, 10
16. Multivalued image information is transferred to the image memory unit 9 via the connector 1009. The image information stored in the image memory unit 9 is stored in the CPU bus 1054 of the connector 1009.
Is sent to the CPU 1003 via. CPU1003
Transfers the data sent from the image memory unit 9 to the computer interface unit 7 described above. The computer interface unit 7 transfers to a computer (workstation 790 in this embodiment) by a desired interface among the above-mentioned three types of interfaces (SCSI, RS232C, Centronics).

Next, a case where information is received from the image memory unit 9 will be described. First, image information is sent from the computer to the core unit 10 via the computer interface unit 7. The CPU 1003 of the core unit 10
Computer interface unit 7 to data bus 105
The data sent via the image memory unit 9
Connector 1009
To the image memory unit 9 via. Next, the image memory unit 9 outputs the 8-bit multilevel signal 1064 via the connector 1009 to the selector 1014 and the selector 1017.
To transmit. Selector 1014 or Selector 1017
In response to an instruction from the CPU 1003, the output signal from the printer is output to the printer unit 2 and image formation is performed on the output paper, similarly to the facsimile unit 4 described above.

The configuration of the facsimile section 4 shown in FIG. 1 will be described below with reference to the block diagram shown in FIG.

FIG. 6 is a block diagram for explaining the detailed structure of the facsimile section 4 shown in FIG.

The facsimile section 4 is connected to the core section 10 by the connector 400 and exchanges various signals. The binary information from the core unit 10 is stored in the memory A405 to the memory D408.
In the case of storing in any of the above, the signal 453 from the connector 400 is input to the memory controller 404, and under the control of the memory controller 404, any one of the memory A405, the memory B406, the memory C407, and the memory D408, or two sets. It is stored in the memory of cascade connection.

The memory controller 404 is the CPU 41
According to the instruction 2, the mode for exchanging data with the memory A 405, the memory B 406, the memory C 407, the memory D 408 and the CPU bus 462, and the mode for exchanging data with the CODEC bus 463 of the CODEC 411 having an encoding / decoding function. , Memory A405, memory B406, memory C407, memory D408 contents D
The scaling circuit 403 is controlled by the MA controller 402.
Mode for exchanging data with the bus 454 from
A mode in which binary video input data 454 is stored in any one of the memories A405 to D408 under the control of the timing generation circuit 409, and the memories A405 to D40.
Read the memory contents from any one of 8
It has the function of 5 modes in total in the mode output to 52.

Each of the memories A405 to D408 has a capacity of 2 Mbytes and stores an image corresponding to A4 size with a resolution of 400 DPI. The timing generation circuit 409 is connected to the connector 400 by a signal line 459, and controls signals (HSYNC, HSYNC) from the core unit 10.
EN, VSYNC, VEN)
Generate signals to accomplish one function. One is that the image signal from the core unit 10 is sent to the memories A405 to D4.
08, a function of storing in any one memory or two memories, the second is a memory A405 to a memory D40
The image signal is read out from any one of
It is a function to transmit to 52.

The dual port memory 410 is connected to the CPU 1003 of the core unit 10 via the signal line 461 and the CP of the facsimile unit 4 via the signal line 462.
U412 is connected. The CPUs exchange commands via the dual port memory 410. The SCSI controller 413 interfaces with the hard disk connected to the facsimile section 4 shown in FIG. It stores the data when sending and receiving a facsimile. CODEC 411 is
After the image information stored in any of the memories A405 to D408 is read and encoded by a desired method of the MH, MR, and MMR methods, the memories A405 to A405 to
It is stored in any of the memories D408 as encoded information.

Further, the coded information stored in the memories A405 to D408 is read out, and MH, MR, and M are read.
After decoding by the desired MR method, the memory A
405 to memory D 408, and stored as decryption information, that is, image information. MODEM 414 is
NCU 415 and the function of modulating the coded information from the hard disk connected to the CODEC 411 or SCSI controller 413 for transmission on the telephone line.
Demodulates the information sent from, converts it into coded information, and
It has a function of transferring encoded information to a hard disk connected to the ODEC 411 or the SCSI controller 413. The NCU 415 is directly connected to a telephone line and exchanges information with an exchange installed in a telephone office or the like according to a predetermined procedure.

The facsimile transmission processing operation will be described.

The binary image signal from the reader unit 1 is input from the connector 400, passes through the signal line 453, and reaches the memory controller 404. The signal 453 is stored in the memory A 405 by the memory controller 404. The timing for storing in the memory A405 is the reader 1
Timing generation circuit 4 according to timing 459 from
It is generated in 09. The CPU 412 replaces the memory A 405 and the memory B 406 of the memory controller 404 with CO.
It is connected to the bus line 463 of the DEC 411. CODE
The C 411 reads the image information from the memory A 405, encodes it by the MR method, and stores the encoded information in the memory B.
Write to 406.

ODEC41 image information of A4 size
When 1 is encoded, the CPU 412 connects the memory C 406 of the memory controller 404 to the CPU bus 462. The CPU 412 stores the encoded information in the memory B40.
The data is sequentially read from the data No. 6 and transferred to the MODEM 414. M
The ODEM 414 modulates the encoded information, and the NCU
The facsimile information is transmitted to the telephone line via 415.

Next, the facsimile transmission processing operation will be described.

The information sent from the telephone line is NCU.
It is input to the facsimile unit 4 in a predetermined procedure by the NCU 415. Information from NCU 415
It enters the MODEM 414 and is demodulated. The CPU 412 is
Information from the MODEM 414 is stored in the memory C407 via the CPU bus 462. Information on one screen is memory C
When stored in 407, the CPU 412 controls the memory controller 404 to change the data line 457 of the memory C 407 to the line 463 of the CODEC 411.
Connect to. The CODEC 411 sequentially reads the encoded information in the memory C407 and decodes it, that is, stores it in the memory D408 as image information. The CPU 412 is
CP of the core unit 10 via the dual port memory 410
U1003 is communicated with, and settings are made to print out an image from the memory D408 to the printer unit 2 through the core unit. When the setting is completed, the CPU 412 activates the timing generation circuit 409 and outputs a predetermined timing signal from the signal line 460 to the memory controller 404. The memory controller 404 reads the image information from the memory D 408 in synchronization with the signal from the timing generation circuit 409, transmits it to the signal line 452, and outputs it to the connector 400. The operation up to the output from the connector 400 to the printer unit 2 has been described in the operation of the core unit 10, and thus the details will be omitted.

The detailed configuration and operation of the file unit 5 will be described below with reference to the block diagram shown in FIG.

FIG. 7 is a block diagram for explaining the detailed structure of the file unit 5 shown in FIG. The file unit 5 is connected to the core unit 10 by the connector 500 and exchanges various signals. The multi-valued input signal 551 is input to the compression circuit 503, where it is converted from multi-valued image information into compressed information and output to the memory controller 510. The output signal 552 of the compression circuit 503 is output to the memory controller 510.
Under control of memory A 506, memory B 507, memory C
508, the memory D509, or two sets of memories connected in cascade. The memory controller 510 is instructed by the CPU 516 to instruct the memory A 506, the memory B 507, the memory C 508, and the memory D.
509 and the CPU bus 560, a mode for exchanging data with each other, and a CODEC 517 CO for encoding / decoding.
Data exchange mode with the DEC bus 570, memory A506, memory B507, memory C508, memory D
A mode in which the contents of 509 are exchanged with the bus 562 from the scaling circuit 511 under the control of the DMA controller 518, and a signal 563 is sent to the memory A 506, the memory B 507, the memory C 508, and the memory D 509 under the control of the timing generation circuit 514. Mode to be stored in any one, memory A506, memory B507, memory C50
8. It has five functions of a mode of reading the memory contents from any one of the memory D509 and outputting to the signal line 558.

The memory A 506, the memory B 507, the memory C 508, and the memory D 509 each have a capacity of 2 Mbytes and store an image corresponding to A4 at a resolution of 400 DPI. The timing generation circuit 514 uses the connector 500.
Are connected to a signal line 553, and control signals (HSYNC, HEN, VSYNC, VE) from the core unit 10 are connected.
N), it generates signals to accomplish the following two functions: One is a function of storing information from the core unit 10 in one of the memories A506, B507, C508, and D509, or two memories, and the second is a memory A506, a memory B507, and a memory. This is a function of reading image information from any one of the C 508 and the memory D 509 and transmitting it to the signal line 556.

The dual port memory 515 is connected to the CPU 1003 of the core unit 10 via the signal line 554 and the CPU 516 of the file unit 5 via the signal line 560. Each CPU exchanges commands via the dual port memory 515. SCSI
The controller 519 interfaces with the external storage device 6 connected to the file unit 5 of FIG. The external storage device 6 in this embodiment uses a magneto-optical disk (MO) as a storage medium and stores data such as large-capacity image information.

The CODEC 517 reads out the image information stored in any of the memory A 506, the memory B 507, the memory C 508, and the memory D 509, and outputs MH,
After encoding with the desired MR or MMR method,
The encoded information is stored in any of the memory A506, the memory B507, the memory C508, and the memory D509. In addition, the memory A506, the memory B507, the memory C50
8. Read the coded information stored in the memory D509, perform decoding by a desired method of the MH, MR, and MMR methods, and then decode into any of the memory A506, the memory B507, the memory C508, and the memory D509. It is stored as information, that is, image information.

The file information storage processing operation for the external storage device 6 will be described below.

The 8-bit multi-valued image signal from the reader unit 1 is input from the connector 500, passes through the signal line 551, and is input to the compression circuit 503. The signal on the signal line 551 is input to the compression circuit 503, where it is converted into compression information 552. The compressed signal 552 is input to the memory controller 510. Memory controller 51
In the case of 0, the timing generation circuit 514 generates the timing signal 559 by the signal 553 from the core unit 10, and the compressed signal 552 is stored in the memory A 506 according to this signal. The CPU 516 connects the memory A 506 and the memory B 507 of the memory controller 510 to the bus line 570 of the CODEC 517. The CODEC 517 reads the compressed information from the memory A 506, encodes it by the MR method, and writes the encoded information in the memory B 507. When the CODEC 517 finishes encoding, the CPU
516 is the memory B 507 of the memory controller 510.
To the CPU bus 560. The CPU 516 sequentially reads the encoded information from the memory B 507,
Transfer to the SI controller 519. The SCSI controller 519 stores the encoded information 572 in the external storage device 520.

Next, the processing operation for fetching information from the external storage device 520 and outputting it to the printer section 2 will be described.

Upon receiving the information retrieval / printing command, the CPU 516 receives the encoded information from the external storage device 520 via the SCSI controller 519 and transfers the encoded information to the memory C508. At this time, the memory controller 510 changes the CPU bus 560 to the bus 5 of the memory C508 according to an instruction from the CPU 516.
Connect to 66. When the transfer of the encoded information to the memory C508 is completed, the CPU 516 causes the memory controller 5
By controlling memory C508 and memory D
509 to bus 570 of CODEC 517. C
The ODEC 517 reads the encoded information from the memory C 508, sequentially decodes the encoded information, and then transfers the encoded information to the memory D 09.

If a scaling such as enlarging / reducing is required when outputting to the printer unit 2, the memory D509 is replaced with the scaling circuit 5.
11 connected to the bus 562 and the DMA controller 518
The contents of the memory D509 are scaled under the control of. CPU5
16 is the core unit 1 via the dual port memory 515.
The CPU 1003 communicates with the CPU 1003 of No. 0, passes through the core unit 10 from the memory D509, and performs setting for printing out an image to the printer unit 2. When setting is completed, CPU51
6 activates the timing generation circuit 514 and outputs a predetermined timing signal from the signal line 559 to the memory controller 510. The memory controller 510 is
The decoding information is read from the memory D509 in synchronization with the signal from the timing generation circuit 514, and the signal line 55 is read.
6 is transmitted. The signal line 556 inputs to the decompression circuit 504, where the information is decompressed. The output signal 555 of the expansion circuit 504 is output to the core unit 10 via the connector 500. The operation up to outputting from the connector 500 to the printer unit 2 has been described in the processing of the core unit 10 and will be omitted.

The configuration and display processing operation of the computer interface unit 7 shown in FIG. 1 will be described below with reference to the block diagram shown in FIG.

FIG. 8 is a block diagram for explaining the detailed structure of the computer interface section 7 shown in FIG.
Hereinafter, an example of a process of receiving image information from the file unit 5 and displaying it on the display will be described.

Connector A700 and connector B701
Is a connector for SCSI interface. The connector C702 is a Centronics interface connector. The connector D703 is an RS232C interface connector. The connector E707 is a connector for connecting to the core unit 10.

The SCSI interface has two connectors (connector A700 and connector B701). When connecting a device having a plurality of SCSI interfaces, the connectors A700 and B701 are used for cascade connection. When the external device 3 and the computer are connected one-to-one, the connector A700 and the computer are connected with a cable, and the connector B701 is connected with a terminator, or the connector B701 and the computer are connected with a cable and the connector A700 is connected. Connect the terminator. Connector A700 or Connector B70
The information input from the S1 is S via the signal line 751.
It is input to the CSI interface A 704 or the SCSI interface B 708. SCSI interface A 704 or SCSI interface B 708 is S
After performing the procedure according to the CSI protocol, the data is output to the connector 707E via the signal line 754. The connector E707 is the CPU bus 10 of the core unit 10.
54 is connected to the CPU 1003 of the core unit 10.
Receives from the CPU bus 1054 the information input to the SCSI interface connectors (connector A700, connector B701). CPU 100 of core unit 10
When outputting the data from No. 3 to the SCSI interface connector (connector A700, connector B701), the above procedure is reversed.

The Centronics interface is connected to the connector C 702 and input to the Centronics interface 705 via the signal line 752. The Centronics interface 705 receives the data according to the procedure of the determined protocol, and outputs the data to the connector E707 via the signal line 754. Connector E707
Is the CPU bus 1054 of the CPU 1003 of the core unit 10.
CPU 1003 of the core unit 10 is connected to C
The information input to the Centronics interface connector (connector C702) is received from the PU bus 1054.

The RS232C interface is connected to the connector D703 and is connected to the RS2 via the signal line 753.
It is input to the 32C interface 706. RS232
The C interface 706 receives the data according to the procedure of the determined protocol, and outputs the data to the connector E707 via the signal line 754. The connector E707 is connected to the CPU bus 1054 of the core unit 10, and the CPU 1003 of the core unit 10 connects the CPU bus 1054 to the R bus.
S232C interface connector (connector D70
Receive the information entered in 3). CPU of core unit 10
When outputting the data from 1003 to the RS232C interface connector (connector D703), the reverse procedure is performed.

The configuration and operation of the formatter unit 8 shown in FIG. 1 will be described below with reference to the block diagram shown in FIG.

FIG. 9 is a block diagram for explaining the detailed structure of the formatter unit 8 shown in FIG.

Computer interface section 7 described above
Is determined by the core unit 10, and if the data is related to the formatter unit 8, the CP of the core unit 10
The U 1003 transfers data from the computer to the dual port memory 803 via the connector 1008 of the core unit 10 and the connector 800 of the formatter unit 8. The CPU 809 of the formatter unit 8 receives the code data sent from the computer via the dual port memory 803. The CPU 809 sequentially develops this code data into image data, and through the memory controller 808, the memory A 806 or the memory B 80.
Transfer the image data to 7. The memory A 806 and the memory B 807 each have a memory capacity of 1 MB,
One memory (memory A806 and memory B807)
With the resolution of 300 DPI, it is possible to support up to A4 paper size. In the case of supporting up to A3 size paper at a resolution of 300 DPI, the memory A806 and the memory B807 are connected in cascade to develop image data.

The above memory control is performed by the memory controller 808 according to an instruction from the CPU 809. Further, when it is necessary to rotate a character, a graphic, or the like when developing the image data, the image data is rotated by the rotation circuit 804 and then transferred to the memory A 806 or the memory B 807.
When the expansion of the image data in the memory A806 or the memory B807 is completed, the CPU 809 controls the memory controller 808 to control the data bus line 858 of the memory A806 or the data bus line 859 of the memory B807.
Is connected to the output line 851 of the memory controller 808. Next, the CPU 809 uses the dual port memory 8
Communication with the CPU 1003 of the core unit 10 via
The mode for outputting image information from the memory A 806 or the memory B 807 is set. CPU 1003 of core unit 10
Is connected to the reader unit 1 via the communication IC 1002 in the core unit 10.
CPU using the communication function built into the CPU 122 of
The print output mode is set to 122.

When the print output mode is set, the CPU 1003 of the core unit 10 activates the timing generation circuit 802 via the connector 1008 and the connector 800 of the formatter unit 8. Timing generation circuit 80
2 generates a timing signal for reading image information from the memory A 806 or the memory B 807 to the memory controller 808 according to the signal from the core unit 10. The image information from the memory A806 or the memory B807 is
It is input to the memory controller 808 via the signal line 858. The output image information from the memory controller 808 is transferred to the core unit 10 via the signal line 851 and the connector 800. The output from the core unit 10 to the printer unit 2 has been described in the core unit 10 and will not be described.

The structure and operation of the image memory unit 9 shown in FIG. 1 will be described below with reference to the block diagram shown in FIG.

FIG. 10 is a block diagram for explaining the detailed structure of the image memory unit 9 shown in FIG.

The image memory unit 9 is connected to the core unit 10 by the connector 900 and exchanges various signals. The multi-valued input signal 954 is stored in the memory 904 under the control of the memory controller 905. Memory controller 90
5 is a memory 904 and CP according to the instruction of the CPU 906.
A signal 954 is stored in the memory 9 under the control of the timing generation circuit 902 in a mode for exchanging data with the U bus 957.
04, and a mode for outputting the memory contents from the memory 904 to the read signal line 955. The memory 904 has a capacity of 32 Mbytes and stores an image corresponding to A3 with a resolution of 400 DPI and 256 gradations. The timing generation circuit 902 is connected to the connector 900 by a signal line 952, and controls signals (HSYNC, HEN, VSY) from the core unit 10.
NC, VEN) to generate signals to achieve the following two functions. One is a function of storing information from the core unit 10 in the memory 904, and the second is a function of transmitting image information from the memory 904 to the signal line 955. The dual port memory 903 is connected to the CPU 1003 of the core unit 10 via a signal line 953 and the CPU 906 of the image memory unit 9 via a signal line 957. Each CPU exchanges commands via the dual port memory 903.

The operation of storing the image information in the image memory unit 9 and transferring the stored information to the computer will be described below.

The 8-bit multi-valued image signal from the reader unit 1 is input from the connector 900 and input to the memory controller 905 via the signal line 954. The memory controller 905 generates a timing signal 956 in the timing generation circuit 902 in response to the signal 952 from the core unit 10, and stores the signal 954 in the memory 904 in accordance with this signal. The CPU 906 is the memory controller 905.
The memory 904 of the above is connected to the CPU bus 957. CPU
The 906 sequentially reads the image information from the memory 904 and transfers it to the dual port memory 903. Core part 1
The CPU 1003 of 0 sets the image information of the dual port memory 903 of the image memory unit 9 to the signal line 95.
3, read via connector 900 and transfer this information to computer interface 7. The process of transferring information from the computer interface 7 to the computer has already been described in detail and will be omitted.

Next, the operation of outputting the image information sent from the computer to the printer section 2 will be described.

The image information sent from the computer is sent to the core unit 10 via the computer interface unit 7. The CPU 1003 of the core unit 10 is a CPU
Image information is transferred to the dual port memory 903 of the image memory unit 9 via the bus 1054 and the connector 1009. At this time, the CPU 906 controls the memory controller 905 to connect the CPU bus 957 to the memory 904.
Connect to the bus. The CPU 906 sends the image information from the dual port memory 903 to the memory controller 90.
5 to the memory 904. After transferring the image information to the memory 904, the CPU 906 controls the memory controller 905 to connect the data line of the memory 904 to the signal 955. The CPU 906 is the CPU 10 of the core unit 10 via the dual port memory 903.
03, and makes settings for printing an image from the memory 904 through the core unit 10 to the printer unit 2.
When the setting is completed, the CPU 906 activates the timing generation circuit 902 and outputs a predetermined timing signal from the signal line 956 to the memory controller 905.
The memory controller 905 is a timing generation circuit 90.
The image information is read from the memory 904 in synchronism with the signal from the signal line 2 and transmitted to the signal line 955.
Output to. The output from the core unit 10 to the printer unit 2 up to the output from the connector 900 to the printer unit 2 has been described in the core unit 10 and thus will be omitted.

[0101]

As described above, according to the present invention,
While the communication means performs communication processing between each information processing means and one small computer system interface controller via an arbitrary local bus,
Since the small computer system interface controller controls the data communication request from each external device, one small computer system interface controller can perform communication processing for each information processing device and each external device. it can.

Therefore, the conventional small computer
Small in system interface system
Since only one computer system interface controller is required, the systemization cost can be significantly reduced.

[Brief description of drawings]

FIG. 1 is a block diagram illustrating a configuration of an image forming system to which the present invention can be applied.

FIG. 2 is a block diagram illustrating a configuration of a data communication control device showing an embodiment of the present invention.

FIG. 3 is a cross-sectional view showing a configuration of a reader unit and a printer unit shown in FIG.

4 is a circuit block diagram showing a signal processing configuration of a reader unit shown in FIG.

5 is a block diagram showing a detailed configuration of a core unit shown in FIG.

6 is a block diagram illustrating a detailed configuration of a facsimile unit illustrated in FIG.

7 is a block diagram illustrating a detailed configuration of a file unit shown in FIG.

8 is a block diagram illustrating a detailed configuration of a computer interface unit illustrated in FIG.

9 is a block diagram illustrating a detailed configuration of a formatter unit shown in FIG.

FIG. 10 is a block diagram illustrating a detailed configuration of an image memory unit illustrated in FIG.

FIG. 11 is a block diagram illustrating a configuration of a conventional data communication control device.

[Explanation of symbols]

 DEV1 information processing device DEV2 information processing device DEV3 information processing device HOST1 host computer HOST2 host computer HOST3 host computer COM communication device CONT SCSI controller

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Kunio Yoshihara 3-30-2 Shimomaruko, Ota-ku, Tokyo Canon Inc.

Claims (1)

[Claims] 1. A plurality of information processing means, and a communication means for performing communication processing between these information processing means and a small computer system interface controller via an arbitrary local bus, Small·
A data communication control device comprising a controller for a computer system interface and a plurality of external devices connected to a network.