JPH05136934A - Image forming system - Google Patents

Abstract

PURPOSE:To set a function processing condition with respect to a desired function processing means from each operation section. CONSTITUTION:The function processing condition to 1st-4th function processing means (1st function processing means consists of a reader section 2, a 2nd function processing means consists of a work station 790 and a formatter section 8, a 3rd function processing means consists of a facsimile equipment section 4 and a 4th function processing means consists of an image memory section 9 and a core section 10) is set and entered by using a work station 790, a key board 619 of a file section 5 and an operation panel of a reader section 1 or the like.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to, for example, a copy processing function,
The present invention relates to an image forming system capable of executing composite functions such as a facsimile processing function, a print processing function, and a file function processing.

[0002]

2. Description of the Related Art As OA equipment, a facsimile machine, a copying machine, a laser beam printer, a file device and the like are independent equipments and are widely used in offices. Due to improvements in communication processing speed, technological advances in digital copying machines, space saving in offices, etc., a device in which a copying machine and a facsimile are integrated has appeared in the world.

[0003]

However, the functions of the combined device are only some combinations of the above-mentioned facsimile, copying machine, laser beam printer, and file device, and a system capable of executing all the functions is not available. Since it does not exist, the fundamental problem of having to have multiple individual kitchens for each application has not been resolved. Further, since the setting of the operation mode for each facsimile, copying machine, laser beam printer, and file device is limited to the setting from the operation unit provided in each system or the information input from the outside,
The user is forced to set the desired operation mode in each system, resulting in a considerable operational burden until the desired image is processed and output, and the final operation depends on the number of function processing means configured in the system. There is an operational problem that it takes a considerable amount of time to obtain a desired image output.

The present invention has been made in order to solve the above-mentioned problems, and each function processing means constructed by combining them is provided with a function processing condition of another function processing means different from its own function processing means. It is an object of the present invention to obtain an image forming system having excellent operability, in which the setting operation can be input from each operation unit, and the function processing condition for a desired function processing unit can be set from each operation unit.

[0005]

In the image forming system according to the present invention, operation means capable of inputting functional processing conditions for the first to fourth functional processing means respectively correspond to the first to fourth functional processing means. And a plurality of them are provided.

[0006] Further, the determination means for determining the competitive use request occurrence state for each of the first to fourth functional processing means set and input from each operation means, and each operation means based on the determination result of this determination means. The control means for controlling the function processing condition input order for each of the first to fourth function processing means based on the priority order that can be arbitrarily set is provided.

Further, the control means has the first to fourth settings input from each operation means based on the determination result of the determination means.
The input order of each function processing condition to each function processing means is controlled based on the use request input timing to the first to fourth function processing means input from each operation means.

Further, the control means, based on the determination result of the determination means, requests the use by each operating means corresponding to each of the first to fourth function processing means one by one rather than the use request by the other operating means. The priority order of inputting the respective functional processing conditions to the first to fourth functional processing means is determined so as to give priority.

Further, the control means has the first to fourth input from the specific operation means based on the determination result of the determination means.
It is configured to invalidate the use request to each function processing means.

The first to fourth function processing means are
It is configured such that each functional process can be executed in parallel.

[0011]

In the present invention, the first to fourth operation means are used.
It is possible to set and input the function processing condition for each function processing means, and it is possible to set each function processing condition for each of the first to fourth function processing means from each operation means.

Further, when the judging means judges the competitive use request occurrence state for each of the first to fourth function processing means set and inputted from each operating means, the control means judges based on the judgment result of the judging means. The order of inputting the functional processing conditions to the first to fourth functional processing means by each operating means is controlled based on the priority order that can be arbitrarily set, and the operating requests conflict with one functional processing means from each operating means. However, it is possible to sequentially set the functional processing conditions according to the desired priority order.

Further, the control means has the first to fourth settings input from each operation means based on the determination result of the determination means.
The order of inputting the respective functional processing conditions for the respective functional processing means is controlled based on the use request input timings for the first to fourth functional processing means input from the respective operating means, and one functional processing means from each operating means. Even if the usage requests conflict with each other, the function processing conditions can be sequentially set in the order of the usage request input from each operating means.

Further, the control means, based on the judgment result of the judging means, makes a request for use by each operation means corresponding to each of the first to fourth function processing means one to one rather than a request for use by other operation means. It is possible to prioritize the setting of the functional processing conditions by the operating means corresponding to the respective functional means by determining the input order of the respective functional processing conditions for the first to fourth functional processing means so as to give priority.

Further, the control means has the first to fourth input from the specific operation means based on the determination result of the determination means.
It is configured to invalidate the use request for each function processing means of (1), and it is possible to arbitrarily differentiate the use request for each of the first to fourth function processing means by each operating means.

The first to fourth function processing means are
Each of the functional processes is configured to be executable in parallel, and when the usage requests for the functional processing units do not conflict with each other, the first to fourth
It is possible to perform parallel processing on each of the functional processing means.

[0017]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a block diagram illustrating the configuration of an image forming system showing an embodiment of the present invention.

In the figure, 1 is an image input device for converting a document into image data (hereinafter referred to as a reader unit), 2 is a plurality of recording paper cassettes, and image data is visible on the recording paper by a print command. An image output device (hereinafter referred to as a printer unit) for outputting as an image, 3 is the reader unit 1
It is an external device electrically connected to and has various functions. The external device 3 has a facsimile unit 4, a file unit 5, a man-machine interface unit 6 connected to the file unit 5, a computer interface unit 7 for connecting to a computer, and information from the computer as a visible image. A formatter unit 8 for storing the information, an image memory unit 9 for storing the information from the reader unit 1 or a temporary storage of the information sent from the computer, and a core unit 10 for controlling each function of the above 1 to 8 And so on.

In the image forming system configured as described above, the first to fourth operation means (in this embodiment, the work station 790, the keyboard 619 of the file unit 5, the display 608, the operation panel of the reader unit 1, etc.) are used.
(In the present embodiment, the first function processing means is composed of the reader section 1, the second function processing means is composed of the workstation 790 and the formatter section 8, and the third function processing means is a facsimile. (The fourth function processing means is configured by the file unit 5), and the function processing conditions for the (4) function processing means can be set and input, and the respective functions for the first to fourth function processing means from the respective operating means are set. Allows setting of processing conditions.

Further, when the judging means (CPU of the core section 10) judges the competitive use request occurrence state for each of the first to fourth function processing means set and inputted from each operating means, the control means (core The CPU of the section 10) controls the first to fourth operation means based on the determination result of the determination means.
The function processing condition input order for each of the function processing means is controlled on the basis of the priority order that can be arbitrarily set, and even if the usage requests from each operation means compete with one function processing means, according to the desired priority order. Enables setting of sequential function processing conditions.

Further, control means (CPU of core unit 10)
Is a first order input from each operation means of the input order of each function processing condition for each of the first to fourth function processing means set and input from each operation means based on the determination result of the determination means.
To the fourth function processing means, the control is performed based on the use request input timing, and even if the use requests from each operation means compete with one function processing means, the function processing is sequentially performed in the order of use request input from each operation means. Allows setting of conditions.

Control means (CPU of core unit 10)
Is 1 to 1 for each of the first to fourth function processing units based on the determination result of the determination unit rather than the usage request by the other operation unit.
The order of inputting the respective functional processing conditions for the first to fourth functional processing means is determined so as to give priority to the use request by the respective operating means corresponding to the above, and the functional processing conditions are set by the operating means corresponding to the respective functional means. Can be re-prioritized.

Further, control means (CPU of core unit 10)
Is configured to invalidate the use request for each of the first to fourth function processing means input from the specific operation means based on the determination result of the determination means, and the first operation performed by each operation means.
It is possible to arbitrarily differentiate the use request for each of the fourth function processing means.

The first to fourth function processing means are
Each of the functional processes is configured to be executable in parallel, and when the usage requests for the functional processing units do not conflict with each other, the first to fourth
It is possible to perform parallel processing on each of the functional processing means.

The functions of the respective units 1 to 8 will be described in detail below.

FIG. 2 is a sectional view showing the construction of the reader unit 1 and the printer unit 2 shown in FIG. The configuration and operation will be described below.

The originals stacked on the original feeding device 101 are sequentially conveyed one by one onto the original table glass surface 102. When the document is conveyed, the lamp 103 of the scanner unit is turned on and the scanner unit 104 moves to illuminate the document. The reflected light of the document is reflected by the mirrors 105, 106, 1
After passing through the lens 108, the light is input to the CCD image sensor unit 109 (hereinafter referred to as CCD).

FIG. 3 is a circuit block diagram showing a signal processing configuration of the reader unit 1 shown in FIG. The configuration and operation will be described below.

The image information input to the CCD 109 is photoelectrically converted here and converted into an electric signal. CCD109
The color information from the following amplifiers 110R, 110G,
At 110B, the signal is amplified according to the input signal level of the A / D converter 111. The output signal from the A / D converter 111 is
Input to the shading circuit 112, where the lamp 1
The light distribution unevenness of No. 03 and the sensitivity unevenness of the CCD 109 are corrected. The signal from the shading circuit 112 is generated by the Y signal generation / color detection circuit 113 and the external I / F switching circuit 11
9 is input. The Y signal generation / color detection circuit 113 calculates the signal from the shading circuit 112 based on the following equation (1) to obtain the Y signal.

Y = 0.3R + 0.6G + 0.1B (1) Further, it has a color detection circuit for separating the R, G, B signals into seven colors and outputting the signals for the respective colors. The output signal from the Y signal generation / color detection circuit 113 is input to the scaling / repeat circuit 114. Scaling in the sub-scanning direction is performed according to the scanning speed of the scanner unit 104, and scaling in the main scanning direction is performed by the scaling / repeat circuit 114. Further, the scaling / repeat circuit 114 can output a plurality of identical images. The contour / edge emphasis circuit 115 obtains edge emphasis and contour information by emphasizing a high frequency component of the signal from the scaling / repeat circuit 114. The signal from the contour / edge emphasis circuit 115 is input to the marker area determination / contour generation circuit 116 and the patterning / thickening / masking / trimming circuit 117. The marker area determination / contour generation circuit 116 reads a portion of a document written with a marker pen of a designated color to generate contour information of a marker, and the next patterning / thickening / masking / trimming circuit 117 uses this contour. Thicken, mask and trim information. Further, patterning is performed by the color detection signal from the Y signal generation / color detection circuit 113. Patterning / Thickening / Masking / Trimming circuit 117
The output signal from is converted into a signal for driving the laser, which is input to the laser driver circuit 118 and variously processed. The signal from the laser driver circuit 118 is input to the printer unit 2 and image formation is performed as a visible image.

Next, the external I / F switching circuit 119 for interfacing with an external device will be described.

When outputting image information from the reader unit 1 to the external device 3, the external I / F switching circuit 119 outputs the image information from the patterning / thickening / masking / trimming circuit 117 to the connector 120. When the reader unit 1 inputs image information from the external device 3, the external I
The / F switching circuit 119 inputs the image information from the connector 120 to the Y signal generation / color detection circuit 113.

The above-mentioned respective image information is performed according to the instruction of the CPU 122, and the area generation circuit 121 generates various timing signals necessary for the above-mentioned image processing from the values set by the CPU 122. In addition, communication with the external device 3 is performed using the communication function built in the CPU 122. The sub-CPU (SUBCPU) 123 controls the operation unit 124 and communicates with the external device 3 by using the communication function built in the sub-CPU.

The configuration and operation of the printer unit 2 will be described below with reference to FIG.

The image signal input to the printer unit 2 is converted into an optical signal by the exposure control unit 201 and irradiates the photoconductor 202. The latent image formed on the photoconductor 202 by the irradiation light is developed by the developing device 203. The transfer paper 204 or the transfer paper stacking unit 2 is timed with the latent image.
The transfer paper is conveyed from 05, and the developed image is transferred at the transfer unit 206. The transferred image is fixed on the transfer paper by the fixing unit 207, and then discharged from the paper output unit 208 to the outside of the apparatus. The transfer paper output from the paper output unit 208 is discharged to each bin when the sort function is working in the sorter 220 or to the highest bin of the sorter when the sort function is not working. .

Next, a method for outputting sequentially read images on both sides of one output sheet will be described.

After the output sheet fixed by the fixing section 207 is once conveyed to the sheet discharge section 208, the conveyance direction of the sheet is reversed and the transfer sheet for re-feeding is conveyed through a conveyance direction switching member (flapper) 209. The sheet is conveyed to the stacking unit 210. When the next original is prepared, the original image is read in the same manner as the above process, but the transfer paper is re-fed.
Since the paper is fed more, it is 2
It is possible to output one original image.

The system configuration operation of the external device 3 shown in FIG. 1 will be described below.

The external device 3 is connected to the reader unit 1 by a cable, and the core unit in the external device 3 controls signals and controls each function. The external device 3 includes an interface between a computer, a facsimile unit 4 for transmitting / receiving a facsimile, a file unit 5 for converting various document information into electric signals and storing the same, a formatter unit 8 for developing code information from a computer into image information, and a computer. The information from the computer interface unit 7 and the reader unit 1 is stored,
It comprises an image memory unit 9 for temporarily storing information sent from a computer and a core unit 10 for controlling the above-mentioned functions.

The configuration and operation of the core section 10 of the external device 3 will be described below with reference to the block diagram shown in FIG.

FIG. 4 is a block diagram showing a detailed structure of the core section 10 shown in FIG.

The connector 1001 of the core unit 10 is connected to the connector 120 of the reader unit 1 by a cable. The connector 1001 contains three types of signals, and the signal 1054 is an 8-bit multivalued video signal and a video control signal. The signal 1051 is the CPU in the reader unit 1.
122 to communicate. The signal 1052 communicates with the sub CPU 123 in the reader unit 1. Signal 1052 and signal 1
A communication protocol processing 053 is performed by the communication IC 1002 and transmits communication information to the CPU 1003 via the CPU bus 1053.

Reference numeral 1054 denotes a bidirectional signal line, which enables the core unit 10 to receive information from the reader unit 1 and output information from the core unit 10 to the reader unit 1. The signal line 1054 is a binarization circuit 1004.
It is connected to the connectors 1010 and 1013. The connector 1010 is connected to the file unit 5, and the connector 1013 is connected to the image memory unit 9.

The binarization circuit 1004 is connected to the signal line 105.
It has a function of converting an 8-bit multilevel signal received via 4 into a binary signal. The binarization circuit 1004 has a simple binarization function for binarizing a multi-valued signal received via the signal line 1054 at a fixed slice level, and the slice level varies from the values of pixels around the pixel of interest. It has a binarization function by the variable slice level and a binarization function by the error diffusion method. Output signal 1055 of the binarization circuit 1004
Is input to the rotating circuit 1005 and the selector 1008.

The rotating circuit 1005 functions together with the memory 1006, and after the information output from the reader unit 1 is converted into a binary signal by the binarizing circuit 1004 via the connector 1001, it is controlled by the rotating circuit 1005. Memory 1006
The information from the reader unit 1 is stored in. Next, the CPU 10
The rotation circuit 1005 causes the memory 10
The information from 06 is rotated and read. Rotating circuit 1005
The output signal 1056 of 1 is input to the expansion circuit 1007.

The enlargement circuit 1007 first converts the binary signal of the output signal 1056 into a multi-valued signal. When "0", "0
0H (H is a hexadecimal notation) "and converted to" FFH "when the output signal 1056 is" 1 ". Enlargement circuit 1007
In accordance with an instruction from the CPU 1003, the enlargement ratio can be set independently in the X and Y directions. The expansion method is a linear interpolation method of the first order. The output signal 1054 of the expansion circuit 1007 is the connector 1001 or the connector 1010, the connector 1013 according to an instruction from the CPU 1003.
Entered in.

The output signal 1055 of the binarization circuit 1004 and the output signal 1056 of the rotation circuit 1005 are the selector 100.
8 and is selected by the instruction of the CPU 1003. The output signal 1058 of the selector 1008 is connected to the connector 1009, the connector 1010, and the connector 1012.

The CPU bus 1053 is the CPU 1003.
Communication IC 1002, connector 1009, connector 101
0, connector 1011, connector 1012, connector 1
It is connected to 013. CPU 1003 is a communication IC
Communication with the reader unit 1 is performed via 1002. Also, C
The PU 1003 communicates with the facsimile unit 4 via the connector 1009. Similarly, communication is performed with the file unit 5 via the connector 1010, the computer interface unit 7 via the connector 1011, the formatter unit 8 via the connector 1012, and the image memory unit 9 via the connector 1013.

The signal flow of the core section 10 and each section will be described below. [Processing of Core Unit 10 Based on Information from Facsimile Unit 4] A case of outputting information to the facsimile unit 4 will be described. The CPU 1003 communicates with the CPU 122 of the reader unit 1 via the communication IC 1002 and issues a document scan command. The reader unit 1 outputs image information to the connector 120 when the scanner unit 104 scans a document according to a document scan command. The reader unit 1 and the external device 3 are connected by a cable, and the information from the reader unit 1 is input to the connector 1001 of the core unit 10. Further, the image information input to the connector 1001 is input to the binarization circuit 1004 through the signal line 1054. The binarization circuit 1004 converts an 8-bit multilevel signal into a binarized signal. The binarized signal 1055 is input to the selector 1008 or the rotation circuit 1005. The output of the rotation circuit 1005 is input to the selector 1008 via the signal line 1056, and the selector 1008 selects either the signal line 1055 or the signal line 1056. The signal is selected by the CPU 1003 on the data bus 10
It is determined by communicating with the facsimile unit via 53. The binarized signal from the selector 1008 is sent to the facsimile section 4 via the signal line 1058 and the connector 1009.

Next, the case of receiving information from the facsimile section 4 will be described.

The image information from the facsimile section 4 is transmitted via the connector 1009 as a binary signal to the signal line 10.
58. The selector 1008 is a CPU
According to the instruction of 1003, the signal is output to the signal line 1055 or the signal line 1056 via the signal line 1058.
When the signal 1055 is selected, the binarized signal from the facsimile unit 4 is rotated by the rotating circuit 1005 and then input to the next enlarging circuit 1007. When the signal 1056 is selected as the output signal from the selector 1008, it is directly input to the enlarging circuit 1007 without undergoing the rotation processing. The enlargement circuit 1007 converts the binary signal into an 8-bit multivalue and then performs an enlargement process by a linear interpolation method of the first order. The 8-bit multilevel signal from the expansion circuit 1007 is sent to the reader unit 1 via the connector 1001. The reader unit 1 inputs this signal to the external interface switching circuit 119 via the connector 120. The external interface switching circuit 119 inputs the signal from the facsimile section 4 to the Y signal generation / color detection circuit 113. The output signal from the Y signal generation / color detection circuit 113 is processed as described above and then output to the printer unit 2 to form an image on an output sheet. [Processing of Core Unit 10 Based on Information from File Unit 5] A case of outputting information to the file unit 5 will be described.

The CPU 1003 communicates with the CPU 122 of the reader unit 1 via the communication IC 1002 and sends a document scan command. The reader unit 1 outputs the image information to the connector 120 by the scanner unit 104 scanning the document according to this command. Reader unit 1
The external device 3 and the external device 3 are connected by a cable, and the reader unit 1
Information is input to the connector 1001 of the core unit 10. The image information input to the connector 1001 passes through the multilevel 8-bit signal line 1054 and the connector 101.
0 or input to the binarization circuit 1004. When the file section 5 compresses and filing 8-bit multivalued information, the information of the signal line 1054 is sent to the file section 5 via the connector 1010. When the file unit 5 compresses binary information for filing, the binarization circuit 1004 performs binarization. The binarization process and the rotation process are the same as in the case of the facsimile unit 4 described above, and therefore description thereof will be omitted.

The binarized output signal from the selector 1008 is sent to the file unit 5 via the signal line 1058 and the connector 1010.

Next, the case of receiving information from the file section 5 will be described. The image information from the file unit 5 is transmitted via the connector 1010 to the signal line 1054 in the case of an 8-bit multilevel signal and to the signal line 1058 in the case of a binary signal. The signal line 1054 is sent to the reader unit 1 via the connector 1001. The signal on the signal line 1058 is input to the selector 1008. The selector 1008 sets the signal line 1058 to the signal 1055 or the signal 1056 according to an instruction from the CPU 1003.
Output to. When the signal 1055 is selected, it is rotated and then input to the next enlarging circuit 1007. When the signal 1056 is selected as the output signal from the selector 1008, it is directly input to the enlarging circuit 1007 without undergoing the rotation processing. The 8-bit multilevel signal from the expansion circuit 1007 is sent to the reader unit 1 via the connector 1001.
The information of the file section sent to the reader section 1 is output to the printer section 2 and image formation is performed on the output paper, as in the above-mentioned facsimile section 4. [Processing of Core Unit 10 Based on Information from Computer Interface Unit 7] The computer interface unit 7
It interfaces with a computer connected to the external device 3. The computer interface unit 7 is an SCS.
I, RS232C, and a plurality of interfaces for communicating with Centronics system. The computer interface unit 7 has three types of interfaces as described above, and information from each interface is stored in the connector 10
11 to the CPU 1003 via the data bus 1053. The CPU 1003 performs various controls based on the sent contents. [Processing of Core Unit 10 Based on Information from Formatter Unit 8] The formatter unit 8 has a function of expanding command data such as a document file sent from the computer interface unit 7 into image data. C
When the PU 1003 determines that the data sent from the computer interface unit 7 via the data bus 1053 is data related to the formatter unit 8, the PU 1003 transfers the data to the formatter unit 8 via the connector 1012.
The formatter unit 8 develops the transferred data in the memory as a meaningful image such as characters and figures. Next, a procedure for receiving information from the formatter unit 8 and forming an image on an output sheet will be described.

The image information from the formatter unit 8 is transmitted to the signal line 1058 via the connector 1012 as a binary signal. The signal on the signal line 1058 is input to the selector 1008. The selector 1008 is C
According to an instruction from the PU 1003, the signal 1055 or the signal 1056 is output via the signal line 1058. Signal 1
If 055 is selected, it is rotated and then input to the next enlarging circuit 1007. When the signal 1056 is selected as the output signal from the selector 1008, it is directly input to the enlarging circuit 1007 without undergoing the rotation processing. The 8-bit multilevel signal from the expansion circuit 1007 is the connector 100
1 to the reader unit 1. The information of the formatter unit 8 sent to the reader unit 1 is output to the printer unit 2 and image formation is performed on the output paper as in the above-described facsimile unit 4. [Processing of Core Unit 10 Based on Information from Image Memory Unit 9] A case of outputting information to the image memory unit 9 will be described. The CPU 1003 communicates with the CPU 122 of the reader unit 1 via the communication IC 1002 and issues a document scan command. The reader unit 1 causes the scanner unit 104 to scan the document according to this command,
The image information is output to the connector 120. The reader unit 1 and the external device 3 are connected by a cable, and the information from the reader unit 1 is input to the connector 1001 of the core unit 10. The image information input to the connector 1001 is multivalued 8
It is sent to the image memory unit 9 via the bit signal line 1054 and the connector 1013. The image information stored in the image memory unit 9 is sent to the CPU 1003 via the data bus of the connector 1013. CPU10
03 transfers the data sent from the image memory unit 9 to the computer interface unit 7 described above.
The three types of interfaces mentioned above, namely SCSI,
Transfer to the computer with a desired interface of RS232C and Centronics.

Next, the case of receiving information from the image memory unit 9 will be described.

First, image information is sent from the computer to the core unit 10 via the computer interface unit 7. When the CPU 1003 of the core unit 10 determines that the data sent from the computer interface unit 7 via the data bus 1053 is the data related to the image memory unit 9, the CPU 1003 transfers the data to the image memory unit 9 via the connector 1013. Next, the image memory unit 9
The 8-bit multilevel signal is transmitted to the signal line 1054 via the connector 1013. The signal line 1054 is sent to the reader unit 1 via the connector 1001. Reader unit 1
The information in the image memory unit 9 sent to the printer is output to the printer unit 2 and image formation is performed on the output paper, similarly to the facsimile unit 4 described above.

The configuration of the facsimile section 4 shown in FIG. 1 will be described below with reference to the block diagram shown in FIG.

FIG. 5 is a block diagram for explaining the detailed structure of the facsimile section 4 shown in FIG.

The facsimile section 4 is connected to the core section 10 by the connector 400 and exchanges various signals. The signal 451 is a bidirectional binary image signal (bidirectional signal), and the buffer 401 separates the bidirectional signal 451 into a signal line 452 from the facsimile unit 4 and an input signal line 453 to the facsimile unit 4. .. The signal line 452 and the signal line 453 are input to the selector 402, and the selector 402 selects according to an instruction from the CPU 412. When the binary information from the core unit 10 is stored in any of the memories A405 to D408, the selector 4
02 selects the signal line 453. Also, one memory (any one of the memories A405 to D408
To transfer data from one) to another memory, the selector 402 selects the signal line 452. The output signal of the selector 402 is input to the scaling circuit 403 via the signal line 453 and subjected to scaling processing. Scaling circuit 40
When transmitting the reading resolution 400 DPI of the reader unit 1 by facsimile, the resolution 3 is converted according to the facsimile on the receiving side. The output signal of the scaling circuit 403 is stored via the signal line 454 under the control of the memory controller to any one of the memory A405, the memory B406, the memory C407, and the memory D408, or a combination of two sets of memories connected in cascade. .. Memory controller 40
4 is a memory A405, a memory B406, a memory C407, a memory D408 and a CP according to an instruction from the CPU 412.
CODEC of CODEC 411 having a mode for exchanging data with the U bus 462 and an encoding / decoding function
In the mode for exchanging data with the bus 463 and under the control of the timing generation circuit 409, binary video input data is stored in any one of the memory A405, the memory B406, the memory C407, and the memory D408 via the signal line 454. Mode and memory A405, memory B406,
It has four functions of a mode in which the memory content is read from either the memory C407 or the memory D408 and output via the read signal line 452. Memory A405, memory B4
06, memory C407, and memory D408 are each 2
It has a capacity of M bytes and stores an image equivalent to A4 at a resolution of 400 DPI. The timing generation circuit 409 is connected to the connector 400 via a signal line 459, and has control signals HSYNC, HEN, VSYN from the core unit 10.
It is activated by C, VEN and generates signals to achieve the following two functions. First, the image signal from the core unit 10 is sent to the memory A405, the memory B406, and the memory C4.
07, one of the memories D408, or 2
The function of storing in one memory, the second is the memory A405,
It is a function of transmitting from any one of the memory B406, the memory C407, and the memory D408 to the read signal line 452. The dual port memory 410 has a signal line 4
It is connected to the CPU 1003 of the core unit 10 via 61 and the CPU 412 of the facsimile unit 4 via a signal line 462. Each CPU is a dual port memory 4
Commands are exchanged via 10. The SCSI controller 413 interfaces with the hard disk connected to the facsimile section 4 shown in FIG. It also stores data at the time of facsimile transmission and facsimile reception. CODEC 411 is a memory A
405, memory B406, memory C407, memory D4
After reading the image information stored in any one of 08, and performing encoding by a desired method of the MH, MR, and MMR methods, the memory A405, the memory B406, and the memory C
407 or memory D 408 and stores it as encoded information. Further, after the encoded information stored in the memory A405, the memory B406, the memory C407, and the memory D408 is read and decoded by a desired method of the MH, MR, and MMR methods, the memory A405 and the memory B40 are read.
6, stored in one of the memory C407 and the memory D408 as decryption information, that is, image information. MODE
The M414 has a function of modulating the coded information from the hard disk connected to the CODEC 411 or the SCSI controller 413 so as to transmit the coded information on the telephone line.
The information sent from the NCU 415 is demodulated and converted into coded information, and the coded information is transferred to the hard disk connected to the CODEC 411 or the SCSI controller 413. The NCU 415 exchanges information with a switching system installed directly at a telephone station or the like by being directly connected to a telephone line according to a predetermined procedure.

An example of the facsimile transmission process will be described below.

The binarized image signal from the reader unit 1 is input from the connector 400 and the signal line 451 to the buffer 401. The buffer 401 is the CPU 412
The signal on the signal line 451 is set to the signal line 4 according to the setting of
Output to 53. The signal on the signal line 453 reaches the scaling circuit 403 after being input to the selector 402. The scaling circuit 403 converts the resolution of 400 DPI of the reader unit 1 into the resolution of facsimile transmission. Magnification circuit 403
The output signal from is stored in memory A 405 by memory controller 404 via signal line 454.
As for the timing to be stored in the memory A 405, the timing signal from the reader unit 1 is generated by the timing generation circuit 409 via the signal line 459. The CPU 412 is
The memory A 405 and the memory B 406 of the memory controller 404 are connected to the bus line 463 of the CODEC 411. The CODEC 411 reads the image information from the memory A 405, encodes it by the MR method, and writes the encoded information in the memory B 406. When the CODEC 411 encodes A4 size image information, the CPU 412
CP the memory B 406 of the memory controller 404
Connect to U-bus 462. The CPU 412 sequentially reads the coded information from the memory B 406, and the MODEM 4
Transfer to 14. The MODEM 414 modulates the encoded information and transmits it as facsimile information on the telephone line via the NCU 415.

Next, an example of the facsimile receiving process will be described.

The information sent from the telephone line is input to the NCU 415 via the signal line 465 of the connector 416, and the NCU 415 carries out a predetermined procedure by the facsimile unit 4
Connected with. Information from NCU 415 enters MODEMM 414 via signal line 464 and is demodulated.
The CPU 412 is a MODEM via the CPU bus 462.
The information from 414 is stored in memory C407. When the information of one screen is stored in the memory C407, the CPU 412
By controlling the memory controller 404,
The data line 457 of the memory C407 is set to the CODEC 41
1 line 463. The CODEC 411 sequentially reads the encoded information in the memory C407 and decodes it, that is, stores it in the memory D408 as image information. C
The PU 412 communicates with the CPU 1003 of the core unit 10 via the dual port memory 410 and the memory D40
From 8 to the core unit 10, settings are made to print out an image to the printer unit 2. When setting is completed, CPU
412 activates the timing generation circuit 409 and outputs a predetermined timing signal from the signal line 460 to the memory controller 404. Memory controller 404
Reads the image information from the memory D 408 in synchronization with the signal from the timing generation circuit 409 and transmits it to the signal line 452. The signal 452 is input to the buffer 401 and output to the connector 400 via the signal line 451. The process up to the output from the connector 400 to the printer unit 2 has been described in the core unit 10 and will be omitted.

The detailed configuration and operation of the file unit 5 will be described below with reference to the block diagram shown in FIG.

FIG. 6 is a block diagram for explaining the detailed structure of the file unit 5 shown in FIG.

The file unit 5 is connected to the core unit 10 by the connector 500 and exchanges various signals. The bidirectional signal 551 is a bidirectional 8-bit multivalued image signal,
It is input to the buffer 501. The buffer 501 outputs the bidirectional signal 551 to the multilevel output signal 556 from the file unit 5.
And the multi-valued input signal 555 to the field section 5 is separated. The multi-valued input signal 555 is input to the compression circuit 503, where multi-valued image information is converted into binary compression information, and the selector 50
Output to 5. The signal 552 is a bidirectional binary image signal and is connected to the buffer 502. Buffer 502
Separates the bidirectional binary image signal 552 into a binary output signal 558 from the file unit 5 and a binary input signal 557 to the file unit 5. The binary input signal 557 is input to the selector 5
It is input to 05. The selector 505 outputs an output signal 561 from the compression circuit 503 according to an instruction from the CPU 516.
Output signal 557 from buffer 502, buffer 512
The output signal 562 is selected from three types of signals and input to the memory controller 510. The output signal 556 of the selector 505 is also input to the selector 511. When the compression information obtained by compressing the 8-bit multi-valued information from the core unit 10 is stored in any of the memory memories A506 to D509, the selector 505 selects the signal 561.
When the binary information is stored in the memory, the selector 505
Selects signal 557. When storing the information from the man-machine interface unit 6 shown in FIG. 1 in the memory, the selector 505 selects the signal 562. The output signal 556 of the selector 505 is the memory controller 5
Under control of 10, memories A506, B507, C508,
It is stored in any one of the D509s or one in which two sets of memories are cascade-connected. Memory controller 510
According to the instruction of the CPU 516, the memory A506, B5
07, C508, D509 and a mode for exchanging data with the CPU bus 560, and a CO for encoding / decoding
Under the control of the mode for exchanging data with the CODEC bus 570 of the DEC 517 and the control of the timing generation circuit 514, the signal 563 is sent to the memories A 506, B 507, C 508,
Mode stored in any of D509 and memory A50
No. 6, B507, C508, D509, 4 of the mode for outputting the memory contents to the read signal line 558
Has two functions. Memories A506, B507, C50
8 and D509 each have a memory capacity of 2 Mbytes and store an image corresponding to A4 at a resolution of 400 DPI. The timing generation circuit 514 is connected to the connector 500 by a signal line 553, is activated by the control signals HSYNC, HEN, VSYNC, VEN from the core unit 10 and generates signals for achieving the following two functions. One is to store information from the core unit 10 in the memory A50.
6, B507, C508, D509 any one memory, or the function of storing in two memories, two are the function of transmitting from any one of the memories A506, B507, C508, D509 to the read signal line 558. is there. The connector 513 exchanges signals with the man-machine interface unit 6 shown in FIG. The image information is connected to the buffer 512, and the command is connected to the communication circuit 518. The signal 569 is a bidirectional image signal, and the buffer 512 outputs the signal information to the signal line 562 when receiving the image information from the man-machine interface unit 6.
In addition, the file unit 5 to the man-machine interface unit 6
When the image information is output to, the information on the signal line 568 is transferred via the buffer 512 and the connector 513.
The dual port memory 515 is connected to the CPU 1003 of the core unit 10 via the signal line 554 and the CPU 516 of the file unit 5 via the signal line 560.
The CPUs 1003 and 516 exchange commands via the dual port memory 515. SCSI
The controller 519 interfaces with the external storage device 520 connected to the file unit 5 shown in FIG. The external recording device 520 is specifically composed of a magneto-optical disk, and stores data such as image information. CO
DEC 517 is a memory A506, B507, C50
8 or D509, the image information stored in either of the memories A506, B507, and C50 is read.
No. 8 or D509 is stored as encoded information.
In addition, memories A506, B507, C508, D509
Read the encoded information stored in MH, MR, M
After decoding by the desired MR method, the memory A
The decoded information, that is, image information is stored in any of 506, B507, C508, and D509.

An example of processing for accumulating file information in the external storage device 520 will be described below.

The 8-bit multi-valued image signal from the reader unit 1 is input from the connector 500 and the signal line 551 to the buffer 501. The buffer 501 is C
The signal 551 is sent to the signal line 555 by setting the PU 516.
Output to. The signal 555 is input to the compression circuit 503, where it is converted into binary compression information 561. The compressed information 561 reaches the memory controller 510 after being input to the selector 505. The signal 563 is input to the memory controller 510 and also the selector 51.
It is also input to the man-machine interface unit 6 via the 1, buffer 512 and the connector 513. The memory controller 510 uses the signal 553 from the core unit 10 to generate the timing signal 559 in the timing generation circuit 514, and according to this signal, outputs the compressed signal 563 to the memory A 506.
Remember. The CPU 516 is the memory controller 51.
0 memory A506 and memory B507 are CODEC
517 to the bus line 570. CODEC 51
7 reads the compressed information from the memory A506,
Encoding is performed by the MR method and encoded information is stored in the memory B507.
Write in. When CODEC 517 finishes encoding,
The CPU 516 is the memory B of the memory controller 510.
507 is connected to the CPU bus 560. The CPU 516 sequentially reads the encoded information from the memory B507,
Transfer to the SCSI controller 519. The SCSI controller 519 stores the encoded information 572 in the external storage device 520.

Next, an example of a print process for extracting information from the external storage device 520 and outputting it from the printer unit 2 will be described.

Upon receiving the information retrieval / printing instruction from the man-machine interface unit 6, the CPU 516 executes S
External storage device 520 via CSI controller 519
And receives the encoded information from and transfers the encoded information to the memory C508. At this time, the memory controller 510 instructs the CPU bus 560 to instruct by the CPU 516.
Is connected to the bus 566 of the memory C508. Memory C5
When the transfer of the encoded information to 08 is completed, the CPU 516
By controlling the memory controller 510,
The memory C508 and the memory D509 are connected to the bus 570 of the CODEC 517. CODEC 517 is a memory C
The encoded information is read from 508 and sequentially decoded, and then transferred to the memory D509. The CPU 516 is the CPU 1003 of the core unit 10 via the dual port memory 515.
And the setting for printing out an image from the memory D509 through the core unit 10 to the printer unit 2 is performed. When the setting is completed, the CPU 516 activates the timing generation circuit 514 and outputs a predetermined timing signal from the signal line 559 to the memory controller 510.
The memory controller 510 uses the timing generation circuit 51.
The decoded information is read from the memory D509 in synchronization with the signal from the signal No. 4 and transmitted to the signal line 558. The signal line 558 is input to the expansion circuit 504, and the decoded information is expanded and converted into image information. The output signal 556 of the expansion circuit 504 is input to the buffer 501 and output to the connector 500 via the signal line 551. Until the output from the connector 500 to the printer unit 2, the core unit 10
Since it has been described above, it is omitted.

The configuration and display processing operation of the man-machine interface unit 6 shown in FIG. 1 will be described below with reference to the block diagram shown in FIG.

FIG. 7 is a block diagram for explaining the detailed structure of the man-machine interface unit 6 shown in FIG. Hereinafter, an example of a process of receiving image information from the file unit 5 and displaying it on the display will be described.

The connector 600 is connected to the connector 513 of the file section 5 by a cable. CPU 615 is C
The communication circuit 610 communicates with the CPU 516 of the file unit via the PU bus 660 to set the image input mode.
The bidirectional image signal 651 from the connector 600 is separated into a unidirectional signal by the buffer 601. File part 5
The signal from is a one-way signal 652 in the buffer 601 and is input to the reduction circuit 602. Reduction circuit 602
Is an FLC display (high dielectric display) 60
The input image signal is reduced according to the display size of 8. The output signal 654 of the reduction circuit 602 is input to the dual port memory 605 through the buffer 603. Writing to the dual port memory 605 is performed by the timing generation circuit 60.
4 signal 658. The timing generation circuit 604 uses the timing signal 65 from the file unit 5.
It is activated by 7. When the image information for one line is written in the dual port memory 605, the CPU 615 receives the signal 666 from the timing generation circuit 604.
A DMA (direct memory access) request to the. C
The PU 615 uses a built-in DMAC (Direct Memory Access Controller) to operate the dual port memory 6
Image information is transferred from 05 to a DRAM (dynamic random access memory) 612 via a CPU bus 660. By repeating the above operation, the image information of one screen is stored in the DRAM 612. FLC display 6
08 is connected to the connector 607 by a cable 662 and inputs an image request signal (hereinafter, FHSYNC) 665 to the timing generation circuit 609. Timing generation circuit 609
Upon receiving FHSYNC 665, outputs a DMA request signal 667 to CPU 615. CPU 615 is D
When the MA request signal 667 is received, the DMAC incorporated in the CPU 615 is activated, and the line address displayed on the FLC display 608 from the DRAM 612 and the image information for one line are transferred to the FIFO 60 via the CPU bus 660.
DMA transfer to 6. Next, the timing generation circuit 609
Outputs the timing signal 663 to read the image information 661 for one line from the FIFO 606 and the connector 607.
To the FLC display 608 via. FLC
The display 608 determines the image display position from the line address to be displayed and displays the image information for one line on the FLC display. By repeating the above operation, the image information of one screen is displayed on the entire FLC.

An example of the transfer process for transferring the image information in the man-machine interface unit 6 to the file unit 5 will be described below.

The CPU 615 communicates with the CPU 516 of the file section 5 via the communication circuit 610 to set the image output mode. The image information of the man-machine interface unit 6 is stored in the DRAM 612, and the CPU 615
Is the DMA request signal 6 from the timing generation circuit 604.
When 66 is received, the image information for one line is transferred from the DRAM 612 to the dual port memory 605. Next, the read timing signal 658 from the timing generation circuit 604 reads the image information 656 from the dual port memory 605. Dual port memory 605
Output signal 656 from buffer 603, buffer 6
An image signal 651 is output to the connector 600 via 01. The operation in the file unit 5 has been described above, and will be omitted.

A keyboard interface 618 and a mouse interface 616 communicate with a keyboard 619 and a pointing device (mouse) 617, and give an operation instruction to the man-machine interface unit 6. 669 and 670 are interface lines.

The configuration and operation of the computer interface unit 7 shown in FIG. 1 will be described below with reference to the block diagram shown in FIG.

FIG. 8 is a block diagram for explaining the detailed structure of the computer interface section 7 shown in FIG.

The connector A (connector) 700 and the connector B (connector) 701 are SCSI interface connectors. The connector C702 is a Centronics interface connector. Connector D70
Reference numeral 3 is an RS232C interface connector.
The connector E707 is a connector for connecting to the core unit 10. The SCSI interface 704 has two connectors 700 and 701. When connecting a device having a plurality of SCSI interfaces, the connector 7
This is performed by making a cascade connection using 00 and 701. When the external device 3 and the computer are connected one-to-one, the connector 700 and the computer are connected with a cable, and the connector 701 is connected with a terminator, or the connector 701 and the computer are connected with a cable, and the connector 700 is connected. Connect the terminator to. Information input from the connector 700 or the connector 701 is
SCSI interface 70 via signal line 751
Input to 4. The SCSI interface 704 is S
After performing the procedure according to the CSI protocol, the data is transferred to the connector E (connector) 70 via the signal line 754.
Output to 7. The connector 707 is the CPU of the core unit 10.
The CPU 1 of the core unit 10 connected to the bus 1053
003 receives the information input to the SCSI interface connectors (connectors 700 and 701) from the CPU bus 1053. Data from the CPU 1003 of the core unit 10 is transferred to the SCSI connector (connectors 700 and 701).
When outputting to, the procedure is the reverse of the above.
Centronics interface 705 is connector C
It is connected to the (connector) 702 and input to the Centronics interface 705 via the signal line 752. The Centronics interface 705 receives the data according to the procedure of the determined protocol, and outputs the data to the connector E (connector) 707 via the signal line 754. The connector 707 is the CPU bus 10 of the core unit 10.
The CPU 1003 of the core unit 10 connected to the CPU 53.
Receives the information input to the Centronics interface connector (connector 702) from the CPU bus 1053.

The RS232C interface 706 is connected to the connector D (connector) 703 and connected to the signal line 7
It is input to the RS232C interface 706 via 53. The RS232C interface 706 receives the data according to the procedure of the determined protocol and outputs the data to the connector E (connector) 707 via the signal line 754. The connector 707 is the CPU bus 1 of the core unit 10.
The CPU 1003 of the core unit 10 connected to the 053.
Receives the information input to the RS232C interface connector (connector 703) from the CPU bus 1053. RS from data from the CPU 1003 of the core unit 10
When outputting to the 232C interface connector (connector 703), the procedure is reversed.

The configuration and operation of the formatter unit 8 shown in FIG. 1 will be described below with reference to the block diagram shown in FIG.

FIG. 9 is a block diagram for explaining the detailed structure of the formatter unit 8 shown in FIG.

Computer interface section 7 described above
Is determined by the core unit 10, and if the data is related to the formatter unit 8, the CP of the core unit 10
The U 1003 transfers data from the computer to the dual port memory 803 via the connector 1012 of the core unit 10 and the connector 800 of the formatter unit 8. The CPU 809 of the formatter unit 8 receives the code data sent from the computer via the dual port memory 803. The CPU 809 sequentially develops this code data into image data, and through the memory controller 808, the memory A 806 or the memory B 80.
Transfer the image data to 7. The memory A806 and the memory B807 each have a memory capacity of 2 Mbytes,
One memory (memory A806 and memory B807)
With the resolution of 400 DPI, it is possible to support up to A4 paper size. In the case of supporting up to A3 size paper at a resolution of 400 DPI, the memory A806 and the memory B807 are connected in cascade to develop image data. The memory control described above is performed by the memory controller 808 according to an instruction from the CPU 809. Also, when you need to rotate characters or figures when expanding image data,
After being rotated by the rotation circuit 804, it is transferred to the memory A 806 or the memory B 807. When the expansion of the image data in the memory A806 or the memory B807 is completed, the CP
U 809 controls the memory controller 808 to control the data bus line 858 of the memory A 806 or the memory B 80.
7 data bus line 859 to memory controller 80
8 output lines 855. Next, the CPU 809
Is the C of the core unit 10 via the dual port memory 803.
It communicates with the PU 1003 and sets a mode in which image information is output from the memory A 806 or the memory B 807.
The CPU 1003 of the core unit 10 sets the print output mode in the CPU 122 using the communication function built in the CPU 122 of the reader unit 1 via the communication circuit 1002 in the core unit 10. The CPU 1003 of the core unit 10 activates the timing generation circuit 802 via the connector 1013 and the connector 800 of the formatter unit 8. The timing generation circuit 802 generates a timing signal for reading image information from the memory A 806 or the memory B 807 to the memory controller 808 according to the signal from the core unit 10. Memory A806 or memory B807
The image information from is input to the scaling circuit 801 through signal lines 858 and 855. The scaling circuit 801
After scaling according to an instruction from the CPU 809, the data is transferred to the core unit 10 via the signal line 851 and the connector 800. Regarding the output of the printer unit 2 from the core unit 10,
Since it has been described with respect to the core portion 10, it will be omitted.

The configuration and operation of the image memory unit 9 shown in FIG. 1 will be described below with reference to the block diagram shown in FIG.

FIG. 10 is a block diagram for explaining the detailed structure of the image memory unit 9 shown in FIG.

The image memory unit 9 is connected to the core unit 10 by the connector 900 and exchanges various signals. The bidirectional signal 951 is a bidirectional 8-bit multivalued image signal and is input to the buffer 901. The buffer 901 separates the bidirectional signal 951 into a multilevel output signal from the image memory unit 9 via the signal line 955 and a multilevel input signal input to the image memory unit 9 via the signal line 954. The multi-valued input signal on the signal line 954 is stored in the memory 904 under the control of the memory controller 905. The memory controller 905 receives a multi-value input signal on the signal line 954 under the control of the timing generation circuit 902 and a mode in which data is exchanged between the memory 904 and the CPU bus 957 according to an instruction from the CPU 906.
04, and a mode for outputting the memory contents from the memory 904 to the read signal line 955. The memory 904 has a storage capacity of 32 Mbytes and is A3 with a resolution of 400 DPI and 256 gradations.
Store considerable images. The timing generation circuit 902 is
It is connected to the connector 900 by the signal line 952,
Control signals HSYNC, HEN, VSY from the core unit 10
It is activated by NC and VEN and generates signals to achieve the following two functions. One is a function of storing information from the core unit 10 in the memory 904, and two is a function of the memory 90.
4 is a function of transmitting the signal to the signal line 955 read from the No. 4. The dual port memory 903 has a signal line 953.
Through the CPU 1003 of the core unit 10 and the signal line 95
The CPU 906 of the image memory unit 9 is connected via 7. The CPUs 1003 and 906 exchange commands via the dual port memory 903. Hereinafter, an example of a transfer process of storing image information in the image memory unit 9 and transferring this information will be described.

The 8-bit multi-valued image signal from the reader unit 1 is input from the connector 900, passes through the signal line 951, and is input to the buffer 901. The buffer 901 is
The bidirectional signal 951 is output to the signal line 954 by the setting of the CPU 906. The memory controller 905 outputs the signal from the core unit 10 to the timing generation circuit 902 through the signal line 952 to generate the timing signal 956, and stores the content on the signal line 954 in the memory 904 according to the timing signal 956. CPU90
6 CPs the memory 904 of the memory controller 905.
Connect to U-Bus 957. CPU 906 is a memory 90
The image information is sequentially read from No. 4 and transferred to the dual port memory 903. CPU 1003 of core unit 10
Is a dual port memory 903 of the image memory unit 9.
Image information is read through the signal line 953 and the connector 900, and this information is transferred to the computer interface unit 7. The transfer of information to the computer interface unit 7 has been described above, and thus its explanation is omitted. Hereinafter, an example of an image output process in which the image information sent from the computer is output from the printer unit 2 will be described.

The image information sent from the computer is sent to the core unit 10 via the computer interface unit 7. The CPU 1003 of the core unit 10 is C
Image information is transferred to the dual port memory 903 of the image memory unit 9 via the PU bus 1053 and the connector 1013. At this time, the CPU 906 controls the memory controller 905 to transfer the CPU bus 957 to the memory 9.
04 bus. The CPU 906 transfers the image information from the dual port memory 903 to the memory 904 via the memory controller 905. Memory 904
After transferring the image information to the CPU 906, the CPU 906 controls the memory controller 905 to connect the data line of the memory 904 to the signal line 955. CPU906
Communicates with the CPU 1003 of the core unit 10 via the dual port memory 903, and makes settings for printing out an image from the memory 904 through the core unit 10 to the printer unit 2. When the setting is completed, the CPU 906
The timing generation circuit 902 is activated and the signal line 95 is activated.
6, a predetermined timing signal from the memory controller 90
Output to 5. The memory controller 905 reads the image information from the memory 904 in synchronization with the signal from the timing generation circuit 902 and transmits it to the signal line 955. The signal line 955 is input to the buffer 901 and is output to the connector 900 via the signal line 951. Until the output from the connector 900 to the printer unit 2, the core unit 1
Since it has been described as 0, it is omitted.

In the above configuration, the operation unit 124 of the reader unit 1, the keyboard 619 of the file unit 5, the connector A700 to the connector D703 of the computer formatter unit 7 of the computer or workstation 790 is connected as an operation unit for inputting various settings. There is a keyboard,
As described in each item, each operation unit is connected to the CPU 1003 of the core unit 10 by the communication unit.

The CPU 1003 of the core section 10 is in constant communication with each connected function, and when an operation setting is input by any of the operating means, a corresponding command code is transmitted to the CPU 1003. , The sequence program is executed after command interpretation, and an operation command is issued to the function requested to operate. At this time, by registering the priority setting and the operation prohibition setting in the sequence program, it is possible to make the user-friendly operation suited to the purpose of use of the user.

When image data is received from an external device by using the third function, the condition set by the external device is set in the communication protocol in advance and is sent out. Training in MODE
The CPU 412 interprets various settings via the M414, and further the C of the core unit 10 through the dual port memory 410.
By sending a command to the PU 1003, it is possible to remotely control the function of this system.

The operation instruction input processing operation from the external operating means and the self operating means will be described below with reference to FIG.

FIG. 11 is a flow chart showing an example of an operation instruction input processing procedure in the image forming system according to the present invention. Note that (1) to (20) indicate each step. For the sake of explanation, the first functional processing is the image reading processing by the reader unit 1 shown in FIG. 1, the second functional processing is the image forming processing by the printer unit 2 shown in FIG. 2, and the third functional processing is It is assumed that the formatter unit 8 shown in FIG. 1 is the image data conversion process, and the fourth functional process is the data transmission / reception process via the telephone line by the facsimile unit 4 shown in FIG. Further, in the present embodiment, the workstation 790 as the operation unit, the keyboard 619 of the external device 3, the reader unit 1
An example is given in which the core control unit 10 controls the functional processing from each of the operation units.

The CPU 1003 of the core unit 10 determines whether or not various settings are requested from each operation unit in a competitive manner with respect to each function processing means (1). If NO, each of the first to fourth
The functional processing of is executed in parallel (2) to (5).

On the other hand, if the judgment in step (1) is YES, it is judged whether or not the first functional processing is competing due to requests for various settings from a plurality of operating sections (6). Among the operation units requesting the setting, it is judged whether or not various setting requests are made from a specific operation unit registered in advance for the first functional processing (7), and if YES, the corresponding operation unit Cancel the setting request from (8),
To return.

On the other hand, if the judgment in step (7) is NO, it is judged whether or not various setting requests are made from the operation section of the first functional means (9), and if YES, it is judged from other operation sections. The setting requests from the operation unit of the first function means are set prioritized over the setting requests (10), and the process proceeds to step (13) and thereafter.

On the other hand, if the judgment in step (9) is NO, the setting priority orders of the plurality of requesting operation parts are compared.
(11) Then, various setting requests from the operation unit provided in the other function processing means are sequentially set (12), and the processing of the first function processing means is executed (13). Next, it is judged whether or not the processing of the first functional processing means requested by all the functional processing means has been completed (14). If NO, the process returns to step (1), and if YES, the processing is completed.

On the other hand, if the determination in step (6) is NO, it is determined whether or not the second functional processing is competing for various settings requested from a plurality of operating units (15). The second function processing execution routine corresponding to steps (7) to (14) is executed (16), and if NO, whether or not the third function processing requires various settings from a plurality of operating units and is in conflict. Is judged (17), and if YES, the above steps (7) to (14)
Executes the third functional process execution routine corresponding to (18),
If NO, the fourth function process determines whether or not various settings are requested from a plurality of operation units and whether there is a conflict (19), YES.
If so, the fourth functional process execution routine corresponding to steps (7) to (14) is executed (20), and if NO, the process returns.

[0100]

As described above, according to the present invention, since the function processing conditions for the first to fourth function processing means can be set and input from each operation means, the first operation from each operation means can be performed.
-Each function processing condition can be set for each of the fourth function processing means.

Further, when the judging means judges the competitive use request occurrence state for each of the first to fourth function processing means set and inputted from each operating means, the control means judges based on the judgment result of the judging means. Since the function processing condition input order for each of the first to fourth function processing means by each operation means is controlled based on the priority order that can be arbitrarily set, each operation means can control one function processing means. Even if the usage requests conflict with each other, the functional processing conditions can be sequentially set according to a desired priority.

Further, the control means is configured such that the first to fourth control input from each operating means is made based on the determination result of the determining means.
Since the input order of each function processing condition for each function processing means is controlled based on the use request input timing for each of the first to fourth function processing means input from each operation means, Even if the usage requests compete for one function processing means, the function processing conditions can be sequentially set in the order of the usage request input from each operation means.

Further, the control means makes a use request by each operating means corresponding to each of the first to fourth functional processing means on a one-to-one basis rather than a use request by another operating means based on the determination result of the determining means. Since the input order of each function processing condition for each of the first to fourth function processing means is determined so as to be prioritized, the setting of the function processing condition by the operating means corresponding to each function means is prioritized again. You can

Further, the control means is arranged such that the first to the fourth operations input from the specific operation means based on the determination result of the determination means.
Since the use request for each function processing means is invalidated, the use request for each of the first to fourth function processing means by each operating means can be arbitrarily differentiated.

Further, the first to fourth function processing means are
Since each functional processing is configured to be executable in parallel, the first to fourth functional processing means can be processed in parallel when the usage requests for the functional processing means do not conflict.

Therefore, there is an effect such that functional processing can be set for each system composed of a plurality of functional processing means with good operability.

[Brief description of drawings]

FIG. 1 is a block diagram illustrating a configuration of an image forming system according to an exemplary embodiment of the present invention.

FIG. 2 is a cross-sectional view showing configurations of a reader unit and a printer unit shown in FIG.

3 is a circuit block diagram showing a signal processing configuration of a reader unit shown in FIG.

FIG. 4 is a block diagram showing a detailed configuration of a core unit shown in FIG.

5 is a block diagram illustrating a detailed configuration of a facsimile unit illustrated in FIG.

6 is a block diagram illustrating a detailed configuration of a file unit shown in FIG.

7 is a block diagram illustrating a detailed configuration of a man-machine interface unit illustrated in FIG.

8 is a block diagram illustrating a detailed configuration of a computer interface unit illustrated in FIG.

9 is a block diagram illustrating a detailed configuration of a formatter unit shown in FIG.

FIG. 10 is a block diagram illustrating a detailed configuration of an image memory unit illustrated in FIG.

FIG. 11 is a flowchart showing an example of an operation instruction input processing procedure in the image forming system according to the present invention.

[Explanation of symbols]

 1 reader unit 2 printer unit 3 external device 4 facsimile unit 5 file unit 6 man-machine interface unit 7 computer interface unit 8 formatter unit 9 image memory unit 10 core unit 608 display 619 keyboard 790 workstation

Claims (6)

[Claims] 1. A first functional processing means for executing a first functional processing for reading an original image and converting it into image data,
The second that converts data input from the outside into image data
Second function processing means for executing the function processing of No. 3, third function processing means for transmitting and receiving image data via a communication line, and writing or reading processing of the image data to a predetermined storage medium. A combination of a fourth function processing means and a fifth function processing means for executing an image forming process on a recording medium based on image data output from any one of the first to fourth function processing means. In the image forming system to be constructed, a plurality of operating means capable of inputting the functional processing conditions for the first to fourth functional processing means are provided corresponding to the first to fourth functional processing means. Image forming system. 2. Judgment means for judging a competition use request occurrence state for each of the first to fourth function processing means set and inputted from each operation means, and each operation means based on the judgment result of this judgment means. 2. The image forming system according to claim 1, further comprising a control unit that controls the order of inputting the functional processing conditions for each of the first to fourth functional processing units based on a priority order that can be arbitrarily set. 3. The control means receives, from each operation means, an input order of each function processing condition for each of the first to fourth function processing means set and input from each operation means based on the determination result of the determination means. 3. The image forming system according to claim 2, wherein the image forming system is configured to be controlled based on a use request input timing for the first to fourth function processing means. 4. The control means, based on the determination result of the determination means, makes a use request by each operation means corresponding to each of the first to fourth function processing means one to one rather than a use request by another operation means. 3. The image forming system according to claim 2, wherein the input order of each of the functional processing conditions for each of the first to fourth functional processing means is determined so as to be prioritized. 5. The control means is configured to invalidate a use request for each of the first to fourth function processing means input from a specific operation means based on the determination result of the determination means. The image forming system according to claim 2. 6. The image forming system according to claim 2, wherein each of the first to fourth functional processing means is configured to be capable of executing each functional processing in parallel.