JPH09181865A - Image processing unit and its method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the adverse effect onto other system configuration device or the like and the effect on the performance of the entire system due to a monopoly time of a bus attended with transfer of image data. SOLUTION: A converter 200 converts an electric signal of each luminance level of RGB from a reader section 1 into multi-value data in black/white 8-bits and the data are stored in a bit map memory section 9, additional bit data with respect to read image data read by using an electric signal of a luminance level of G among RGB data and stored in a bit map memory 9. A CPU 1003 references the additional bit data received via a serial-parallel converter 204 to discriminate the processing with respect to the image and transfers the result to an image processing hardware 208. The image processing hardware 208 applies image processing to the black/white 8-bit multi-value data stored in the bit map memory section 9 based on the transferred information and after the image processing is finished, a printer section 2 is used to print out the image.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image processing apparatus and method, for example, a digital copying machine or main board capable of printing out, storing and transferring after reading multivalued image data and executing image processing, and a plurality of options. The present invention relates to an image processing apparatus and method most suitable for an external processing apparatus of a digital copying machine including a board.

[0002]

2. Description of the Related Art Conventionally, in a digital copying apparatus capable of reading multi-valued image data, in order to output the multi-valued image data read by the reader section of the digital copying apparatus after image processing (editing / processing), Multivalued image data is transferred to a terminal device such as a workstation via an interface means such as SCSI or parallel I / O, and image processing / editing is performed by making full use of the CPU / memory of the terminal device. After the completion of editing, the image data after editing was transferred to the printer section of the digital copying apparatus by using the interface means again and printed out.

When the data amount of multi-valued image data in the above conventional example is roughly calculated, black and white 8-bit multi-valued × 4
00 dpi, 11 x 17 inch original (11 x 400) x (17 x 400) x 8 = 239360000 bits (approximately 28.5
(Mbytes) Color 24-bit multi-value, 400 dpi, 11 × 17 inch original (11 × 400) × (17 × 400) × 8 × 3 = 718080000 bits (about 85.6 Mbytes) of data exists. Become.

[0004]

First, in the above-mentioned conventional example, since multi-valued image processing is performed by the terminal device,
A memory device having the capacity shown in the above calculation example is required on the terminal device side (in order to perform editing work in real time, not a magneto-optical disk or a hard disk but a DRAM or SRA).
A memory device such as M is required), and there is a point that a large amount of cost is required for capital investment for that purpose at the present time.

Secondly, in order to perform image editing processing on the data of the capacity shown in the above calculation example by the terminal device, a practical image editing speed can be obtained unless a high-level terminal device operating at high speed is used. Absent. Moreover, at the present time, such a terminal device is very expensive.

Thirdly, since it is necessary to transfer the data having the capacity shown in the above calculation example to the terminal device, the bus of the interface device and the internal CPU bus are occupied for a long time. , The performance of the whole network is deteriorated due to the increase of the Ethernet load, and the CPU bus is occupied so that the multi-operation of the digital copying system (while scanning, the printer unit operates as an LBP separately, F from the MOD
AX transmission operation is also performed).

[0007]

The present invention has been made for the purpose of solving the above-mentioned problems, and is provided with the following structure as a position means for solving the above-mentioned problems.

That is, reading means for reading an original and generating image data, generating means for generating information relating to image processing performed on the image data generated by the reading means, and generating means for the generating means. Control means for controlling execution of image processing by a predetermined image processing means according to the information, and transmitting / receiving means for transmitting / receiving the information generated by the generating means to / from an external device independently of the image data. It is characterized by having.

[0009]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, an embodiment of the present invention will be described in detail with reference to the drawings.

[First Example of Embodiment of the Invention] FIG. 1 is a block diagram showing the arrangement of an image forming system showing a first example of the embodiment of the present invention.

In FIG. 1, 1 is an image input device for converting an original into image data (hereinafter referred to as a reader unit), 2 is a plurality of kinds of recording paper cassettes, and image data is visible on the recording paper by a print command. An image output device (hereinafter referred to as a printer) 3 for outputting as an image is an external device electrically connected to the reader unit 1 and has various functions described later. The external device 3 includes a facsimile unit 4, a file unit 5, an external storage device 6 connected to the file unit 5, a computer interface unit 7 for connecting to a computer, and information from the computer as a visible image. A formatter unit 8, an image memory unit 9 for accumulating information from the reader unit 1 and temporarily accumulating information sent from a computer, and a core unit 10 for controlling each of the above functions. There is.

The function of each unit 1-9 will be described in detail below. <Description of Reader Unit 1> FIG. 2 is a cross-sectional view showing a schematic configuration of the reader unit 1 and the printer unit 2. The configuration and operation of the reader unit 1 will be described below with reference to FIG.
The reader unit 1 of the present example shown in FIG. 2 is a reader unit capable of reading a color image and capable of reading a color image.

The originals stacked on the original feeding device 101 are sequentially conveyed one by one onto the original glass surface 102. When the document is conveyed, the lamp 103 of the reader unit lights up and the scanner unit 104 moves to illuminate the document. Light reflected from the original is reflected by the mirrors 105, 1
After passing through the lens 108, the optical path is changed and the CCD image sensor unit 109
An image is formed on (hereinafter referred to as CCD) and read as an image signal.

FIG. 3 is a circuit block diagram showing the signal processing configuration of the reader unit 1 described above, and the configuration and operation will be described below.

The image information input to the CCD 109 is photoelectrically converted here and converted into an electric signal. CCD109
The image information (color image information for each color of R, G, and B) from A is output by the following amplifiers 110R, 110G, and 110B.
It is amplified according to the input signal level of the / D converter 111. Then, it is converted into a corresponding digital signal by the A / D converter 111.

The converted digital output signal from the A / D converter 111 is input to the shading circuit 112, where uneven light distribution of the lamp 103 and uneven sensitivity of the CCD are corrected. The signal from the shading circuit 112 is input to the Y signal generation / color detection circuit 113 and the external I / F switching circuit 119.

The Y signal generation / color detection circuit 113 is a circuit for calculating the signal from the shading circuit 112 by the following equation to obtain a Y signal.

Y = 0.3R + 0.6G + 0.1B The Y signal generation / color detection circuit 113 further has a color detection circuit for separating the R, G, and B color-specific signals into seven colors and outputting the signals for the respective colors. Y signal generation / color detection circuit 11
The output signal from 3 is input to the scaling / repeat circuit 114. In this example, the scaling processing in the sub-scanning direction is performed by changing the scanning speed of the scanner unit 104,
The scaling processing in the main scanning direction is performed by this scaling circuit / repeat circuit 1.
14. Also, the scaling / repeat circuit 114 is
In addition to the scaling processing in the main scanning direction described above, it is possible to output a plurality of identical images.

The output signal from the scaling / repeat circuit 114 is input to the contour / edge enhancement circuit 115, where edge enhancement and contour information are generated by enhancing the high frequency components of the signal from the scaling / repeat circuit 114. To do. The signal from the contour / edge emphasis circuit 115 is input to the marker area determination / contour generation circuit 116 and the patterning / thickening / masking / trimming circuit 117.

Marker area determination / contour generation circuit 116
Reads the portion of the document written with the marker pen of the specified color and generates the contour information of the marker. Then, the next patterning / thickening / masking / trimming circuit 1
At 17, the necessary thickening masking processing and trimming processing are performed from this contour information. Also, patterning, thickening,
The masking / trimming circuit 117 generates a Y signal.
Patterning processing is also performed by the color detection signal from the color detection circuit 113.

The output signal from the patterning / thickening / masking / trimming circuit 117 is input to a laser driver circuit 118 and converts various processed signals into signals for driving a laser. The output signal of the laser driver 118 is input to the printer 2 and an image is formed as a visible image.

Next, an external I / F for performing I / F with an external device
The F switching circuit 119 will be described. The external I / F switching circuit 119 outputs the image information from the patterning / thickening / masking / trimming circuit 117 to the connector 1 when outputting the image information from the reader unit 1 to the external device 3.
20. In addition, the external I / F switching circuit 119
When inputting the image information from the external device 3 to the reader unit 1, the image information for each color from the connector 120 is Y
The signal is input to the signal generation / color detection circuit 113.

Each image processing by each circuit described above is performed under the instruction and control of the CPU 122. Also,
The area signal generation circuit 121 generates various timing signals necessary for the image processing according to the value set by the CPU 122 and outputs the timing signals to the connector 1
It is possible to output to an external device via 20.

In addition, the reader unit 1 of this example includes a CPU 122.
It is configured to be able to communicate with the external device 3 by using the communication function built in. SUB / CPU1
23 controls the operation unit 124 and also performs SUB / CP
External device 3 using the communication function built in U123
Communicate with. <Description of Printer Unit 2> Next, the configuration and operation of the printer unit 2 of this example will be described with reference to FIG.

The output signal (image signal) of the laser driver 118 input to the printer unit 2 is converted into a corresponding optical signal by the exposure control unit 201 and irradiates the photosensitive member 202. The latent image formed on the photoconductor 202 by the irradiation light is developed by the developing device 203. The transfer paper is conveyed from the transfer paper stacking section 204 or 205 at the same timing as the above-mentioned development, and the developing unit 20 is transferred to the transfer section 206.
The image developed by 3 is transferred. The transferred image is fixed on the transfer sheet by the fixing unit 207,
It is discharged outside the device. The transfer paper output from the paper output unit 208 is discharged to each bin when the sort function is working in the sorter 220 or to the highest bin of the sorter when the sort function is not working. .

Next, a method for outputting sequentially read images on both sides of one output sheet will be described.

In the case of double-sided output, the output paper sheet fixed by the fixing unit 207 is once conveyed to the paper discharge unit 208, and then the conveyance direction of the paper sheet is reversed, and the paper sheet for re-feeding is conveyed through the conveyance direction switching member 209. The sheet is conveyed to the transfer sheet stacking unit 210. When the next original is prepared, the original image is read in the same manner as the above process, but since the transfer paper is fed from the re-transferred transfer paper stacking section 210, the front and back sides of the same output are eventually taken. It is possible to output two original images. <Description of External Device 3> The external device 3 is connected to the reader 1 via a cable as shown in FIG. 1, and the core unit 10 in the external device 3 controls signals and controls overall functions such as control of each function. Are doing. In the external device 3, a facsimile unit 4 for performing facsimile transmission / reception, a file unit 5 for converting various document information into electric signals and storing the same, a formatter unit 8 for developing code information from the computer into image information, and an interface with the computer. An image memory unit 9 for storing information from the computer interface unit 7, the reader unit 1 or temporarily storing information sent from the computer, and a core unit 10 for controlling the above functions. . <Description of Core Unit> The detailed configuration and operation of the core unit 10 of the external device 3 will be described below with reference to the block diagram shown in FIG.

FIG. 4 is a block diagram showing a detailed structure of the core section 10.

The connector 1001 of the core section 10 is connected to the connector 120 of the reader section 1 by a cable. Four types of signals are relayed to the connector 1001. Signal 1
057 is an 8-bit multi-value video signal, signal 1055 is a control signal for controlling the video signal, and signal 1051 is the reader 1
A signal for communicating with the CPU 122 in the reader 1052 is a signal for communicating with the SUB / CPU 123 in the reader 1.

Signals 1051 and 1052 are used for communication I
Communication protocol processing is performed in C1002, and CPU bus 10
Communication information is transmitted to the CPU 1003 via 53. The signal 1057 is a bidirectional video signal line, and it is possible for the core unit 10 to receive information from the reader unit 1 and to output information from the core unit 10 to the reader unit 1. The signal 1057 is a conversion device 200 for generating additional bit data from the G signal of the RGB signals from the reader unit 1 peculiar to this example, which will be described in detail later, and the buffer 101.
Connected to 0. The image processing hardware 208 is connected to the buffer 1010, and the information from the reader unit 1 is transferred from the bidirectional signal to the unidirectional signal 1058 and the signal 1058.
Separate into 70. If the signal from the reader unit 1 is an RGB serial signal, it is converted into an 8-bit multivalued signal here, and if it is an 8-bit multivalued signal, it is output as it is. Therefore, the signal 1058 is an 8-bit multivalued video signal and is input to the LUT 1011 in the next stage.

The LUT 1011 converts the image information from the reader unit 1 into a desired value by using a look-up table. The output signal 1059 from the LUT 1011 is input to the binarization circuit 1012 or the selector 1013.
The binarization circuit 1012 is a simple binarization function that binarizes a multi-valued signal 1059 at a fixed slice level, and a binarization function that uses a variable slice level in which the slice level varies from the values of pixels around the pixel of interest. , And a binarization function by the error diffusion method. The information binarized by the binarization circuit 1012 is (00) H when it is “0” and (F) when it is “1”.
F) is converted into a multilevel signal of H, and the selector 1013 at the next stage
Is input to

The selector 1013 selectively outputs either the signal from the LUT 1011 or the output signal from the binarization circuit 1012. The output signal 1060 from the selector 1013 is input to the selector 1014. The selector 1014 inputs the output video signals from the facsimile unit 4, the file unit 5, the computer interface unit 7, the formatter unit 8 and the image memory unit 9 to the core unit 10 via the connectors 1005, 1006, 1007, 1008, 1009, respectively. One of the output signal 1064 and the output signal 1060 of the selector 1013 is selectively output according to an instruction from the CPU 1003 based on the above-mentioned additional bit data, for example.

The output signal 1061 of the selector 1014 is
The signal is input to the rotation circuit 1015 or the selector 1016. The rotation circuit 1015 converts the information output from the reader unit 1 into a binary signal by the binarization circuit 1012, and then stores it in the rotation circuit 1015 as information from the reader unit 1. The rotation circuit 1015 inputs the input image signal by +90 degrees,
It has a function of rotating at −90 degrees and +180 degrees, and next, according to an instruction from the CPU 1003, the rotation circuit 101
Reference numeral 5 performs a predetermined rotation process on the stored information and reads it.
The selector 1016 selects either the output signal 1062 from the rotation circuit 1015 or the input signal 1061 of the rotation circuit 1015, and outputs the signal 1063 as a connector 1005 with the facsimile unit 4, a connector 1006 with the file unit 5, and a computer. Connector 1007 with interface unit, connector 1008 with formatter unit 8, connector 1009 with image memory unit, and selector 101
Output to 7.

The signal 1063 is a synchronous 8-bit unidirectional video bus for transferring image information from the core unit 10 to the facsimile unit 4, file unit 5, computer interface unit 7, formatter unit 8 and image memory unit 9. The signal 1064 is a synchronous 8-bit unidirectional video bus for transferring image information from the facsimile unit 4, the file unit 5, the computer interface unit 7, the formatter unit 8 and the image memory unit 9. Signal 1 above
It is the video control circuit 1004 that controls the synchronous bus of 063 and the signal 1064.
Control is performed by the output signal 1056 from 004.

Other signals 1054 are connected to the connectors 1005 to 1009, respectively. Signal 1
Reference numeral 054 denotes a bidirectional 16-bit CPU bus, which asynchronously exchanges data commands. Also this CP
The U-bus 1054 is connected to a serial-parallel conversion circuit 204 that serial-parallel converts additional bit data stored in the image memory unit 9 described later.

As a result, the transfer of information between the facsimile unit 4, the file unit 5, the computer interface unit 7, the formatter unit 8, the image memory unit 9 and the core unit 10 is performed by the above-mentioned two video buses 1063 and 1064. This can be done using the CPU bus 1054.

The signal 1064 from the facsimile section 4, file section 5, computer interface section 7, format section 8, and image memory section 9 is sent to the selector 1014.
Is input to the selector 1017. Selector 1016
Inputs the signal 1064 to the rotation circuit 1015 at the next stage according to the instruction from the CPU 1003.

The selector 1017 selectively outputs either the signal 1063 or the signal 1064 according to an instruction from the CPU 1003. The output signal 1065 of the selector 1017 is
It is input to the pattern matching 1018 and the selector 1019. The pattern matching 1018 is applied to the input signal 10
When the pattern is matched with a predetermined pattern by 65, a predetermined multilevel signal is output to the signal line 1066. If they do not match in the pattern matching, the input signal 1065 is changed to the signal 1
066.

The selector 1019 outputs the signal 1065 and the signal 1
Any one of 066 and 066 is selectively output according to an instruction from the CPU 1003. The output signal 1067 of the selector 1019 is input to the LUT 1020 at the next stage. LUT1020 is
When the image information is output to the printer unit 2, the input signal 1067 is converted according to the characteristics of the printer. Selector 10
21 is an output signal 1068 of the LUT 1020 and a signal 10
Any one of 65 and 65 is selectively output according to an instruction from the CPU 1003. The output signal of the selector 1021 is input to the enlargement circuit 1022 of the next stage.

The enlarging circuit 1022 can set the enlarging magnification independently in the X and Y directions according to an instruction from the CPU 1003. The expansion method adopted in this example is a linear interpolation method of the first order. Output signal 10 of expansion circuit 1022
70 is input to the buffer 1010. Buffer 10
The signal 1070 input to 10 becomes a bidirectional signal 1057 according to an instruction from the CPU 1003, and the connector 1001
Is sent to the printer unit 2 via the printer and printed out.

Hereinafter, the core portion 1 of this example having the above configuration
The signal flow between 0 and each unit will be described.

[Core part 1 based on information of the facsimile part 4
Operation of 0] First, the case of outputting information to the facsimile unit 4 will be described.

The CPU 1003 communicates with the CPU 122 of the reader 1 via the communication IC 1002 and issues a document scan command. When the reader unit 1 receives this command,
The scanner unit 104 is driven to scan the document. As a result, the document image information is read and output to the connector 120. Reader unit 1 and external device 3
Are connected by a cable, and information from the reader unit 1 is input to the connector 1001 of the core unit 10.

The image information input to the connector 1001 is input / stored in the buffer 1010 via the multilevel 8-bit signal line 1057. Buffer circuit 1010
According to the instruction of the CPU, the bidirectional signal 1057 is used as a one-way signal via the signal line 1058 to the LUT 1011.
To enter. The LUT 1011 converts the image information from the reader unit 1 into a desired value using a look-up table. For example, it is possible to skip the background of a document.

The output signal 1059 of the LUT 1011 is input to the binarization circuit 1012 at the next stage. Binarization circuit 101
2 converts the 8-bit multilevel signal 1059 into a binary signal. In the binarization circuit 1012, the binarized signal is "0".
In the case of (00) H and in the case of "1" (FF) H, it is converted into two multilevel signals. The output signal of the binarization circuit 1012 is input to the rotation circuit 1015 or the selector 1016 via the selectors 1013 and 1014.

The output signal 1062 of the rotating circuit 1015 is also input to the selector 1016, and the selector 1016 selectively outputs either the signal 1061 or the signal 1062. The selection of the signal is determined by the CPU 1003 communicating with the facsimile unit 4 via the CPU bus 1054. The output signal 1063 from the selector 1016 is sent to the facsimile unit 4 via the connector 1005.

Next, the case of receiving information from the facsimile section 4 will be described.

The image information from the facsimile section 4 is transmitted to the signal line 1064 via the connector 1005. The signal 1064 is generated by the selector 1014 and the selector 10
17 is input. When rotating and outputting an image at the time of facsimile reception to the printer unit 2 according to an instruction from the CPU 1003, the rotation circuit 1015 rotates the signal 1064 input to the selector 1014. The output signal 1062 from the rotation circuit 1015 is the selector 1016 and the selector 1.
It is input to the pattern matching 1018 via 017.

When the image at the time of facsimile reception is output to the printer 2 as it is according to the instruction of the CPU 1003, the signal 1064 input to the selector 1017 is input to the pattern matching 1018.

The pattern matching 1018 has a function of smoothing the backlash of an image when receiving a facsimile. The signal subjected to pattern matching is supplied to selector 1
019 to the LUT 1020. L in this example
The UT 1020 uses the LUT 1 in order to output an image received by facsimile to the printer unit 2 at a desired density.
The table of 20 can be changed by the CPU 1003.

The output signal 1068 of the LUT 1020 is input to the expansion circuit 1022 via the selector 1021. The enlargement circuit 1022 has two values ((00) H, (F
F) The 8-bit multivalue having H) is subjected to enlargement processing by a linear interpolation method of the first order. An 8-bit multi-valued signal having many values from the enlargement circuit 1022 is sent to the reader unit 1 via the buffer 1010 and the connector 1001.

The reader unit 1 transmits this signal to the connector 120
Is input to the external I / F switching circuit 119 via the. The external I / F switching circuit 119 inputs a signal from the facsimile unit 4 to the Y signal generation / color detection circuit 113. Y
An output signal from the signal generation / color detection circuit 113 is output to the printer unit 2 after being subjected to the above-described processing, and an image is formed on an output sheet.

[Operation of Core Unit 10 Based on Information of File Unit 5] A case of outputting information to the file unit 5 will be described.

The CPU 1003 communicates with the CPU 122 of the reader unit 1 via the communication IC 1002 and issues a document scan command. The reader unit 1 reads the image information on the document by the scanner unit 104 scanning the document according to this command, and outputs it to the connector 120.
The reader unit 1 and the external device 3 are connected by a cable, and information from the reader unit 1 is transferred to the connector 10 of the core unit 10.
01 is input.

The image information input to the connector 1001 becomes a unidirectional signal 1058 by the buffer 1010. The signal 1058, which is a multi-valued 8-bit signal, is an LUT
The signal is converted into a desired signal by 1011. LUT1
The output signal 1059 of 011 is transmitted to the connector 10 via the selector 1013, the selector 1014, and the selector 1016.
It is input to 06.

That is, without using the functions of the binarization circuit 1012 and the rotation circuit 1015, the 8-bit multi-value data is transferred to the file unit 5 as it is. CPU bus 1054 of CPU 1003
When filing the binarized signal by communicating with the file unit 5 via the, the functions of the binarization circuit 1012 and the rotation circuit 1015 are used. Since the binarization process and the rotation process are the same as those in the above-mentioned facsimile, detailed description thereof will be omitted.

Next, the case of receiving information from the file section 5 will be described.

The image information from the file section 5 is the connector 1
Selector 1014 as signal 1064 via 006.
Is input to the selector 1017. Selector 1017 for 8-bit multi-valued filing, or selector 1014 or selector 101 for binary filing.
It is possible to input in 7. In the case of binary filing, the detailed description is omitted because it is the same processing as facsimile.

In the case of multi-value filing, the output signal 1065 from the selector 1017 is input to the LUT 1020 via the selector 1019. In the LUT 1020, a look-up table is created according to an instruction from the CPU 1003 in accordance with a desired print density. LUT1
The output signal 1068 from 020 is input to the expansion circuit 1022 via the selector 1021. Enlargement circuit 102
The 8-bit multi-level signal 1070 expanded to a desired expansion ratio by 2 is sent to the reader unit 1 via the buffer 1010 and the connector 1001. The information in the file section sent to the reader section 1 is output to the printer section 2 and image formation is performed on the output paper, as in the above-mentioned facsimile.

[Operation of Core Unit 10 Based on Information of Computer Interface Unit 7] The computer interface unit 7 interfaces with a computer connected to the external device 3. The computer interface unit 7 includes a plurality of interfaces for communicating with other connection devices according to the interface specifications of SCSI, RS232C, and Centronics. The computer interface unit 7 has the above-mentioned three types of interfaces, and information from each interface is a connector 1007.
To the CPU 1003 via the data bus 1054. The CPU 1003 performs various controls based on the transmitted contents.

[Core part 1 based on information from the formatter part 8]
Operation of 0] The formatter unit 8 has a function of converting command data such as a document file sent from the computer interface unit 7 described above into image data and expanding the image data. When the CPU 1003 determines that the data sent from the computer interface unit 7 via the data bus 1054 is data regarding the formatter unit 8, the CPU 1003 transfers the data to the formatter unit 8 via the connector 1008. The formatter unit 8 expands the transferred data to be formatted, and expands it in the memory as a meaningful image such as characters and figures.

Next, a procedure for receiving information from the formatter unit 8 and forming an image on an output sheet will be described.

The image information from the formatter unit 8 is transmitted as a multi-valued signal having two values ((00) H, (FF) H) on the signal line 1064 through the connector 1008. The signal 1064 is input to the selector 1014 and the selector 1017. The selectors 1014 and 1017 are controlled by an instruction from the CPU 1003. Hereafter, the description is omitted because it is similar to the case of the above-mentioned facsimile.

[Operation of Core Unit 10 Based on Information of Image Memory Unit 9] A case of outputting information to the image memory unit 9 will be described.

The CPU 1003 communicates with the CPU 122 of the reader unit 1 via the communication IC 1002 to issue a document scan command. The reader unit 1 scans the original with the scanner unit 104 according to this instruction,
The image information is output to the connector 120. The reader unit 1 and the external device 3 are connected by a cable, and information from the reader unit 1 is input to the connector 1001 of the core unit 10. Image information input to the connector 1001 is multi-valued 8
It is sent to the LUT 1011 via the bit signal line 1057 and the buffer 1010. The output signal 1059 of the LUT 1011 is supplied to the selectors 1013, 1014, 101
6. To the image memory unit 9 via the connector 1009,
Transfer multi-valued image information. Note that additional bit data, which will be described later, is also stored in association with the multi-valued image information.

The image information including the additional bit data stored in the image memory unit 9 is the CPU of the connector 1009.
It is sent to the CPU 1003 via the bus 1054. CP
The U1003 transfers the data sent from the image memory unit 9 to the computer interface unit 7 described above. The computer interface unit 7 transfers a desired interface among the above three types of interfaces (SCSI, RS232C, and Centronics) to the computer.

Next, the case of receiving information from the image memory unit 9 will be described.

Image information is sent from the computer to the core unit 10 via the computer interface unit 7. Therefore, when the CPU 1003 of the core unit 10 determines that the data sent from the computer interface unit 7 via the CPU bus 1054 is the data related to the image memory unit 9, the CPU 1003 transfers the data to the image memory unit 9 via the connector 1009. Forward.

Next, the image memory unit 9 is connected to the connector 10
09, an 8-bit multilevel signal 1064 is supplied to the selector 10
14 and the selector 1017. Selector 101
4 or the output signal from the selector 1017 is the CPU 1
According to the instruction of 003, it is output to the printer unit 2 in the same manner as the above-mentioned facsimile, and an image is formed on the output paper. <Description of Facsimile Unit 4> FIG.
FIG. 3 is a block diagram showing a detailed configuration of the embodiment.

The facsimile section 4 is connected to the core section 10 by a connector 400, and exchanges various signals with the core section 10 via a connection cable. When the binary information from the core unit 10 is stored in any of the memories A405 to D408, the signal 453 from the connector 400 is input to the memory controller 404, and the memories A405 and B406 are controlled by the memory controller 404. ,
It is stored in either the memory 407 or the memory D 408, or one in which two sets of memories are cascade-connected.

The memory controller 404 is the CPU 41
The CODEC bus 4 of the CODEC 411 having the first mode for exchanging data between the memory A 405, the memory B 406, the memory C 407, the memory D 408 and the CPU bus 462 according to the instruction of No. 2 and the encoding / decoding function.
A second mode for exchanging data with 63 and the memory A4
05, memory B406, memory C407, memory D40
Under the control of the timing generation circuit 409, a third mode in which the contents of 8 are transferred to and from the bus 454 from the scaling circuit 403 under the control of the DMA controller 402 and 2 under the control of the timing generation circuit 409.
A fifth mode of storing the value video input data 454 in any of the memories A405 to D408 and a fifth mode of outputting the memory contents from any of the memories A405 to D408 to the read signal line 452;
It has the function of operating in one operation mode.

Each of the memory A 405, the memory B 406, the memory C 407, and the memory D 408 has a storage capacity of 2 Mbytes, and is capable of storing an image of A4 size at a resolution of 400 dpi. The timing generation circuit 409 includes a connector 400 and a signal line 459.
Connected via the control unit 10 and is activated by control signals (HSYNC, HEN, VSYNC, VEN) from the core unit 10, and generates signals for achieving the following two functions. The first is to store the image signal from the core unit 10 in the memory A4.
05 to a function of storing in any one of the memories D408 or two memories, the second is the memory A405
The function of transmitting an image signal from any one of the memories D408 to the read signal line 452.

The dual port memory 410 is connected to the CPU 1003 of the core section 10 via a signal line 461, and is connected to the CPU 412 of the facsimile section 4 via a signal line 462. Each CPU4
12, 1003 exchange commands via the dual port memory 410. SCSI controller 4
Reference numeral 13 interfaces with a hard disk connected to the facsimile section 4 shown in FIG. This hard disk stores data at the time of facsimile transmission and facsimile reception.

The CODEC 411 reads out the image information stored in any of the memories A405 to D408, encodes the image information by any one of the MH, MR, and MMR systems, and then executes the encoding.
It is stored in one of the memories D408 as encoded information. Further, the CODEC 411 reads out the encoded information stored in the memory A405 to the memory D408,
After performing decoding by any one of the H, MR, and MMR methods, the memories A405 to D408
In any of the above, it is stored as decoding information, that is, image information.

The MODEM 414 has a function of modulating the coded information from the hard disk connected to the CODEC 411 or the SCSI controller 413 for transmission on the telephone line, and demodulating the information sent from the NCU 415 to obtain the coded information. And a function to transfer the encoded information to the hard disk connected to the CODEC 411 or the SCSI controller 413. The NCU 415 is directly connected to a telephone line, administers an interface with the telephone line, and exchanges information with an exchange or the like installed in a telephone office or the like by a predetermined procedure.

An example of facsimile transmission in the facsimile section 4 of the present example having the above configuration will be described below.

The binary image signal from the reader unit 1 is input from the connector 400 and reaches the memory controller 404 via the signal line 453. The binarized image signal 453 is stored in the memory A 405 by the memory controller 404. The timing stored in the memory A 405 is generated by the timing generation circuit 409 based on the timing signal 459 from the reader unit 1. C
The PU 412 is the memory A4 of the memory controller 404.
05 and the memory B406 are connected to the bus line 463 of the CODEC 411. The CODEC 411 is a memory A4
05, image information is read out, encoded by a desired code or a method such as the MR method, and the encoded information is stored in the memory B.
Write to 406.

Image information of A4 size is converted to CODEC4
When 11 is encoded, the CPU 412 connects the memory B 406 of the memory controller 404 to the CPU bus 462. Then, the CPU 412 sequentially reads the encoded information from the memory B406 and transfers it to the MODEM 414. The MODEM 414 modulates the encoded information and transmits it as facsimile information on the telephone line via the NCU 415 according to a predetermined transmission procedure.

Next, an example of an embodiment of the invention in the facsimile reception processing in the facsimile section 4 will be described.

When a call is sent from the facsimile machine of the other party through the telephone line, the NCU 415 detects this and responds, and the information sent subsequently is transferred to the NCU 4
It is received at 15, and is connected to the facsimile section 4 in a predetermined procedure. The received information from the NCU 415 is MODEM41
4 and is demodulated there. CPU412 is CP
The demodulation information from the MODEM 414 is stored in the memory C407 via the U bus 462.

Thus, the information for one screen is stored in the memory C407.
Stored in the memory controller 4,
Controlling 04 connects the data line 457 of memory C407 to line 463 of CODEC 411. The CODEC 411 sequentially reads the stored information (encoded information) in the memory C407, decodes it, that is, converts it into the original image information, and stores it in the memory D408.

The CPU 412 is a dual port memory 4
The CPU 1003 communicates with the CPU 1003 of the core unit 10 via the CPU 10, and makes settings for printing out an image from the memory D 408 to the printer unit 2 via the core unit 10. When the setting is completed, the CPU 412 causes the timing generation circuit 40
9 is activated, and a predetermined timing signal is output from the signal line 460 to the memory controller. The memory controller 404 reads the image information from the memory D 408 in synchronization with the signal from the timing generation circuit 409, transmits the image information to the signal line 452, and outputs the image information to the connector 400. The process up to the output from the connector 400 to the printer unit 2 is the same as that described in the core unit, and thus detailed description will be omitted. <Description of File Unit 5> FIG. 6 is a block diagram showing a detailed configuration of the file unit 5, and the configuration and operation of the file unit 5 of this example will be described with reference to FIG.

The file section 5 is connected to the core section 10 via the connector 500, and exchanges various signals with the core section 10. In the file section 5, the core section 10
The multi-valued input signal 551 is input to the compression circuit 503, where multi-valued image information is converted into compression information and output to the memory controller 510. The output signal 552 of the compression circuit 503 is output to the memory A 506, the memory B 507, the memory C 508, under the control of the memory controller 510.
It is stored in any one of the memories D509 or in a cascade connection of two sets of memories.

The memory controller 510 includes the CPU 51.
Between the memory A 506, the memory B 507, the memory C 508, the memory D 509 and the CPU bus 560 in accordance with the instruction of No. 6, and the CODEC bus 570 of the CODEC 517 that performs encoding / decoding. The second mode for exchanging data and the memory A50
6, memory B507, memory C508, memory D509
The contents of the data are transferred to and from the bus 562 from the scaling circuit 511 under the control of the DMA controller 518.
Mode, a fourth mode in which the signal 563 is stored in any of the memories A506 to D509 under the control of the timing generation circuit 514, and the memories A506 to D5.
09 to read the memory contents from any one of the signal lines 5
It has a function capable of operating in five modes of the fifth mode for outputting to 58.

Each of the memory A506, the memory B507, the memory C508, and the memory D509 has a storage capacity of 2 Mbytes, and can store an image corresponding to A4 at a resolution of 400 dpi. The timing generation circuit 514 is connected to the connector 500 via a signal line 553, and controls signal (HSY) from the core unit 10.
NC, HEN, VSYNC, VEN),
Generate signals to achieve the following two functions.

The first is a function of storing the information from the core unit 10 in any one of the memories A506 to D509, or two memories, and the second is the memory A.
506 to a function of transmitting image information from any one of the memories D509 to the read signal line 556.

The dual port memory 515 is connected to the CPU 1003 of the core unit 10 via the signal line 554 and to the CPU 516 of the file unit 5 via the signal line 560. Each CPU exchanges commands via the dual port memory 515. The SCSI controller 519 interfaces with the external storage device 6 connected to the file unit 5 in FIG. The external storage device 6 is specifically composed of a magneto-optical disk, and stores data such as image information.

The CODEC 517 reads out the image information stored in any of the memory A 506 to the memory D 509 and encodes it by a desired one of the MH, MR and MMR codes. , Memory A 506 to memory D 509, as encoded information. Also, the memory A506 to the memory D509
The encoded information stored in the MH, MR,
After decoding by the desired method of the MMR method, it is stored in any of the memories A506 to D509 as the decoding information, that is, the image information.

An example of an embodiment of the invention for accumulating file information in the external storage device 6 in this example will be described below.

The 8-bit multi-valued image signal from the reader unit 1 is input from the connector 500 and input to the compression circuit 503 via the signal line 551. The 8-bit multi-valued image signal input to the compression circuit 503 is compressed information 55 here.
Converted to 2. The compressed information 552 is then input to the memory controller 510. Memory controller 510
Generates a timing signal 559 in the timing generation circuit 559 according to the signal 553 from the core unit 10, and stores the compression information 552 in the memory A 506 according to this signal.

The CPU 516 is the memory controller 51.
0 is instructed to set the memory A 506 and the memory B 507 under the control of the memory controller 510 to the CODEC 517.
Connected to the bus line 570. CODEC 517 is
The compressed information is read from the memory A506 and encoded by the MR method, for example, and the encoded information is stored in the memory B50.
Write to 7.

When CODEC 517 finishes encoding,
The CPU 516 is the memory B of the memory controller 510.
507 is connected to the CPU bus 560. And CPU5
16 sequentially reads the coded information from the memory B 507 and transfers it to the SCSI controller 519. SCS
The I controller 519 stores the encoded information 572 in the external storage device 6.

Next, an example of an embodiment of the invention for extracting information from the external storage device 6 and outputting it to the printer section 2 will be described.

Upon receiving the information retrieval / printing command, the CPU 516 receives the encoded information from the external storage device 6 via the SCSI controller 519 and transfers the encoded information to the memory C508. At this time, the memory controller 510 connects the CPU bus 560 to the bus 566 of the memory C508 according to an instruction from the CPU 516. When the transfer of the encoded information to the memory C 508 is completed, the CPU 516 controls the memory controller 510 to cause the memory C 508 and the memory D 509 to C.
Connect to ODEC 517 bus 570.

The CODEC 517 reads the coded information from the memory C 508, sequentially decodes it, and then stores it in the memory D 5
It transfers to 09. If it is necessary to change the magnification such as enlargement / reduction when outputting to the printer unit 2, the memory D50
9 is connected to the bus 562 of the scaling circuit 511 to scale the contents of the memory D509 under the control of the DMA controller 518.

The CPU 516 is the dual port memory 5
15 and communicate with the CPU 1003 of the core unit 10 via the memory D509 and the printer unit 2 through the core unit 10.
To print out the image. When the setting is completed, the CPU 516 starts the timing generation circuit 514
Then, a predetermined timing signal is output from the signal line 559 to the memory controller 510. The memory controller 510 reads the decoding information from the memory D509 in synchronization with the signal from the timing generation circuit 514, and transmits the decoding information to the signal line 556. The signal line 556 is connected to the decompression circuit 504, and the decompression circuit 504 inputs the decoding information and performs the necessary decompression processing. Expansion circuit 5
The output signal 555 from 04 is output to the core unit 10 via the connector 500. Since the core unit 10 has been described until the output from the connector 500 to the printer unit 2, detailed description thereof will be omitted. <Description of Computer Interface Unit 7> The computer interface unit 7 of this example will be described in detail with reference to FIG. FIG. 7 shows a computer interface section 7.
FIG. 3 is a block diagram showing a detailed configuration of the embodiment.

Connector A400 and connector B701
Is a connector for a SCSI interface. The connector C702 is a Centronics interface connector. The connector D703 is an RS232C interface connector. The connector E707 is a connector for connecting to the core unit 10.

SCSI interfaces 704 and 708
Are two connectors (connector A700 and connector B
701), each of which can be connected to a plurality of SCs.
When connecting a device with SI interface,
Cascade connection is performed using the connector A700 and the connector B701. When the external device 3 and the computer are connected on a one-to-one basis, the connector A700 and the computer are connected by a cable, the terminator is connected to the connector B701, or the connector B701 and the computer are connected by a cable. To the terminator.

Connector A700 or Connector B701
Is input via the signal line 751 to the SC.
It is input to the SI interface-A 704 or the SCSI interface-B 708. SCSI interface-A704 or SCSI interface-B7
08 outputs the data to the connector 707E via the signal line 754 after performing the procedure according to the SCSI protocol.

The connector E707 is connected to the CPU bus 1054 of the core unit 10, and the CPU 10 of the core unit 10 is connected.
03 receives information input to the SCSI interface connectors (connector A700, connector B701) from the CPU bus 1054. CPU 100 of core unit 10
The data from 3 is the SCSI connector (connector A700
And to the connector B701), the procedure is the reverse of the above.

The Centronics interface is connected to the connector C 702 and input to the Centronics interface 705 via the signal line 752. The Centronics interface 705 receives the data according to the procedure of the determined protocol, and outputs the data to the connector E707 via the signal line 754. Connector E707
Is connected to the CPU bus 1054 of the core unit 10,
The CPU 1003 of the core unit 10 receives the information input from the CPU bus 1054 to the Centronics interface connector (connector C702).

RS232C interface is connector D
703 and is connected to RS23 via signal line 753.
It is input to the 2C interface 706. RS232C
The interface 706 receives the data according to the procedure of the determined protocol, and outputs the data to the connector E707 via the signal line 754. The connector E707 is connected to the CPU bus 1054 of the core unit 10, and the CPU 1003 of the core unit 10 connects the CPU bus 1054 to the RS bus.
232C interface connector (connector D70
Receive the information entered in 3). CPU of core unit 10
When the data from 1003 is output to the RS232C interface connector (connector D703), the procedure is reversed. <Description of Formatter Unit 8> FIG.
FIG. 3 is a block diagram showing the configuration of FIG. The configuration and operation of the formatter unit 8 of this example will be described with reference to FIG.

The data from the computer interface unit 7 described above is discriminated by the core unit 10, and when the data is related to the formatter unit 8, the CPU 1003 of the core unit 10 causes the connector 1008 and the formatter unit 9 of the core unit 10. The data from the computer is transferred to the dual port memory 803 via the connector 800 of FIG. The CPU 809 of the formatter unit 8 receives the code data sent from the computer via the dual port memory 803.

The CPU 809 sequentially develops the code data into image data and transfers the image data to the memory A 806 or the memory B 807 via the memory controller 808. Memory A806 and memory B8
07 has a storage capacity of 1 Mbyte each, and one memory (memory A806 or memory B807) is 300 dp.
It is possible to store up to A4 paper size with a resolution of i. In order to support a paper size of A3 at a resolution of 300 dpi, memory A806 and memory B
Image data is expanded by connecting 807 in cascade. The above memory control is performed by the memory controller 808 in accordance with an instruction from the CPU 809.

Further, when it is necessary to rotate a character or a graphic when developing the image data, the image data is rotated by the rotation circuit 804 and then transferred to the memory A 806 or the memory B 807. When the expansion of the image data in the memory A806 or the memory B is completed, the CPU 809 controls the memory controller 808 to control the data bus line 858 of the memory A806 or the data bus line 85 of the memory B807.
9 is connected to the output line 855 of the memory controller 808.

Next, the CPU 809 communicates with the CPU 1003 of the core unit 10 via the dual port memory 803 and sets the mode in which the image information is output from the memory A 806 or the memory B 807. CPU 1 of core unit 10
003 sets the print output mode in the CPU 122 using the communication function built in the CPU 122 of the reader unit 1 via the communication circuit 1002 in the core unit 10.

When the print output mode is set, the CPU 1003 of the core unit 10 activates the timing generation circuit 802 via the connector 1008 and the connector 800 of the formatter unit 8. Timing generation circuit 802
Generates a timing signal for reading image information from the memory A 806 or the memory B 807 to the memory controller 808 according to the signal from the core unit 10.

The image information from the memory A 806 or the memory B 807 is input to the memory controller 808 via the signal line 858. Memory controller 808
The output image information from is transferred to the core unit 10 via the signal line 851 and the connector 800. The output from the core unit 10 to the printer unit has been described in the core unit 10, and thus detailed description thereof will be omitted. <Description of Image Memory Unit 9> FIG. 9 is a block diagram showing a detailed configuration of the image memory unit 9. The configuration and operation of the image memory unit 9 will be described below with reference to FIG.

The image memory section 9 is connected to the core section 10 by the connector 900 and exchanges various signals. The multi-level input signal 954 is stored in the memory 904 under the control of the memory controller 905. Memory controller 905
Is a first mode in which data is transferred between the memory 904 and the CPU bus 957 according to an instruction from the CPU 906, and the signal 954 is stored in the memory 90 under the control of the timing generation circuit 902.
4 has a function of operating in three modes, that is, a second mode for storing in memory 4 and a third mode for outputting the memory contents from the memory 904 to the read signal line 955.

The memory 904 has a storage capacity of 32 Mbytes and can store an image corresponding to A3 size with a resolution of 400 dpi and 256 gradations. The timing generation circuit 902 includes a connector 900 and a signal line 95.
It is connected via 2 and is activated by a control signal (HSYNC, HEN, VSYNC, VEN) from the core unit 10 and generates a signal for achieving the following two functions. The first is to store the information from the core unit 10 in the memory 90.
4 is a function of storing the image information in the memory 4, and the second is a function of reading the image information from the memory 904 and transmitting the image information to the signal line 955.

The dual port memory 903 includes a CPU 1003 of the core unit 10 via a signal line 953, and a CPU 906 of the image memory unit 9 via a signal line 957.
Is connected. Each CPU exchanges commands via the dual port memory 903.

An embodiment in which image information is stored in the image memory unit 9 and the information is transferred to the computer in the above-mentioned configuration will be described.

The 8-bit multi-valued image signal from the reader unit 1 is input from the connector 900 and input to the memory controller 905 via the signal line 954. The memory controller 905 causes the timing generation circuit 902 to receive the timing signal 956 in response to the signal 952 from the core unit 10.
And the signal 954 is stored in the memory 904 according to this signal.
To memorize. The CPU 906 is a memory controller 90.
5 memory 904 is connected to the CPU bus 597. CP
The U906 sequentially reads the image information from the memory 904 and transfers it to the dual port memory 903.

The CPU 1003 of the core unit 10 reads the image information of the dual port memory 903 of the image memory unit 9 via the signal line 953 and the connector 900 and transfers this information to the computer interface unit 7. Transferring information from the computer interface unit 7 to the computer has been described above, and thus detailed description thereof will be omitted.

Next, an example of outputting the image information sent from the computer to the printer unit 2 will be described.

The image information sent from the computer is sent to the core section 10 via the computer interface section 7. The CPU 1003 of the core unit 10 is a CP
Image information is transferred to the dual port memory 903 of the image memory unit 9 via the U bus 1054 and the connector 1009. At this time, the CPU 906 controls the memory controller 905 to connect the CPU bus 957 to the bus of the memory 904. The CPU 906 sends the image information from the dual port memory 903 to the memory controller 905.
Through the memory 904.

After transferring the image information to the memory 904, the CPU 906 controls the memory controller 905 to connect the data line of the memory 904 to the signal 955. The CPU 906 communicates with the CPU 1003 of the core unit 10 via the dual port memory 903, and makes settings for printing out an image from the memory 904 to the printer unit 2 via the core unit 10.

When the setting is completed, the CPU 906 activates the timing generation circuit 902 and outputs a predetermined timing signal from the signal line 956 to the memory controller 905. The memory controller 905 reads the image information from the memory 904 in synchronization with the signal from the timing generation circuit 902, transmits it to the signal line 955, and outputs it to the connector 900. Since the output from the connector 900 to the printer unit 2 has been described in the core unit 10, the description thereof will be omitted.

In this example, the above configuration is provided and various image processing and image print output processing are performed.

The detailed configuration of this example has been described above. R from the reader unit 1 which is a characteristic configuration of this example according to each of the above configurations
FIG. 10 schematically shows an example of how the process of generating the additional bit data from the GB signal and performing the image processing according to the additional bit data is specifically performed in an actual device. The outline of the processing in this example will be described in an easy-to-understand manner with reference to FIG.

The reader unit 1 reads an original with the CCD 109, converts it into an electrical signal of each of RGB brightness levels, performs a predetermined process, and then supplies it to the conversion device 200 as a read signal. The conversion device 200 uses RGB signals from the reader unit 1.
The electric signal of each luminance level is converted into black and white 8-bit multi-valued data as needed, and the converted data is stored in the image memory unit 9 which is, for example, a bitmap memory. Further, the conversion device 200 generates additional bit data for the image data read using the electric signal of the G brightness level of RGB, and stores it in the image memory unit 9.

In this example, an example in which the image memory unit 9 is used as a bit map memory will be described. However, the capacity required for separate processing in the core unit 10 or in the image processing hardware unit for actually performing image processing. Alternatively, a bitmap memory dedicated to image processing having a storage capacity for storing multi-valued data and additional bit storage may be provided.
By doing so, it is possible to perform more efficient image processing by eliminating the need for communication of image data. In this case, the image memory unit 9 of FIG. 10 becomes a dedicated bitmap memory, and the serial-parallel conversion circuit 20
4 also has a circuit configuration connected only to the bitmap memory.

The structure of this memory may be a memory such as a volatile semiconductor memory or a non-volatile memory such as a magnetic disk device, and its type is not limited.

Further, for the transfer of the additional bit data and the like, the communication with the image memory unit 9 may be met by a communication method by standardized Ethernet or the like (this is the same in the case of communication with other components. .), And CPU bus 1
It may be carried out by a specific bus which is an extension of 054.

As the above-mentioned additional bits, the conversion device 200 extracts, for example, a bit representing the existence of color, a bit representing image editing, a bit representing a binary image, and a bit representing the characteristics of a read multivalued image.

Each of the CPU 1003 and the file unit 5, the image memory unit 9, the serial-parallel converter 204, and the image control hardware 208 is a CPU bus 10.
They are connected to each other via 53 and 1054. Then, the CPU 1003 accesses the file unit 5 and the image memory unit 9 via the CPU bus 1054 and refers to the memory to communicate with the serial-parallel converter 204 and the image processing hardware (including communication of control signals). )I do. Then, the serial-parallel converter 20
The processing for the image read by the reader unit 1 is determined by referring to the additional bit data received via the CPU 4, and the result is transmitted to the image processing hardware 208 via the CPU buses 1053 and 1054.

The image processing hardware 208 performs image processing on the monochrome 8-bit multi-valued data stored in the image memory unit (bitmap memory) 9 based on the transmitted information, and the image processing is completed. After that, the printer unit 2
Perform printing with.

As described above, according to this embodiment, in a digital copying apparatus capable of reading multi-valued image data, a means for storing the read multi-valued image data, an additional bit is added to the multi-valued image data. By adding means, hardware means for performing image processing by the information of the additional bits, and means for transmitting / receiving information of only the additional bits to / from the image editing apparatus, digital copying of the processing which has been performed in the terminal device and which requires a large amount of calculation load. It is possible to reduce the amount of data to be processed because high-speed processing is performed by the hardware means on the device side and only the additional bits are transmitted and received.

Therefore, since the image processing load and the processing data amount load are released on the side of the terminal device, it is possible to perform sufficiently high-speed image processing without the need of using a particularly high-speed terminal. Furthermore, since the amount of data to be transferred is only additional bits, the transfer time is shortened, the adverse effect on the multi-operation due to the bus occupation time and the influence on the performance of the entire network are drastically reduced, and the overall performance of the copying system is improved.

The present invention may be applied to a system composed of a plurality of devices or an apparatus composed of one device. Needless to say, the present invention can be applied to a case where the present invention is implemented by supplying a program to a system or an apparatus. In this case, the storage medium storing the program according to the present invention constitutes the present invention. Then, by reading the program from the storage medium to a system or an apparatus, the system or the apparatus operates in a predetermined manner.

[0131]

As described above, according to the present invention, necessary image processing is performed only by generating information for controlling execution of image processing by a predetermined image processing means when image processing is performed and sending the information. Because I was able to do
Wherever the image processing is performed, the control side can perform the control for performing the appropriate image processing only by receiving this information. Therefore, it is possible to reduce the occupation time of the communication path between the respective components for transferring the image data, and for example, in a system in which the image data is read from the copying machine according to an instruction from the terminal device and necessary image processing is performed. Even in the case, conventionally, the read image is transferred to the terminal device, the terminal device side performs necessary image processing on the transferred image,
According to the present invention, what is sent back to the printer unit of the copying machine can select and instruct appropriate image processing by only transferring the above additional bits to, for example, the terminal device. No need to transfer
It is possible to drastically reduce the adverse effects of the bus occupation time on other system constituent devices and the like and the influence on the performance of the entire system.

[Brief description of the drawings]

FIG. 1 is a diagram showing an overall configuration of an image forming apparatus according to an example of an embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration of a reader unit and a printer unit shown in FIG.

FIG. 3 is a block diagram showing a configuration of an image processing unit in the reader unit shown in FIG.

FIG. 4 is a detailed block diagram of a core unit shown in FIG.

5 is a detailed block diagram of the facsimile unit shown in FIG.

FIG. 6 is a detailed block diagram of a file unit shown in FIG.

FIG. 7 is a detailed block diagram of a computer interface unit shown in FIG.

FIG. 8 is a detailed block diagram of a formatter unit shown in FIG.

FIG. 9 is a detailed block diagram of an image memory unit shown in FIG.

FIG. 10 is a diagram schematically showing an outline of image processing based on additional bit data of this example.

[Explanation of symbols]

 1 image input device (reader unit) 2 image output device (printer) 3 external device 4 facsimile unit 5 file unit 6 external storage device 7 computer interface unit 8 formatter unit 9 image memory unit 10 core unit 200 conversion device 204 serial-parallel conversion Circuit 208 Image processing hardware

Claims (20)

[Claims] 1. A reading unit for reading a document to generate image data, a generating unit for generating information related to image processing performed on the image data generated by the reading unit, and a generating unit for generating the information. Control means for controlling execution of image processing by a predetermined image processing means in accordance with the information, and transmission / reception means for transmitting / receiving the information generated by the generation means to / from an external device independently of the image data. An image processing apparatus having. 2. The image processing apparatus according to claim 1, wherein the image data is black-and-white multi-valued data. 3. The image processing apparatus according to claim 1, wherein the image data is multi-valued color data. 4. The image processing apparatus according to claim 1, wherein the information is a bit indicating the presence of color. 5. The image processing apparatus according to claim 1, wherein the information is a bit representing image editing. 6. The image processing apparatus according to claim 1, wherein the information is a bit representing a binary image. 7. The image processing apparatus according to claim 1, wherein the information is a bit representing a characteristic of a read multi-valued image. 8. The image processing apparatus according to claim 1, further comprising storage means for storing the image data. 9. The image processing apparatus according to claim 8, wherein the storage unit is a non-volatile memory. 10. The image processing apparatus according to claim 1, wherein the transmitting / receiving unit uses a specific bus unit for transmitting / receiving the information. 11. The image processing apparatus according to claim 1, wherein the transmitting / receiving unit uses a standardized transmitting / receiving unit for transmitting / receiving the information. 12. The image processing apparatus according to claim 1, wherein the image processing means is built in a digital copying machine. 13. The image processing apparatus according to claim 1, wherein the image processing means processes an image by hardware. 14. An image control processing method for an apparatus including a reading unit for reading an original and generating image data, the method generating information related to image processing performed on the image data generated by the reading unit. An image characterized by controlling execution of image processing by a predetermined image processing means according to the generated information and transmitting / receiving the generated information to / from an external device independently of the image data. Processing method. 15. The image processing method according to claim 14, wherein the image data is multi-valued black and white data. 16. The image processing method according to claim 14, wherein the image data is multi-valued color data. 17. The image processing method according to claim 14, wherein the information is a bit indicating the presence of color. 18. The image processing method according to claim 14, wherein the information is a bit representing image editing. 19. The image processing method according to claim 14, wherein the information is a bit representing a binary image. 20. The bit according to claim 14, wherein the information represents a characteristic of a read multi-valued image.
The image processing method described in the above.