JPH08242367A - Image processor - Google Patents

Abstract

PURPOSE: To generate plural pieces of binary image data by inputting multilevel image data once by executing binarizing processing on stored multilevel image data by a selected binarizing method for plural times. CONSTITUTION: The multilevel image data of an original stacked on an original feeder is read optically by operating a reader part 1 first, and it is stored in memory which comprises an image memory part 9 in an external device 3 transiently. Thence, the binarizing processing and resolution converting processing are applied to the multilevel image data stored in the memory, and it is stored in the image memory part 9 transiently again via the connector of a core part 10. Following that, generated binarized or resolution-converted image data is outputted to computer terminal equipment 8 connected to a printer part 2, a facsimile part 4, a filing part 5 and a computer interface part 7 via the core part 10. By repeating such processing, it is possible to generate and output plural binary images or resolution-converted image data only by one time of scanner input.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image processing apparatus for generating an image by binarization processing or resolution conversion processing.

[0002]

2. Description of the Related Art Usually, when a plurality of input image data are binarized by different methods or a plurality of image data having different resolutions are created, (1) inputting a multi-valued image (2) inputting a multi-valued image Generally, a series of processes of binarizing data or executing resolution conversion is repeatedly performed by changing the binarization method and the resolution conversion resolution.

In the case of creating an image in which binarized images by different binarization methods are combined for each partial region or an image in which image data of different resolutions are combined for each partial region, the above (1), The processing of (2) is repeated a plurality of times, and then the resulting images are combined to be executed.

[0004]

However, in the above-mentioned conventional method, the external input means is operated every time one binarized image or resolution-converted image used for processing is created,
It is necessary to input a multi-valued image. Therefore, it is necessary to input a multi-valued image a plurality of times, resulting in a long overall processing time, and when the external input means is shared with another processing device, the occupied time is increased. However, there is a problem in that the overall processing capacity is reduced because the processing time becomes longer.

The present invention has been made in view of the above problems, and an object thereof is an image in which a plurality of binarized image data and resolution-converted image data can be created by one input of multivalued image data. It is to provide a processing device.

[0006]

[Means for Solving the Problems] and

In order to achieve the above object, the present invention provides an input means for inputting multivalued image data, a first storage means for temporarily storing the multivalued image data, and a plurality of binarization methods. Means for selecting a binarization method according to the processing content from among the plurality of resolutions, means for selecting a resolution according to the processing content from a plurality of resolutions, and the selection for the stored multivalued image data. Processing by the selected binarization method, resolution conversion processing by the selected resolution, or means for executing the binarization processing and the resolution conversion processing a plurality of times, and the image data after the binarization processing. And output means for outputting.

Further, in another invention, a plurality of image data after the binarization process, the resolution conversion process, or the binarization process and the resolution conversion process are temporarily stored. Second storage means, means for specifying a partial area of the plurality of image data stored in the second storage means, image data stored in the first storage means, and the corresponding one of the partial areas And means for combining the image data stored in the second storage means.

In the above configuration, it functions to shorten the processing time and improve the processing capability of the entire image processing when the image data is generated by the binarization processing, the resolution conversion, and the image synthesis.

[0009]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

FIG. 1 is a block diagram showing a configuration of an image processing system (hereinafter referred to as a system) according to an embodiment of the present invention. In FIG. 1, reference numeral 1 denotes an image input device (hereinafter, referred to as a reader unit) for converting a document image into image data, and 2 has plural kinds of recording paper cassettes, and image data is recorded on recording paper by a print command. An image output device that outputs a visible image (hereinafter referred to as a printer unit), 3
Is an external device electrically connected to the reader unit 1,
It has various functions described later.

The external device 3 includes a fax unit 4, a file unit 5, an external storage device 6 connected to the file unit 5, a computer interface unit 7 for connecting to a computer terminal device 8, and a reader unit 1. Image memory unit 9 for accumulating information of the above, or temporarily accumulating information sent from the computer terminal device 8, and a core unit 10 for controlling each of the above functions.

The functions of the above-mentioned units will be described in detail below. <Description of Reader Unit 1> FIG. 2 shows the reader unit 1 according to the present embodiment.
3 is a cross-sectional view showing the configuration of the printer unit 2. FIG. The configuration and operation will be described below.

Documents (not shown) stacked on the document feeder 101 shown in FIG. 2 are sequentially transferred one by one to the platen glass surface 10.
2 is transported to above. When the document is conveyed, the lamp 103 of the scanner unit is turned on and the scanner unit 10
4 moves to illuminate the document. Then, the reflected light from the document passes through the lens 108 through the mirrors 105, 106 and 107 in order, and then the CCD image sensor unit 1
09 (hereinafter referred to as CCD) 9 is input.

FIG. 3 is a block diagram for explaining signal processing in the reader unit 1. In the figure, the CCD 10
The image information input to 9 is photoelectrically converted here and converted into a predetermined electric signal. The color information from the CCD 109 is transmitted to the next amplifier 110R, 110G, 110B.
Then, the signal is amplified according to the input signal level of the A / D converter 111 in the next stage. Then, the output signal from the A / D converter 111 is input to the shading circuit 112, where the light distribution unevenness of the lamp 103 and the sensitivity unevenness of the CCD 109 are corrected. The signal from the shading circuit 112 is input to the Y signal / color detection circuit 113 and the external I / F switching circuit 119.

The Y signal generation / color detection circuit 113 performs a calculation on the signal from the shading circuit 112 according to the following equation (1) to obtain a Y signal.

Y = 0.3R + 0.6G + 0.1B (1) The Y signal generation / color detection circuit 113 further includes R, G, B
It has a color detection circuit that separates the signal of 7 colors into 7 colors and outputs the signal for each color. The output signal from the Y signal generation / color detection circuit 113 is input to the scaling / repeat circuit 114 to perform scaling in the sub-scanning direction based on the scanning speed of the scanner unit 104, and the scaling / repeat circuit 1.
Magnification change in the main scanning direction is performed by 14. Further, the scaling / repeat circuit 114 can output a plurality of identical images.

In the contour / edge emphasis circuit 115, scaling /
By emphasizing the high frequency component of the signal from the repeat circuit 114, edge enhancement and contour information are obtained. The signal from the contour / edge enhancement circuit 115 is input to the marker area determination / contour generation circuit 116 and the patterning / thickening / masking / trimming circuit 117.

Marker area determination / contour generation circuit 116
Reads a portion of a document written with a marker pen of a designated color, generates contour information of the marker, and then performs the next patterning / thickening / masking / trimming circuit 1.
At 17, the thickening, masking, and trimming are performed based on this contour information. In addition, the Y signal generation / color detection circuit 113
Patterning is performed by the color detection signal from.

An output signal from the patterning / thickening / masking / trimming circuit 117 is input to the laser driver circuit 118 and variously processed signals are converted into signals for driving a laser. The output signal of the laser driver 118 is input to the printer 2 and image formation is performed as a visible image.

Next, the external I / F switching circuit 119 for interfacing (I / F) with the external device 3 will be described.

When outputting image information from the reader unit 1 to the external device 3, the external I / F switching circuit 119 outputs the image information from the patterning / thickening / masking / trimming circuit 117 to the connector 120. When the image information from the external device 3 is input to the reader unit 1, the external switching circuit 119 inputs the image information from the connector 120 to the Y signal generation / color detection circuit 113.

Each of the above image processes is performed in accordance with an instruction from the CPU 122, and the area signal generating circuit 121 generates various timing signals required for the above image process according to the value set by the CPU 122. further,
Communication with the external device 3 is performed using the communication function built in the CPU 122. In addition, SUB / CPU123
Controls the operation unit 124, and
Communication with the external device 3 is performed using the communication function built in the PU 123. <Description of Printer Unit 2> Referring to FIG. 2, the printer unit 2
The configuration and operation of will be described.

The signal input to the printer unit 2 is converted into an optical signal by the exposure control unit 201, and the photoconductor 202 is illuminated according to the image signal. With this irradiation light, the photoconductor 20
The latent image formed on 2 is developed by the developing device 203. The transfer paper is conveyed from the transfer paper stacking section 204 or the transfer paper stacking section 205 at the same timing as the above development, and the developed image is transferred at the transfer section 206. The transferred image is fixed on the transfer paper by the fixing unit 207, and then discharged from the paper output unit 208 to the outside of the apparatus. The transfer paper output from the paper output unit 208 is
When the sort function is working in the sorter 220, it is discharged to each bin, and when the sort function is not working, it is discharged to the highest bin of the sorter 220.

Next, a method for outputting sequentially read images on both sides of one output sheet will be described.

When the images to be sequentially read are output on both sides of one output sheet, the output sheet fixed by the fixing section 207 is once conveyed to the sheet discharge section 208, and then the conveyance direction of the sheet is reversed to change the conveyance direction. The sheet is conveyed to the re-transferred transfer sheet stacking section 210 via the switching member 209. Then, when the next original is prepared, the original image is read in the same manner as in the above process, but since the transfer paper is fed from the re-transferred transfer paper stacking section 210, the same result is obtained. It is possible to output two document images on the front surface and the back surface of the output paper. <Description of External Device 3> The external device 3 is connected to the reader unit 1 by the cable 12, and the core unit 10 in the external device 3
Controls signals and functions. This external device 3
As described above, the fax unit 4 that performs fax transmission / reception, the file unit 5 that converts various document information into electric signals and saves the signals on the magneto-optical disk, the computer interface unit 7 that interfaces with the computer terminal device 8, It comprises an image memory unit 9 for accumulating information from the reader unit 1 and temporarily accumulating information sent from the computer terminal device 8, and a core unit 10 for controlling each of the above functions. <Description of Core Unit 10> FIG. 4 is a block diagram showing a detailed configuration of the core unit 10.

The connector 1001 of the core portion 10 shown in FIG.
Is connected to the connector 120 of the reader unit 1 by a cable. The connector 1001 contains four types of signals,
The signal 1057 is an 8-bit multilevel video signal, and the signal 10
Reference numeral 55 denotes a control signal for controlling the video signal, which is a signal 1051.
Is a signal for communicating with the CPU 122 in the reader unit 1, and a signal 1052 is a SUB signal in the reader unit 1.
A signal for communicating with the CPU 123. Of these signals, the signal 1051 and the signal 1052 are subjected to communication protocol processing by the communication IC 1002, which is the CPU.
Communication information is transmitted to the CPU 1003 via the bus 1053.

The transmission path of the signal 1057 is a bidirectional video signal line, and the core unit 10 receives information from the reader unit 1 and outputs the information from the core unit 10 to the reader unit 1. Is possible.

The transmission path for the signal 1057 is the buffer 1
010, where the bidirectional signals are separated into unidirectional signals 1058, 1070. Of these signals, the signal 1058 is an 8-bit multi-valued video signal input from the reader unit 1 or an 8-bit multi-valued signal 1070 output from the resolution conversion circuit 1022, and L of the next stage.
It is input to the UT 1011. The LUT 1011 converts the image information from the reader unit 1 into a desired value by referring to a built-in lookup table.

Output signal 1059 from LUT 1011
Is input to the binarization circuit 1012 or the selector 1013. The binarization circuit 1012 has a multilevel signal 10
A simple binarization function of binarizing 59 with a fixed slice level, a binarization function of a variable slice level in which the slice level fluctuates from the values of pixels around the pixel of interest, and a binarization function of an error diffusion method. Have. The binarized information is converted into a multilevel signal of 00H when the value is “0” and FFH when the value is “1”, and these are input to the selector 1013 at the next stage.

The selector 1013 selects either the signal from the LUT 1011 or the output signal of the binarization circuit 1012, and the output signal 106 from the selector 1013 is selected.
0 is input to the selector 1014. Selector 101
Reference numeral 4 designates output video signals from the fax unit 4, the file unit 5, the computer interface unit 7 and the image memory unit 9, respectively.
Signal 1 input to the core unit 10 via 07, 1009
064 and the output signal 1060 from the selector 1013 are selected by the instruction of the CPU 1003.

Output signal 1061 from selector 1014
Is input to the rotation circuit 1015 or the selector 1016. The rotation circuit 1015 has a function of rotating the input image signal by +90 degrees, -90 degrees, and +180 degrees. The rotation circuit 1015 stores the information after the information output from the reader unit 1 is converted into a binary signal by the binarization circuit 1012 as information from the reader unit 1.

Next, according to an instruction from the CPU 1003,
The rotation circuit 1015 rotates and reads the stored information. The selector 1016 outputs the output signal 1062 from the rotation circuit 1015 and the input signal 106 to the rotation circuit 1015.
1 is selected, and as the signal 1063, the connector 1005 with the fax unit 4, the connector 1006 with the file unit 5, the connector 1007 with the computer interface unit 7, and the connector 100 with the image memory unit 9 are selected.
9 and the selector 1017.

The path of the signal 1063 is a synchronous 8-bit unidirectional video bus for transferring image information from the core unit 10 to the fax unit 4, file unit 5, computer interface unit 7 and image memory unit 9. Also,
The path of the signal 1064 includes a fax unit 4, a file unit 5,
This is a synchronous 8-bit unidirectional video bus for transferring image information from the computer interface unit 7 and the image memory unit 9. Then, the above signals 1063, 1
It is the video control circuit 1004 that controls the 064 synchronous bus, and this control is performed by the output signal 1056 from the video control circuit 1004.

Connectors 1005, 1006, 1007,
In addition to the above signals, signals 1054 are connected to 1009, respectively. This signal 1054 has a bidirectional 1
It is a 6-bit CPU bus, and exchanges data commands asynchronously. Further, in transferring information between the fax unit 4, the file unit 5, the computer interface unit 7, the image memory unit 9 and the core unit 10, the above two video buses 1063 and 1064 and the CPU bus 10 are used.
54 makes this possible.

The signal 1064 from the fax unit 4, file unit 5, computer interface unit 7, and image memory unit 9 is input to the selector 1014 and the selector 1017. Further, the selector 1014 is the CPU 100.
In accordance with the instruction of No. 3, the signal 1064 is output to the rotation circuit 1015 of the next stage.
To enter.

The selector 1017 selects either the signal 1063 or the signal 1064 according to an instruction from the CPU 1003. Output signal 1065 from this selector 1017
Is input to the pattern matching 1018 and the selector 1019. The pattern matching 1018 performs pattern matching with a predetermined pattern on the input signal 1065, and when the patterns match, outputs a predetermined multi-valued signal to the signal line 1066. However, if no match is found in this pattern matching, the input signal 1065
Is output as the signal 1066 as it is.

The selector 1019 selects either the signal 1065 or the signal 1066 according to an instruction from the CPU 1003, and the output signal 1068 is input to the LUT 1020 at the next stage. The LUT 1020, when outputting the image information to the printer unit 2, receives the input signal 10 according to the printer characteristics.
Convert 68.

The selector 1021 outputs the output signal 1067 from the LUT 1020 and the above signal 1065 to the CPU.
The output signal from the selector 1021 selected by the instruction of 1003 is input to the resolution conversion circuit 1022 at the next stage. The resolution conversion circuit 1022 can set the enlargement / reduction ratio independently in the X and Y directions according to an instruction from the CPU 1003. The enlargement / reduction method here is a linear interpolation method. The output signal 1070 from the resolution conversion circuit 1022 is output to the buffer 101.
Input to 0.

The signal 107 input to the buffer 1010
0 indicates a bidirectional signal 1057 according to an instruction from the CPU 1003.
And the printer unit 2 via the connector 1001.
To be printed out or a signal 1058 is sent to the LUT 1011.

Next, the signal flow between the core section 10 and each section will be described. <Operation of Core Unit 10 Based on Information of Fax Unit 4> (1) When Outputting Information to the Fax Unit 4 When outputting image information from the scanner unit 1 to the fax unit 4, the CPU 1003 uses the communication IC 1002. , Communicates with the CPU 122 of the reader unit 1 and issues a document scan command. In the reader unit 1, the scan unit 104 scans the document according to this command, and outputs the obtained image information to the connector 120. As described above, the reader unit 1 and the external device 3 are connected by the cable 12, and the information from the reader unit 1 is input to the connector 1001 of the core unit 10. Further, the image information input to the connector 1001 is the multi-valued 8-bit signal line 1057.
And is input to the buffer 1010.

Note that the signal 1070 can be input to the buffer 1010 again in accordance with an instruction from the CPU 1003.

The buffer circuit 1010 is a CPU 1003.
, The bidirectional signal 1057 is input to the LUT 1011 via the signal line 1058 as a unidirectional signal. The LUT 1011 converts the image information from the reader unit 1 into a desired value using a built-in lookup table. For example, this conversion makes it possible to remove the background of the document.

Output signal 1059 from LUT 1011
Is input to the binarization circuit 1012 at the next stage, and the binarization circuit 1012 converts the 8-bit multilevel signal 1059 into a binarized signal. The binarization circuit 1012 converts the input signal into two multi-level signals, for example, outputs 00H when the binarized signal is “0” and outputs FFH when it is “1”. The output signal from the binarization circuit 1012 is
It is input to the rotation circuit 1015 or the selector 1016 via the selector 1013 and the selector 1014.

Output signal 1062 from the rotating circuit 1015
Is also input to the selector 1016, and the selector 101
6 selects either the signal 1061 or the signal 1062. This signal is selected by the CPU bus 1 of the CPU 1003.
It is determined by communicating with the fax unit 4 via 054. Then, the output signal 1 from the selector 1016
063 is sent to the fax unit 4 via the connector 1005. (2) When receiving information from the fax unit 4 and outputting the information The image information from the fax unit 4 is transmitted to the signal line 1064 via the connector 1005. This signal 106
4 is input to the selectors 1014 and 1017.

When the image at the time of fax reception is rotated and output to the printer unit 2 according to the instruction of the CPU 1003, the image is input to the selector 1014 and the selected signal 1064 is rotated by the rotation circuit 1015. The output signal 1062 from the rotation circuit 1015 is input to the pattern matching 1018 via the selector 1016 and the selector 1017.

When the image at the time of fax reception is output to the printer unit 2 as it is according to the instruction of the CPU 1003, the signal 10164 input to the selector 1017 is input to the pattern matching 1018.

The pattern matching 1018 has a function of smoothing the rattling of an image when receiving a fax. The pattern-matched signal is sent to the selector 102.
9 is input to the LUT 1020, and the LUT 1020 is input.
In order to output the image received by fax to the printer unit 2 at a desired density, the contents of the table built therein can be changed by the CPU 1003.

Output signal 1067 from LUT 1020
Is the resolution conversion circuit 1022 via the selector 1021.
Is input to The resolution conversion circuit 1022 performs enlargement processing on an 8-bit multivalued signal having two values (00H, FFH) by a linear interpolation method of the first order.

When the image information from the fax unit 4 is output to the printer unit 2, the 8-bit signal 1070 from the resolution conversion circuit 1022 is sent to the reader unit 1 via the buffer 1010 and the connector 1001. Reader unit 1
Inputs this signal to the external I / F switching circuit 119 via the connector 120. Then, the external I / F switching circuit 119 inputs the signal from the fax unit 4 to the Y signal generation / color detection circuit 113. The output signal from the Y signal generation / color detection circuit 113 is subjected to the above-described processing and then output to the printer unit 2 to form an image on an output sheet.

The image information from the fax unit 4 is stored in the CPU 1
In response to the instruction of 003, the signal 1058 is again used as LUT1.
It can also be sent to 011. <Operation of Core Unit 10 Based on Information of File Unit 5> (1) When Information from the Reader Unit 1 is Output to the File Unit 5 When image information from the scanner unit 1 is output to the file unit 5, the CPU 1003 performs communication. It communicates with the CPU 122 of the reader unit 1 via the IC 1002 for use to issue a document scan command. In the reader unit 1, this command causes
Image information is output to the connector 120 as the scanner unit 104 scans the document.

As described above, the reader unit 1 and the external device 3 are connected by the cable 12, and the information from the reader unit 1 is input to the connector 1001 of the core unit 10. The image information input to the connector 1001 is further input to the buffer 1010. As a result, the signal 1058, which is a one-way multi-valued 8-bit signal, becomes
It is converted into a desired signal by 1.

On the other hand, the signal 1070 can be input to the buffer 1010 again according to an instruction from the CPU 1003. In this case, the buffer circuit 1010 is the CPU 1
According to the instruction of 003, the bidirectional signal 1057 is input to the LUT 1011 via the line of the signal 1058 as a unidirectional signal.

Output signal 1059 from LUT 1011
Is input to the connector 1006 via the selector 1013, the selector 1014, and the selector 1016. That is, the binarization circuit 1012 and the rotation circuit 101
The signal is transferred to the file unit 5 in the 8-bit multi-valued state without using the function of 5.

However, the CPU bus 10 of the CPU 1003
When filing a binarized signal by communicating with the file unit 5 via 54, the binarization circuit 101
2. The function of the rotating circuit 1015 is used. Since the binarization process and the rotation process here are the same as the processes in the above fax, the description thereof will be omitted here. (2) When receiving and outputting information from the file unit 5 The image information from the file unit 5 is transmitted to the signal line 1064 via the connector 1006. The signal 1064 on this signal line corresponds to the selector 1014 and the selector 10
In the case of 8-bit multi-value filing, it can be input to the selector 1017, and in the case of binary filing, it can be input to the selector 1014 or the selector 1017. Note that the processing in the case of binary filing is similar to the above-mentioned fax, and therefore its explanation is omitted.

In the case of multi-value filing, the selector 10
The output signal 1065 from 17 is input to the LUT 1020 via the selector 1019. In the LUT 1020, a look-up table is created according to an instruction from the CPU 1003 in accordance with a desired print density. LUT1
The output signal 1067 from 020 is input to the resolution conversion circuit 1022 via the selector 1021.

Here, when outputting the image signal from the file unit 5 to the printer unit 2, the 8-bit multi-value signal 107 enlarged to a desired enlargement ratio by the resolution conversion circuit 1022.
0 is via the buffer 1010 and the connector 1001
It is sent to the reader unit 1. Then, the information of the file section 5 sent to the reader section 1 is the same as in the case of the above fax.
The image is output to the printer unit 2, and an image is formed on the output paper there.

The image information from the file section 5 is C
In response to an instruction from the PU 1003, the signal 1058 is returned to L
It can also be sent to the UT 1011. <Operation of Core Unit 10 Based on Information of Computer Interface Unit 7> Computer interface unit 7
Interface with the computer terminal device 8 connected to the external device 3. The computer interface section 7 includes a plurality of interfaces for communicating with SCSI, RS-232C, and Centronics. Information from the above interfaces is sent to the CPU 10 via the connector 1007 and the data bus 1054.
Sent to 03. Then, the CPU 1003 performs various controls described below based on the content of the sent information. <Operation of Core Unit 10 Based on Information of Image Memory Unit 9> (1) When Outputting Image Information Read from Reader Unit 1 to Image Memory Unit 9 The CPU 1003 reads the reader unit 1 via the communication IC 1002. The CPU 122 communicates with the CPU 122 to issue a document scan command. In the reader unit 1, the scanner unit 104 scans the document according to this command, and outputs image information to the connector 120. Since the reader unit 1 and the external device 3 are connected by the cable 12, the reader unit 1
The image information from is input to the connector 1001 of the core unit 10.

The image information input to the connector 1001 is the multilevel 8-bit signal line 1057 and the buffer 10.
Sent to LUT 1011 via 10. And LU
The output signal 1059 from T1011 is the selector 101
It is transferred to the image memory section 9 as multi-valued image information via 3, 10, 14 and 1016 and the connector 1009. (2) When Outputting Image Information from the Fax Unit 4 to the Image Memory Unit 9 The image information from the fax unit 4 is sent to the signal line 1064 via the connector 1005 as two values (00H, FF).
H) is transmitted as a multilevel signal. Then, this signal 1064 is input to the selector 1014.

The signal 106 transmitted to the selector 1014
4 is the rotation circuit 1015 or the selector 1016 next.
Input to the output signal 1062 from the rotation circuit 1015.
Is also input to the selector 1016. As a result, the selector 1016 selects either the signal 1061 or the signal 1062. This signal selection is C
The PU 1003 determines by communicating with the fax unit 4 via the CPU bus 1054.

Output signal 1063 from the selector 1016
Are transferred to the image memory unit 9 via the connector 1009. (3) When outputting image information from the file unit 5 to the image memory unit 9 The image information from the file unit 5 is input to the selector 1014 as a signal 1064 via the connector 1006. The signal transmitted to the selector 1014 is the rotation circuit 1
015 or the selector 1016. Also,
The output signal 1062 from the rotation circuit 1015 is also the selector 1
The signal is input to 016, and the selector 1016 selects either the signal 1061 or the signal 1062. Similar to the above, the selection of this signal is determined by the CPU 1003 communicating with the file unit 5 via the CPU bus 1054. The output signal 1063 from the selector 1016 is transferred to the image memory unit 9 via the connector 1009. (4) When outputting data from the computer interface unit 7 to the image memory unit 90 The CPU 1003 has a connector 1007 and a data bus 10.
Upon receiving a data transmission request command from the computer interface unit 7 via 54, the connector 1007 outputs a data transmission instruction corresponding to the command to the computer interface unit 7. Computer·
In response to this instruction, the interface unit 7 transfers the data from the connected computer terminal device 8 to the core unit 10.

The data transferred to the core unit 10 is transferred to the connector 1007, and the data transferred to the connector 1007 is further transferred to the data bus 1054 and the connector 10.
It is transferred to the image memory unit 9 via 09. (5) When the image information from the image memory unit 9 is output from the printer unit 2. The image memory unit 9 is
The bit multi-level signal 1064 is transmitted to the selectors 1014 and 1017. The output signal from the selector 1014 or the selector 1017 is the CPU 1003.
Is output to the printer unit 2 in the same manner as in the case of the above-mentioned fax, and an image is formed on the output paper there. (6) When Outputting Image Information from the Image Memory Unit 9 from the Fax Unit 4 The image memory unit 9 transmits the image signal 1064 to the selector 1014 via the connector 1009. The signal transmitted to the selector 1014 is input to the rotation circuit 1015 or the selector 1016. Also, the rotating circuit 1
The output signal 1062 from 015 is also input to the selector 1016, and the selector 1016 receives the signal 1061 or signal 10
Select any of 62.

To select this signal, the CPU 1003 selects C
It is determined by communicating with the fax unit 4 via the PU bus 1054. The output signal 1063 from the selector 1016 is sent to the fax unit 4 via the connector 1005. (7) When Outputting Image Information from the Image Memory Unit 9 from the File Unit 5 The image memory unit 9 transmits the image signal 1064 to the selector 1014 via the connector 1009. The signal transmitted to the selector 1014 is input to the rotation circuit 1015 or the selector 1016. Rotating circuit 1015
The output signal 1062 from is also input to the selector 1016.
Select any of 62. As described above, the selection of this signal is determined by the CPU 1003 communicating with the file unit 5 via the CPU bus 1054. The output signal 1063 from the selector 1016 is sent to the file unit 5 via the connector 1006. (8) When the data from the image memory unit 9 is output from the computer terminal device 8 connected to the computer interface unit 7 In this case, the data from the image memory unit 9 is input to the core unit 10 via the connector 1009. It Core part 1
The data input to 0 is input to the computer interface unit 7 via the data bus 1054 and the connector 1007. <Description of Fax Unit 4> FIG. 5 is a block diagram showing a detailed configuration of the fax unit 4.

The fax unit 4 is connected to the core unit 10 via the connector 400 and exchanges various signals.
For example, the binary information from the core unit 10 is stored in the memory A405-
When stored in any of the memories D 408, the signal 453 from the connector 400 is transferred to the memory controller 404.
Under the control of the memory controller 404, the memory A 405, the memory B 406, and the memory C 40.
7, any of the memory D408, or of these,
It is stored in a cascade connection of two sets of memories.

The memory controller 404 is the CPU 41
2 is a mode for exchanging data between the memory A 405, the memory B 406, the memory C 407, the memory D 408 and the CPU bus 462, and a mode for exchanging data with the CODEC bus 463 of the CODEC 411 having an encoding / decoding function. , The memory A 405, the memory B 406, the memory C 407, and the memory D 408 are controlled by the DMA controller 402 to exchange data with the bus 454 from the scaling circuit 403. The video input data 454 is stored in the memory A405 to the memory D40.
8 mode, and memory A40
5 to a mode in which the memory content is read from any one of the memories D408 and is output to the signal line 452,
It has a total of five functions.

The memory A 405, the memory B 406,
Memory C407 and memory D408 are 2 Mby each
It has a capacity of tes and stores an image corresponding to A4 size at a resolution of 400 dpi.

The timing generation circuit 409 is connected to the connector 4
00 and the signal line 459, the core unit 10
Control signals from (HSYNC, HEN, VSYNC, V
EN) to generate signals for accomplishing the following two functions. One of them is that the image signal from the core unit 10 is stored in one of the memories A405 to D408.
One memory, or the function of storing in two of these memories, the second function is memory A405 to memory D
A function of reading an image signal from any one of 408 and transmitting it to the signal line 452.

The dual port memory 410 is connected to the CPU 1003 of the core unit 10 via the signal line 461 and the CP of the fax unit 4 via the signal line 462.
It is connected to U412. And each CPU
Commands are exchanged via the dual port memory 410. In addition, the SCSI controller 413
Interface with the hard disk 11 connected to the fax unit 4, as shown in FIG. The hard disk 11 stores data at the time of fax transmission and fax reception.

The CODEC 411 is the memory A40 described above.
5 to read the image information stored in any one of the memories D 408, encode the image information in a desired one of the MH, MR, and MMR systems, and then store it in the memory A 405 to
It is stored in one of the memories D408 as encoded information. Further, the coded information stored in the memories A405 to D408 is read out, and MH, MR, MMR, J
After the decoding is performed by a desired method among the BIG methods, it is stored in any of the memories A405 to D408 as the decoding information, that is, the image information.

The MODEM 414 has a function of modulating a signal for transmitting the coded information from the hard disk connected to the CODEC 411 or the SCSI controller 413 to the telephone line, and the information sent from the telephone line via the NCU 415. The coded information is demodulated, converted into coded information, and the coded information is transferred to the hard disk connected to the CODEC 411 or the SCSI controller 413. The NCU 415 is directly connected to a telephone line and exchanges information with an exchange installed in a telephone office or the like according to a predetermined procedure. (1) Description of Fax Transmission The image signal to be faxed is input from the reader unit 1 and the image memory unit 9 via the core unit 10. The image signal transferred from the core unit 10 is transferred to the connector 4
00, and reaches the memory controller 404 through the signal line 453. This signal 453 is stored in the memory A 405 by the memory controller 404. The timing stored in the memory A 405 is generated by the timing generation circuit 409 in response to the timing signal 459 from the reader unit 1.

The CPU 412 is the memory controller 40.
Memory A 405 and memory B 406 connected to
It is connected to the bus line 463 of the CODEC 411. CO
The DEC 411 reads the image information from the memory A 405, performs encoding by the MR method, for example, and writes the encoded information in the memory B 406. When CODEC 411 encodes A4 size image information, CP
U412 is the memory B40 of the memory controller 404.
6 is connected to the CPU bus 462. And the CPU 41
2 sequentially reads the coded information from the memory B 406 and transfers it to the MODEM 414. MODEM414
Modulates the encoded information and sends it as fax information over the telephone line via the NCU 415. (2) Description of Fax Reception Information sent from the telephone line is input to the NCU 415 and is connected to the fax unit 4 by the NCU 415 according to a predetermined procedure. The information from NCU415 is MODEM414
Demodulated at. The CPU 412 transfers the information from the MODEM 414 to the memory C407 via the CPU bus 462.
To memorize. When the information of one screen is stored in the memory C407, the CPU 412 controls the memory controller 404 to cause the data line 45 of the memory C407.
7 to line 463 of CODEC 411. Then, the CODEC 411 sequentially reads the encoded information in the memory C407 and decodes it, that is, stores it in the memory D408 as image information.

The CPU 412 is the dual port memory 4
The CPU 1003 communicates with the CPU 1003 of the core unit 10 via the CPU 10, and makes settings for outputting an image from the memory D 408 through the core unit 10 to the printer unit 2 or the image memory unit 9. When this setting is completed, CPU4
12 activates the timing generation circuit 409 and outputs a predetermined timing signal from the signal line 460 to the memory controller 404. Memory controller 404
Is synchronized with the signal from the timing generation circuit 409,
The image information is read from the memory D408, transmitted to the signal line 452, and output to the connector 400.

From the connector 400 to the printer unit 2,
Alternatively, the method for outputting to the image memory unit 9 is
The description is omitted because it is the same as in the core unit 10. <Description of File Unit 5> FIG. 6 is a block diagram showing a detailed configuration of the file unit 5.

The file unit 5 is connected to the core unit 10 via the connector 500 and exchanges various signals.
The image input signal 551 is input to the selector 521, and when the image input signal 551 is a multi-valued image that has not been compressed, the selector 521 is switched by the judgment of the CPU 516 and this signal is compressed. Fifty
Input to 3. Then, the multi-valued image signal input to the compression circuit 503 is converted into compression information and then output to the memory controller 510.

On the other hand, when the image input signal 551 is compressed, the signal 558 is selected by the selector 521, and the input signal is not compressed and the memory controller 5 is selected.
10 is input as a signal 552. The signal 552 is under the control of the memory controller 510, the memory A 506,
It is stored in any one of the memory B 507, the memory C 508, and the memory D 509, or one of these memories in which two sets of memories are cascade-connected.

The memory controller 510 is the CPU 51.
6, a mode for exchanging data between the memory A 506, the memory B 507, the memory C 508, the memory D 509 and the CPU bus 560, and a mode for exchanging data with the CODEC bus 570 of the CODEC 517 for encoding / decoding, The contents of memory A506, memory B507, memory C508, and memory D509 are
The scaling circuit 5 is controlled by the DMA controller 518.
Under the control of the timing generation circuit 514, a mode for exchanging data with the bus 562 from
Is stored in any of the memories A506 to D509, and a mode in which the memory contents are read out from any of the memories A506 to D509 and output to the signal line 558.

Memory A 506, memory B 507,
Memory C508 and memory D509 are 2 Mby each
It has a capacity of tes and stores an image corresponding to A4 size at a resolution of 400 dpi.

The timing generation circuit 514 is connected to the connector 5
00 and the signal line 553, and the core unit 10
Control signals from (HSYNC, HEN, VSYNC, V
EN) to generate signals for performing the following two functions. One of them is a function of storing the information from the core unit 10 in any one of the memories A506 to D509 or two of them, and the second function is to store the information in the memories A506 to D509. D5
09 is a function of reading out image information from any one of them and transmitting it to the signal line 556.

The dual port memory 515 is the CPU of the core unit 10 via the signal line 554 and the connector 500.
1003, and is also connected to the CPU 516 of the file unit 5 via a signal line 560. Each CP
The U exchanges commands via the dual port memory 515. Also, the SCSI controller 5
Reference numeral 19 interfaces with the external storage device 6 connected to the file unit 5 shown in FIG.

The external storage device 6 is specifically composed of a magneto-optical disk and stores data such as image information.

The CODEC 517 reads out the image information stored in any of the memories A506 to D509, encodes the image information in any one of MH, MR, and MMR by a desired method, and then selects one of the memories A506 to D509. The crab is stored as encoded information. Also, CODE
The C517 reads the encoded information stored in the memory A506 to the memory D509, decodes the encoded information by a desired one of the MH, MR, and MMR methods, and then, the memory A5.
06-stored in any of the memories D509 as decryption information, that is, image information. (1) Description of Storage of File Information in External Storage Device 6 When the image signal from the core unit 10 is input from the connector 500 and the signal reaching the signal line 551 is a non-compressed multi-valued image, The selector 521 is switched according to the judgment of the CPU 516, and the signal is transmitted to the compression circuit 50.
Input to 3. Then, the multi-valued image signal input to the compression circuit 503 is converted into predetermined compression information and then input to the memory controller 510.

On the other hand, when the compressed image signal is input, the selector 521 selects the signal 558 side,
The signal is not compressed and is stored in the memory controller 51.
Input to 0. The memory controller 510 uses the signal 553 from the core unit 10 to generate the timing generation circuit 55.
The compressed signal 552 is stored in the memory A 506 according to the timing signal 559 generated in 9.

The CPU 516 is the memory controller 51.
0 memory A506 and memory B507 to CODEC5
17 bus lines 570. CODEC 517
Reads the compressed information from the memory A 506,
Encoding is performed by the R method, and the obtained encoded information is written in the memory B507. When the CODEC 517 finishes the encoding, the CPU 516 controls the memory controller 510.
Memory B 507 of the above is connected to the CPU bus 560. Then, the CPU 516 stores the encoded information in the memory B50.
Sequentially read from 7, SCSI controller 51
Transfer to 9. The SCSI controller 519 stores the encoded information 572 in the external storage device 6. (2) Explanation of taking information from the external storage device 6 and outputting it to the printer unit 2 and the image memory unit 9 When the information retrieval / print command is received, the CPU
516 receives the encoded information from the external storage device 6 via the SCSI controller 519 and transfers the encoded information to the memory C508. At this time, the memory controller 510 receives a C instruction from the CPU 516.
PU bus 560 is connected to bus 566 of memory C508. When the transfer of the encoded information to the memory C508 is completed, the CPU 516 causes the memory controller 510 to
By controlling the memory C508 and the memory D50.
9 to bus 570 of CODEC 517. COD
The EC 517 reads the encoded information from the memory C 508, sequentially decodes it, and then transfers it to the memory D 509.

When it is necessary to change the magnification such as enlargement / reduction when outputting to the printer unit 2 and the image memory unit 9, the memory D
509 is connected to the bus 562 of the scaling circuit 511, and DMA
Under the control of the controller 518, the contents of the memory D509 are scaled.

The CPU 516 is the dual port memory 5
Communication with the CPU 1003 of the core unit 10 is performed via 15, and settings for printing out an image from the memory D509 through the core unit 10 to the printer unit 2 are performed. When this setting is completed, the CPU 516 activates the timing generation circuit 514 and outputs a predetermined timing signal from the signal line 559 to the memory controller 510.

The memory controller 510 reads the decoded information from the memory D509 in synchronization with the signal from the timing generation circuit 514 and transmits it to the signal line 556. The signal on the signal line 556 is input to the selector 520, and when it is stored in the file unit 5 as file information, it is determined whether or not the signal has been compressed by the compression circuit 503.

This determination is made by the CPU 516, and if the image information is compressed by the compression circuit 503, the output signal from the selector 520 is expanded by the expansion circuit 504, and the image information is It is output as the signal 555. Further, the above image information is compressed by the compression circuit 503.
If it is determined that the image signal is not compressed, the image signal is output as the signal 555 via the signal line 557.

The signal 555 is output to the core unit 10 via the connector 500, and the route from the connector 500 to the printer unit 2 and the image memory unit 9 is the same as in the core unit 10. Therefore, the description thereof is omitted. <Description of the computer interface section 7> FIG.
FIG. 3 is a block diagram showing the configuration of the computer interface unit 7.

In FIG. 7, a connector A700 and a connector B701 are SCSI interface connectors, a connector C702 is a Centronics interface connector, and a connector D703 is RS-232S.
Interface connector and connector E70
Reference numeral 7 is a connector for connecting to the core portion 10.

The SCSI interface has two connectors (connector A700, connector B701),
When connecting a device having a plurality of SCSI interfaces, a connector A700 and a connector B701 are used for cascade connection. When the external device 3 and the computer are connected one-to-one, the connector A700 is connected to the computer with a cable, and the connector B701 is connected to a terminator (terminator) or the connector B7.
01 and the computer with a cable, connector A7
Connect a terminator to 00.

Information input from the connector A 700 or the connector B 701 is sent to the SCSI I / F-A 704 or the SCSI I / F-A 704 via the signal line 751.
-Input to I / F-B708. SCSI I / F-
A704 or SCSI I / F-B708 is S
After performing the procedure according to the CSI protocol, the data is output to the connector 707E via the signal line 754. The connector E707 is the CPU bus 1 of the core unit 10.
054 and is connected to the CPU 1003 of the core unit 10.
Receives from the CPU bus 1054 the information input to the SCSI / I / F connector (connector A700, connector B701).

When outputting the data from the CPU 1003 of the core unit 10 to the SCSI connector (connector A700, connector B701), the procedure is reversed.

The Centronics interface is connected to the connector C702 and input to the Centronics I / F 705 via the signal line 752. The Centronics I / F 705 receives data according to a predetermined protocol and outputs it to the connector E707 via the signal line 754. The connector E707 is connected to the CPU bus 1054 of the core unit 10, and the CPU 1003 of the core unit 10 receives the information input to the Centronics I / F connector (connector C702) from the CPU bus 1054.

The RS-232C interface is connected to the connector D703 and is connected to the R line via the signal line 753.
It is input to the S-232C I / F 706. This RS-
The 232C I / F 706 also receives data according to a predetermined protocol and sends the signal to the signal line 754.
To the connector E707. Connector E70
7 is connected to the CPU bus 1054 of the core unit 10, and the CPU 1003 of the core unit 10 is connected to the CPU bus 1054.
4 receives the information input to the RS-232C I / F connector (connector D703).

When outputting the data from the CPU 1003 of the core unit 10 to the RS-232C I / F connector (connector D703), the procedure is reversed. <Description of Image Memory Unit 9> FIG. 8 is a block diagram showing the configuration of the image memory unit 9.

The image memory unit 9 is connected to the core unit 10 via the connector 900 and exchanges various signals. The input signal 954 is stored in the memory 904 under the control of the memory controller 905. The memory controller 905 is instructed by the CPU 906 to operate the memory 9
04 and the CPU bus 957 in a mode for exchanging data, under the control of the timing generation circuit 902, the signal 9
It has three functions: a mode for storing 54 in the memory 904 and a mode for reading the memory contents from the memory 904 and outputting it to the signal line 955.

The memory 904 has a memory capacity of 32 Mbytes capable of storing an image corresponding to A3 size with a resolution of 400 dpi and 256 gradations, as well as binarization processing and resolution conversion processing of an in-memory image described later. It also has a sufficient memory capacity for storing a plurality of image data obtained as a result of the execution. Further, the timing generation circuit 902 includes a connector 900 and a signal line 952.
Connected by a control signal (HSY) from the core unit 10.
NC, HEN, VSYNC, VEN),
Generate signals to achieve the following two functions:

One of them is a function of storing the information from the core unit 10 in the memory 904, and the second is a function of reading the information from the memory 904 and transmitting it to the signal line 955.

In the dual port memory 903, the CPU 1003 of the core unit 10 via the signal line 953 and the C of the image memory unit 9 via the signal line 957.
The PU 906 is connected. Each CPU exchanges commands via the dual port memory 903. (1) Description of accumulating image information input from the core unit 10 in the image memory unit 9 The image information input from the core unit 10 is transferred from any one of the reader unit 1, the fax unit 4, and the file unit 5. It was done. Therefore, the CPU 906 controls the memory controller 905 to connect the signal line 954 to the bus of the memory 904. That is, the reader unit 1, the fax unit 4,
The image signal of the core unit 10 transferred from any one of the file units 5 is input from the connector 900, and the signal line 9
It is input to the memory controller 905 via 54.

The memory controller 905 is the core unit 10
Signal 952 from the timing generation circuit 902
The signal 954 described above is stored in the memory 904 in accordance with the timing signal 956 generated in the above step. (2) Description of storing data input from the computer terminal device 8 connected to the computer interface unit 7 via the core unit 10 in the image memory unit 9 The core unit 10 receives from the computer terminal device 8 The data is input to the image memory unit 9 as described above. The data input to the image memory unit 9 is transferred to the dual port memory 903 via the connector 900. The data transferred to the dual port memory 903 is transferred to the CPU 906 of the image memory unit 9 from the memory 904 of the memory controller 905 to the CPU bus 9 of the memory controller 905.
After being connected to the computer 57, the data is sequentially read by the CPU 906 and stored in the memory 904 via the memory controller 905. (3) Description of outputting image information accumulated in the memory 904 of the image memory unit 9 to the core unit 10: The image information output to the core unit 10 can be any of the printer unit 2, the fax unit 4, and the file unit 5. Will be transferred to. C
The PU 906 controls the memory controller 905 to
The data line of the memory 904 is connected to the signal line 955. The CPU 906 communicates with the CPU 1003 of the core unit 10 via the dual port memory 903,
From the memory 904 through the core unit 10, the printer unit 2,
Settings are made to output image information to either the fax unit 4 or the file unit 5.

Upon completion of this setting, the CPU 906
The timing generation circuit 902 is activated and the signal line 9
From 56, a predetermined timing signal is input to the memory controller 905. The memory controller 905 synchronizes with the memory 90 in synchronization with the signal from the timing generation circuit 902.
4 reads the image information and sends it to the signal line 95
5 and outputs to the connector 900.

From the connector 900 to the printer unit 2,
The route to the fax unit 4 and the file unit 5 is the same as in the core unit 10 described above.
The description is omitted. (4) Description of outputting data stored in the memory 904 of the image memory unit 9 to the computer terminal device 8 connected to the computer interface unit 7 via the core unit 10 The CPU 906 controls the memory controller 905. Memory 9
04 is connected to the CPU bus 957. CPU 906
Image information is sequentially read from the memory 904 and transferred to the dual port memory 903. Core part 10
The CPU 1003 outputs the image information of the dual port memory 903 of the image memory unit 9 to the signal line 95.
3. Read through the connector 900 and transfer this information to the computer interface unit 7.

The computer interface unit 7
Since the transfer of information from the computer to the computer has been described above, the description thereof will be omitted here.

In the image memory unit 9, the memory 9
The multi-valued image data stored in 04 is output to the core unit 10, and the data obtained as a result of the binarization process and the resolution conversion process in the core unit 10 is again used in the image memory unit 9.
By storing the multi-valued image in the memory 904 of FIG. The processing in this case will be described below.

First, the CPU 906 communicates with the CPU 1003 of the core unit 10 via the dual port memory 903 to determine what processing is to be performed on the multi-valued image data stored in the memory 904. 10 CPU 1003. The setting items are as shown below.

(1) Existence of execution of binarization processing (2) Method of binarization processing when performing binarization processing (3) Presence of execution of resolution conversion processing (4) When execution of resolution conversion processing The CPU 1003 of the core unit 10 controls the binarization circuit 1012, the resolution conversion circuit 1022, and the selector 1013 in the core unit 10 based on these pieces of information to binarize the multivalued image data. And resolution conversion processing.

When the setting of the image processing contents is completed by the communication between the CPU 906 and the CPU 1003, the CPU
906 activates the timing generation circuit 902 and outputs a predetermined timing signal to the memory controller 905 via the signal line 956. The memory controller 905 reads the image information from the memory 904 in synchronization with this signal from the timing generation circuit 902,
It is transmitted to the signal line 955 and output to the connector 900. Then, the multi-valued image data output from the connector 900 is input to the core unit 10 via the connector 1009.

The data input to the core section 10 is sent to the selector 1017 as a signal 1065 via the selector 1017.
21 and further to the resolution conversion circuit 1022 via the selector 1021. The resolution conversion circuit 1022, when the execution of the resolution conversion processing is instructed by the setting of the processing content described above, the CPU 10
The resolution conversion process is executed at the enlargement / reduction ratio set by the instruction of 03.

Output signal 1 from resolution conversion circuit 1022
070 is input to the LUT 1011 as a signal 1058 via the buffer 1010. Where LUT10
In No. 11, the CPU 1003 is set not to perform any particular processing.
It is made by. Therefore, the data output from the LUT 1011 is input to either the binarization circuit 1012 or the selector 1013, and this selection is made by an instruction from the CPU 1003 according to the setting of the above processing content.

When data is binarized by the binarization circuit, depending on the setting of the above processing contents,
A binarization method that can be executed by the binarization circuit 1012, that is, either (1) simple binarization by a fixed slice level (2) binarization by a variable slice level (3) binarization by an error diffusion method Is selected.

The data binarized by the binarization circuit 1012 is input to the selector 1013, and this selector 101
The data input to No. 3 is further input to the connector 1009 as a signal 1063 via the selector 1016. The processed image data output from the connector 1009 is input to the image memory unit 9 via the connector 900.

Although the signal 954 input from the connector 900 is stored in the memory 904 under the control of the memory controller 905, the data storage in the memory 904 has already been described and will not be repeated.

By performing the above processing a plurality of times, it becomes possible to store a plurality of image data that have undergone different binarization processing and different resolution conversion processing in the memory 904 of the image memory unit 9.

Further, the CPU 906 of the image memory unit 9
Is image data obtained by combining different binarized images and resolution-converted images by combining partial areas of a plurality of image data stored in the memory 904 and subjected to different binarization and different resolution conversion processes. To create. The image data is synthesized by the CPU 906 of the image memory unit 9 by executing data movement on the memory 904. The image obtained as a result of this processing is stored in the memory 904 again.

As for an instruction as to what kind of synthesizing process is to be performed, an operator's instruction from the operation unit 124 in the reader unit 1 or the computer terminal device 8 connected to the computer interface unit 7 is used.
This is done by inputting through 0.

Hereinafter, in the image processing system according to the present embodiment, the binary conversion and resolution conversion processing functions of the image memory unit 9 are used to perform different binary conversions by only performing a scanner input of a multi-valued image once. A process of outputting a plurality of image data subjected to the conversion and resolution conversion process will be described.

FIG. 9 is a flow chart showing the procedure of a plurality of binarization and resolution conversion image output processing by one scanner input of a multivalued image.

First, in step S901 of FIG. 9, the reader unit 1 is operated to optically read the multivalued image data of the original document stacked on the original document feeder 101. The reading of this image data has been described above, and will be omitted. The read image data is converted into an electric signal and input to the external device 3 via the cable 12.

In step S902, the multi-valued image data input from the reader unit 1 is temporarily stored in the memory 904 constituting the image memory unit 9 in the external device 3.
The operation of storing the multi-valued image data input from the reader unit 1 in the memory 904 of the image memory unit 9 has been described above, and will not be described.

In step S903, binarization and resolution conversion processing of the multivalued image data stored in the memory 904 is performed. Here, the multi-valued image data stored in the memory 904 of the image memory unit 9 is once output to the core unit 10 via the connector 900, where the binarization processing or resolution conversion previously instructed by the operator is performed. After the processing, it is input again to the image memory unit 9 via the connector 1009 of the core unit 10. in this way,
The inputted binarized or resolution-converted image data is temporarily stored in the image memory unit 9 again.

Since the binarization processing and the resolution conversion processing performed in the core unit 10 are the same as the processes in the image memory unit 9, the description thereof will be omitted here.

Here, the memory area for storing the binarized or resolution-converted image data is secured in a memory area other than the memory area for storing the multi-valued image data temporarily stored in the memory 904 in step S902. Use the one that has been used.

Subsequently, in step S904, the created binarized or resolution-converted image data is transferred to the core unit 10.
Output to the computer terminal device 8 connected to the printer unit 2, the fax unit 4, the file unit 5, and the computer interface unit 7 via the. The details of this processing have also been described as the processing in the image memory unit 9, and will be omitted.

After the above processing, in step S905, it is determined whether or not the above output processing is completed. If it is not completed, the processing of step S903 and step S904 is repeated, and thus 1 in step S901 is executed. It is possible to create and output a plurality of binary image data or resolution-converted image data by only performing scanner input once.

Further, in the image processing system according to the present embodiment, the multi-valued image is processed once by using the binarization and resolution conversion processing function in the image memory unit 9 and the image synthesis processing function using the CPU 906. The process of outputting the combined image data in which the different binarization and resolution conversion processes are applied to the partial regions of the image only by performing the scanner input of is described.

FIG. 10 is a flow chart showing a process of synthesizing a plurality of binarized and resolution-converted images by one input of a multi-valued image scanner and its output process.

First, in step S1001 of FIG.
The reader unit 1 is operated to optically read the multivalued image data of the original document stacked on the original document feeder 101. In addition, since this image data reading was also described above,
Omit it. The read image data is converted into an electric signal and input to the external device 3 via the cable 12.

In step S1002, the multi-valued image data input from the reader unit 1 is temporarily stored in the memory 904 of the image memory unit 9 in the external device 3. The operation of storing the multi-valued image data input from the reader unit 1 in the memory 904 of the image memory unit 9 has also been described above, and will be omitted here.

Next, in step S1003, the memory 9
By performing binarization and resolution conversion processing of the multi-valued image data stored in 04, the first image data to be combined when creating the combined image data (hereinafter, referred to as image combined data A) To generate. Here, the multi-valued image data stored in the memory 904 of the image memory unit 9 is
Through the connector 900, once output to the core unit 10,
Therefore, after the binarization process or the resolution conversion process instructed by the operator in advance, the core unit 10 is re-executed.
Is input to the image memory unit 9 via the connector 1009.

The binarized or resolution-converted image composite data A thus input is temporarily stored in the memory 904 of the image memory unit 9 again. The binarization process and the resolution conversion process performed in the core unit 10 are the same as the processes in the image memory unit 9 described above, and therefore the description thereof is omitted here.

The memory area for storing the binarized or resolution-converted image composite data A is
In the step S1002, a memory area reserved other than the memory area for storing the multi-valued image data temporarily stored in the memory 904 is used.

In the following step S1004, the memory 90
By re-performing the binarization and resolution conversion processing of the multi-valued image data stored in No. 4, another composition target image data (hereinafter referred to as image composition data B Call). Here, the multi-valued image data stored in the memory 904 of the image memory unit 9 is once output to the core unit 10 via the connector 900, where the binarization processing or resolution conversion previously instructed by the operator is performed. After being processed, the image data is again input to the image memory unit 9 via the connector 1009 of the core unit 10.

The memory area for storing the binarized or resolution-converted image composite data B input in this manner is the multivalued image data temporarily stored in the memory 904 in step S1002. Further, the data secured in a region other than the memory region storing the image synthesis data A temporarily stored in the memory 904 in step S1003 is used.

Succeedingly, in a step S1005, an image synthesizing process is performed. The image synthesizing process is performed in the step S1.
003, in step S1004, the CPU 906 of the image memory unit 9 executes the image composition processing on the image composition data A and the image composition data B temporarily stored in the memory 904. Since the details of this image composition processing are the same as the processing relating to the image memory unit 9 described above, the description thereof is omitted here.

The combined image data obtained as a result of the above image combining processing is temporarily stored in the memory 904 again.
This is overwritten in the memory area in which the image composite data A is temporarily stored.

In step S1005a, it is determined whether or not the above-described combining process is completed. If it is not completed, the processes in steps S1004 to S1005 are repeatedly executed, whereby a plurality of image processes are partially executed. It is possible to create a composite image that has been applied. In addition,
The combined image data in step S1005 is sequentially overwritten on the combined image data temporarily stored in the memory 904 in the process in step S1005 in which the combination is first executed.

If it is determined that the image synthesizing process is completed, finally, in step S1006, the synthesized image data created is sent to the printer unit 2, the fax unit 4, and the file unit 5 via the core unit 10. , And to the computer terminal device 8 connected to the computer interface unit 7. The details of this processing have been described in the description of the image memory unit 9 above, and thus will be omitted here.

By executing such processing, the image data combined for each of a plurality of binary image data or resolution conversion image data partial areas is created and output by performing only one scanner input in step S1001. To do.

As described above, according to this embodiment,
The multi-valued image data input once is repeatedly used to execute a plurality of different binarization processes or resolution conversion processes to create binarized image data or resolution-converted image data. By inputting the image data, all the binarized image data and the resolution-converted image data can be created, or the image data in which different binarized image data and the resolution-converted data are combined for each partial area can be created.

Further, by this processing, the processing time of the entire image processing is shortened, and when the external input means is shared with another processing apparatus, the occupied time is shortened, so that the entire processing capacity is reduced. Can be improved.

In the above embodiment, the binarization method relating to the image binarization processing which the core unit 10 has as a function is as follows:
The method is not limited to the simple binarization method, the variable slice level method, and the error diffusion method.
The core unit 10 may have another binarization processing function known in the art.

In the process for outputting a binarized or resolution-converted image, in the above embodiment, the image data binarized or resolution-converted in step S1003 of FIG. After being stored in the memory 904 of FIG. 9, the data is output to the outside in step S1004. However, the present invention is not limited to this.
The multi-valued image data stored in 4 is output to the core unit 10,
While performing binarization and resolution conversion processing, the signal is directly output to the computer terminal device 8 connected to the fax unit 4, the file unit 5, and the computer interface unit 7 via the signal line 1063, the connectors 1005, 1006 and 1007. You may do it.

Further, the binarized or resolution-converted image data may be output as it is to the printer unit 2 to perform the binarization and resolution conversion processing while performing the printing processing.

The present invention may be applied to a system composed of a plurality of devices or an apparatus composed of one device. Further, it goes without saying that the present invention can be applied to the case where it is achieved by supplying a program to a system or an apparatus.

[0144]

As described above, according to the present invention,
By executing a plurality of different binarization processes and resolution conversion processes by repeatedly using the input multivalued image data, a plurality of binarized image data and resolution converted image data can be obtained by one input of the multivalued image data. It can be created, and the overall processing time can be shortened.

According to another invention, it is possible to easily create image data in which different binary image data and resolution conversion data are combined for each partial area.

[0146]

[Brief description of drawings]

FIG. 1 is a block diagram showing an overall configuration of an image processing system according to an embodiment of the present invention.

FIG. 2 is a cross-sectional view showing configurations of a reader unit 1 and a printer unit 2.

FIG. 3 is a block diagram showing a configuration of an image processing unit in the reader unit 1.

FIG. 4 is a block diagram showing a configuration of a core unit 10.

FIG. 5 is a block diagram showing a configuration of a fax unit 4.

FIG. 6 is a block diagram showing a configuration of a file unit 5.

FIG. 7 is a block diagram showing a configuration of a computer interface unit 7.

FIG. 8 is a block diagram showing a configuration of an image memory unit 9.

FIG. 9 is a flowchart showing a processing procedure of multiple binarization and resolution-converted image output by one input of the multi-valued image scanner.

FIG. 10 is a flowchart showing a procedure of a process of combining and outputting a plurality of binarized and resolution-converted images by one input of a multi-valued image scanner.

[Explanation of symbols]

 1 image input device (reader unit) 2 image output device (printer unit) 3 external device 4 fax unit 5 file unit 6 external storage device 7 computer interface unit 8 computer terminal device 9 image memory unit 10 core unit

Continuation of front page (51) Int.Cl. ⁶ Identification number Internal reference number FI Technical display location G06F 15/68 320Z (72) Inventor Yuka Nagai 3-30-2 Shimomaruko, Ota-ku, Tokyo Canon Inc. (72) Inventor Eiji Ohara 3-30-2 Shimomaruko, Ota-ku, Tokyo Canon Inc.

Claims (14)

[Claims] 1. Input means for inputting multi-valued image data, first storage means for temporarily storing the multi-valued image data, and binary data corresponding to processing contents from a plurality of binarization methods. Means for selecting a binarization method, means for executing binarization processing by the selected binarization method a plurality of times on the stored multivalued image data, and image data after the binarization processing An image processing apparatus comprising: an output unit that outputs 2. A second storage means for temporarily storing the plurality of image data after the binarization processing, and a partial area of the plurality of image data stored in the second storage means. Means for synthesizing the image data stored in the first storage means and image data stored in the second storage means corresponding to the partial area, and the output means includes: The image processing device according to claim 1, wherein the combined image data is output. 3. Input means for inputting multi-valued image data, first storage means for temporarily storing the multi-valued image data, and means for selecting a resolution according to processing contents from a plurality of resolutions. And a means for performing resolution conversion processing on the stored multi-valued image data a plurality of times according to the selected resolution, and an output means for outputting the image data after the resolution conversion processing. Image processing device. 4. A second storage means for temporarily storing the plurality of image data after the resolution conversion processing, and a partial area of the plurality of image data stored in the second storage means are specified. Means for synthesizing the image data stored in the first storage means with the image data stored in the second storage means corresponding to the partial area, and the output means The image processing apparatus according to claim 3, wherein the subsequent image data is output. 5. Input means for inputting multi-valued image data, first storage means for temporarily storing the multi-valued image data, and binary data corresponding to processing contents from a plurality of binarization methods. Means for selecting a binarization method, means for selecting a resolution according to processing contents from a plurality of resolutions, and binarization by the selected binarization method for the stored multi-valued image data Processing, resolution conversion processing according to the selected resolution, or means for executing the binarization processing and resolution conversion processing a plurality of times, and output means for outputting the image data after the binarization processing. A characteristic image processing device. 6. A second storage unit for temporarily storing a plurality of image data after the binarization process, the resolution conversion process, or the binarization process and the resolution conversion process. A means for specifying a partial area of the plurality of image data stored in the second storage means, and a second storage means corresponding to the image data and the partial area stored in the first storage means. The image processing apparatus according to claim 5, further comprising a unit configured to combine the stored image data, wherein the output unit outputs the combined image data. 7. The image processing apparatus according to claim 1, wherein the binarization process is a simple binarization process. 8. The binarization process according to claim 1, wherein the binarization process is a binarization process using a variable slice level in which the slice level varies from the values of pixels around the pixel of interest. The image processing device according to item 1. 9. The image processing apparatus according to claim 1, wherein the binarization process is an error diffusion binarization process. 10. The image processing apparatus according to claim 1, wherein the input unit is an apparatus that optically reads an image. . 11. The image processing according to claim 1, wherein the input unit has an interface with a host computer and inputs image data from the host computer. apparatus. 12. The image processing apparatus according to claim 1, wherein the input unit inputs image data from a storage device connected to the outside of the image processing apparatus. . 13. The image processing apparatus according to claim 1, wherein the output unit is a printer device. 14. The image processing apparatus according to claim 1, wherein the output unit is a communication device connected to the outside of the image processing apparatus.