JPH06132432A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPH06132432A
JPH06132432A JP4276933A JP27693392A JPH06132432A JP H06132432 A JPH06132432 A JP H06132432A JP 4276933 A JP4276933 A JP 4276933A JP 27693392 A JP27693392 A JP 27693392A JP H06132432 A JPH06132432 A JP H06132432A
Authority
JP
Japan
Prior art keywords
substrate
main surface
etching
separation groove
chip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP4276933A
Other languages
Japanese (ja)
Other versions
JP2922066B2 (en
Inventor
Kazuki Tatsuoka
一樹 立岡
Masanori Hirose
正則 広瀬
Kunihiko Kanazawa
邦彦 金澤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electronics Corp filed Critical Matsushita Electronics Corp
Priority to JP27693392A priority Critical patent/JP2922066B2/en
Publication of JPH06132432A publication Critical patent/JPH06132432A/en
Application granted granted Critical
Publication of JP2922066B2 publication Critical patent/JP2922066B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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  • Junction Field-Effect Transistors (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

PURPOSE:To obtain a GaAs IC wherein its uniformity and its controllability are excellent by a method wherein a chip isolation groove is formed on the surface of a substrate by an etching operation, the substrate is made thin down to a thickness which does not reach the bottom of the groove from the rear side and a PHS is formed by a vapor deposition method or the like. CONSTITUTION:A surface side of a GaAs substrate 2 on which a semiconductor element part has been formed is etched, a groove for chip isolation is formed, a support sheet 5 is pasted and fixed by using a wax material 4, the rear side is then polished and the substrate is made thin dawn to 30 to 60mum. In addition, an Ni layer 6 and an Au layer 7 as substrate metals to be used as electricity- feeding layers in a plating operation are vapor-deposited, and an Au layer 8 to be used as a PHS is formed by an electrolytic plating operation. A resist pattern 9 is formed, the Au layer 8 is etched and removed along a chip isolation position. Lastly, the Ni layer 6 is etched and removed, the GaAs substrate 2 is etched until the isolation groove is reached, and elements are isolated. Even when an etch rate is irregular, the element part is not damaged and the shape of the surface is not spoiled.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、プレーティドヒートシ
ンク(Plated Heatsink:PHS)を有する高周波高出
力GaAsFETおよびIC等の半導体装置の製造方法
に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a high frequency and high power GaAs FET having a plated heat sink (PHS) and a method of manufacturing a semiconductor device such as an IC.

【0002】[0002]

【従来の技術】高出力GaAsFETおよびICでは熱
抵抗低減のため基板であるGaAsを薄く研磨し、さら
にこの基板裏面上にヒートシンクとなる金属層を形成す
る必要がある。従来、このようなGaAsICを製造す
る方法としては、例えば基板の表側主面に半導体素子部
を形成した後に、基板裏面を所定の厚さまで研磨し、さ
らに蒸着およびメッキによってヒートシンクとなる金属
層(PHS)を形成した後に、チップ分離位置の金属層
をフォトリソ工程および金属層のエッチング工程によっ
て除去し、さらにこの金属層の除去された窓の部分から
基板であるGaAsをエッチングにより基板表面に達す
るまで除去することによってチップを分離する方法がと
られていた。
2. Description of the Related Art In high-power GaAs FETs and ICs, it is necessary to thinly polish GaAs, which is a substrate, in order to reduce thermal resistance, and to form a metal layer to be a heat sink on the back surface of the substrate. Conventionally, as a method of manufacturing such a GaAs IC, for example, after a semiconductor element portion is formed on the front main surface of a substrate, the back surface of the substrate is polished to a predetermined thickness, and further a metal layer (PHS) to be a heat sink is formed by vapor deposition and plating. ) Is formed, the metal layer at the chip separation position is removed by a photolithography process and an etching process of the metal layer, and GaAs, which is the substrate, is removed by etching from the window portion where the metal layer is removed until the substrate surface is reached. By doing so, a method of separating the chips has been adopted.

【0003】以下従来の製造方法について、説明する。
図2(a)〜(h)は従来のPHSを有する高出力Ga
AsICの製造方法を示す図である。同図(a)におい
て、1は基板2表面側に形成された半導体素子部であ
る。同図(b)に示すように支持板5にワックス材4を
用いて基板2を貼付けて固定し、基板2の裏面側を研磨
することにより30〜60μmまで薄くする。さらに同
図(c)に示すように、ディップエッチして表面を清浄
化した後、メッキ時の給電層となる下地金属のNi6と
Au7を蒸着する。同図(d)は下地金属上にPHSと
なるAu8を電解メッキによって形成する工程である。
この後、同図(e)に示すようにAuをチップ分離位置
に沿ってエッチング除去するためのレジストパターン9
を形成し、同図(f)に示すようにAu7,8エッチし
た後にレジストを除去する。最後に同図(g)に示すよ
うにNi6をエッチング除去し、続いて同図(h)に示
すように基板2であるGaAsをエッチングし素子の分
離を行う。
A conventional manufacturing method will be described below.
2A to 2H show high-power Ga having a conventional PHS.
It is a figure which shows the manufacturing method of AsIC. In FIG. 1A, 1 is a semiconductor element portion formed on the front surface side of the substrate 2. As shown in FIG. 3B, the substrate 2 is attached and fixed to the support plate 5 using the wax material 4, and the back surface side of the substrate 2 is polished to reduce the thickness to 30 to 60 μm. Further, as shown in FIG. 3C, after dip-etching to clean the surface, Ni6 and Au7 as base metals to be a power feeding layer during plating are deposited. FIG. 3D shows a process of forming Au8, which becomes PHS, on the base metal by electrolytic plating.
After that, as shown in FIG. 7E, a resist pattern 9 for removing Au by etching along the chip separation position is formed.
Is formed, and as shown in FIG. 3F, after etching Au 7 and 8, the resist is removed. Finally, Ni6 is removed by etching as shown in FIG. 9G, and subsequently, GaAs as the substrate 2 is etched as shown in FIG.

【0004】[0004]

【発明が解決しようとする課題】しかしながら上記の従
来の製造方法では、基板であるGaAsエッチングのエ
ンドポイントがはっきりしにくいため、エッチングの進
行ばらつきによってチップ分離が完全に行われない箇所
がウエハ中に生じたり、またエッチング時間が長くなっ
てしまうとウエットエッチの場合サイドエッチが進行し
チップ表面で素子部へのダメージや外観,形状等の不良
が発生しやすいという課題を有していた。
However, in the above-described conventional manufacturing method, since the end point of GaAs etching, which is the substrate, is difficult to be clearly defined, there are portions in the wafer where chip separation is not completely performed due to variations in etching progress. If the etching occurs, or if the etching time becomes long, in the case of wet etching, side etching progresses, and there is a problem that damage to the element portion on the chip surface and defects such as appearance and shape are likely to occur.

【0005】本発明は上記の課題を解決するもので、P
HSを有する高出力GaAsICの均一性および制御性
に優れた半導体装置の製造方法を提供することを目的と
する。
The present invention is intended to solve the above-mentioned problems.
It is an object of the present invention to provide a method for manufacturing a semiconductor device which is excellent in uniformity and controllability of a high-power GaAs IC having HS.

【0006】[0006]

【課題を解決するための手段】この目的を達成するため
に本発明の半導体装置の製造方法は、半導体素子部を形
成した基板の第一主面の、チップ分離ラインにエッチン
グによって所定の幅および深さの分離溝を形成する工程
と、前記基板をその基板の第二主面側から第一主面側に
形成された前記分離溝底部に達しない所定の厚さになる
まで薄くする工程と、前記基板第二主面に蒸着,メッ
キ,エッチング等の方法によりヒートシンクとなる金属
層(PHS)を形成する工程と、さらにこの金属層の窓
の部分より、基板を分離溝に達するまでエッチングする
ことによってチップを分離する工程とを有する構成によ
る。
In order to achieve this object, a method of manufacturing a semiconductor device according to the present invention provides a chip separation line on a first main surface of a substrate on which a semiconductor element portion is formed with a predetermined width by etching. Forming a separation groove having a depth; and thinning the substrate from a second main surface side of the substrate to a predetermined thickness that does not reach the separation groove bottom formed on the first main surface side. A step of forming a metal layer (PHS) to be a heat sink on the second main surface of the substrate by a method such as vapor deposition, plating and etching, and further etching the substrate from the window portion of the metal layer until reaching the separation groove. And a step of separating the chips.

【0007】[0007]

【作用】上記構成により、裏面側より基板であるGaA
sをエッチングする際に、チップ分離用に形成しておい
た溝にエッチングが到達した時点でGaAs基板のエッ
チングのエンドポイントとすることができ、またウエハ
内でのエッチングの進行ばらつきに対応するためエッチ
ング時間を余分にとり、分離不十分な所をなくすように
しても、予め表面側より形成されている分離溝の深さ分
だけエッチングマージンとなるため、ウエットエッチの
際のサイドエッチの進行によるチップ表面での素子部へ
のダメージや外観,形状等の不良発生がなく、均一性お
よび制御性に優れたGaAsICの製造を可能にするこ
とができる。
With the above structure, the GaA which is the substrate from the back side
When etching s, it can be used as the etching end point of the GaAs substrate when the etching reaches the groove formed for chip separation, and it corresponds to the variation in the etching progress within the wafer. Even if extra etching time is taken to eliminate insufficient separation, the etching margin will be the depth of the separation groove formed from the surface side in advance. It is possible to manufacture a GaAs IC excellent in uniformity and controllability without causing damages to the element portion on the surface or causing defects such as appearance and shape.

【0008】[0008]

【実施例】以下本発明の一実施例について図面を参照し
ながら説明する。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings.

【0009】図1(a)〜(j)は本発明の一実施例に
おけるGaAsICからなる半導体装置の製造方法を示
す工程断面図である。同図(a)において、1は基板表
面側に形成された半導体素子部、2はGaAs基板であ
る。同図(b)は、チップ分離用の溝を形成するための
レジストパターン3の形成工程であり、同図(c)はエ
ッチング後、レジスト除去した状態である。この後、同
図(d)に示すようにワックス材4を用いて支持板5に
基板2を貼付けて固定し、裏面側を研磨等により30〜
60μmまで基板2を薄くする。さらに同図(e)に示
すように、ディップエッチして表面を清浄化した後、メ
ッキ時の給電層となる下地金属のNi6とAu7を蒸着
する。同図(f)は下地金属上にPHSとなるAu8を
電解メッキによって形成する工程である。この後、同図
(g)に示すようにAuをチップ分離位置に沿ってエッ
チング除去するためのレジストパターン9を形成し、同
図(h)に示すようにAuエッチした後にレジスト9を
除去する。最後に同図(i)に示すようにNiをエッチ
ング除去し、続いて同図(j)に示すように、基板2で
あるGaAsを予め表面側より形成しておいた分離溝に
達するまでエッチングし素子の分離を行う。
1 (a) to 1 (j) are process sectional views showing a method of manufacturing a semiconductor device made of a GaAs IC in an embodiment of the present invention. In FIG. 1A, 1 is a semiconductor element portion formed on the substrate surface side, and 2 is a GaAs substrate. FIG. 6B shows a step of forming a resist pattern 3 for forming a groove for chip separation, and FIG. 6C shows a state where the resist is removed after etching. After that, as shown in FIG. 3D, the substrate 2 is attached and fixed to the supporting plate 5 using the wax material 4, and the back surface side is polished to 30 to 30%.
The substrate 2 is thinned to 60 μm. Further, as shown in FIG. 7E, after dip-etching to clean the surface, Ni6 and Au7, which are base metals to be a power supply layer during plating, are deposited. FIG. 6F shows a process of forming Au8, which becomes PHS, on the base metal by electrolytic plating. After that, a resist pattern 9 for etching and removing Au along the chip separation position is formed as shown in FIG. 9G, and then the resist 9 is removed after Au etching as shown in FIG. . Finally, Ni is removed by etching as shown in (i) of the same figure, and subsequently, as shown in (j) of the figure, GaAs which is the substrate 2 is etched until reaching a separation groove formed in advance from the surface side. Then, the elements are separated.

【0010】このような製造工程でチップ分離を行う
と、GaAsエッチングのエッチング速度がばらついて
も各チップの素子部にダメージを与えたり、表面の形状
を損なったりすることなく確実に分離を行うことができ
る。すなわち、ウエハ内で最も早くGaAsエッチング
が溝に達した所では最もエッチングの遅いところが溝に
達するまでサイドエッチが進行するが、溝の幅をGaA
sエッチの進行する幅より広くしておけば余分なエッチ
ングが深さ方向に進まない。また、さらに余分にエッチ
ングを行って深さ方向にエッチングされても、素子の表
面側に達するまでには溝の深さ分がマージンとなる。従
って、ウエハ全体のチップ分離を確実に行い、かつ素子
部にダメージを与えたり、表面の形状を損なったりする
可能性を極めて小さくできる。特に、エッチングばらつ
きやサイドエッチの大きいウエットエッチによってチッ
プ分離を行う際に有効である。
When the chip separation is performed in such a manufacturing process, even if the etching rate of GaAs etching varies, the chip separation can be surely performed without damaging the element portion of each chip or damaging the surface shape. You can That is, in the place where the GaAs etching reaches the groove earliest in the wafer, the side etching progresses until the portion where the etching is latest reaches the groove.
s Excessive etching does not proceed in the depth direction if the width is wider than the width in which etching progresses. Further, even if extra etching is performed to etch in the depth direction, a margin is the depth of the groove before reaching the surface side of the element. Therefore, the chips can be reliably separated from the entire wafer, and the possibility of damaging the element portion and damaging the surface shape can be extremely reduced. In particular, it is effective when performing chip separation by wet etching, which has large etching variations and side etching.

【0011】ここで、本実施例ではヒートシンクである
Auメッキをウエハ全体で行った後にエッチングによっ
て分離したが、下地金属を形成した後にレジストパター
ンを形成し選択メッキによって形成してもかまわない。
下地金属も、本実施例のNi/Auの他にも、Niの
み、Ti/Au、Tiのみ、Cr/Au、Crのみ等が
考えられる。
In this embodiment, Au plating, which is a heat sink, is formed on the entire wafer and then separated by etching. However, a resist pattern may be formed after forming a base metal and selective plating may be formed.
As the base metal, in addition to Ni / Au of this embodiment, only Ni, Ti / Au, Ti only, Cr / Au, Cr only, etc. can be considered.

【0012】また、チップ分離をエッチングでなくダイ
シングによって行う工程も考えられる。すなわち、図1
(h)あるいは(i)まで工程を進めた後、PHSのエ
ッチングの窓の部分の幅より狭い刃幅のブレードによっ
て、裏面側から予め表面側より形成しておいた電離溝に
達しかつ支持板に達しない深さまでダイシングを行う方
法である。この場合も、ワックス材の厚みと溝の深さ分
だけがダイシング深さのマージンとなるため、分離溝が
ない場合に比べてチップ分割が不完全になったり、支持
板を損傷したりする可能性が極めて小さくでき再現性に
優れた安定な工程を得ることができる。
Further, a process of separating the chips by dicing instead of etching can be considered. That is, FIG.
After the process is advanced to (h) or (i), a blade having a blade width narrower than the width of the window portion of the PHS etching reaches the ionization groove previously formed from the back surface side and the support plate. This is a method of dicing to a depth that does not reach Also in this case, since the thickness of the wax material and the depth of the groove are the margins of the dicing depth, chip division may be incomplete or the support plate may be damaged as compared with the case without the separation groove. It is possible to obtain a stable process with extremely low reproducibility and excellent reproducibility.

【0013】[0013]

【発明の効果】以上、説明したところから明らかなよう
に、本発明の半導体装置の製造方法は、半導体素子部を
形成した基板の第一主面の、チップ分離ラインにエッチ
ングによって所定の幅および深さの分離溝を形成する工
程と、上記基板をその基板の第二主面側から第一主面側
に形成された上記分離溝底部に達しない所定の厚さにな
るまで薄くする工程と、さらに第二主面側のチップ分離
溝の形成されていない所に蒸着,メッキ,エッチング等
の方法によりヒートシンクとなる金属層(PHS)を形
成する工程と、さらにこの金属層の窓の部分より、基板
を分離溝に達するまでエッチングまたはダイシングする
ことによってチップを分離する工程とを有する構成より
なり、PHS構造を有する再現性,均一性に優れた半導
体装置を提供できる。
As is apparent from the above description, the method of manufacturing a semiconductor device according to the present invention has a predetermined width and a predetermined width obtained by etching the chip separation line on the first main surface of the substrate on which the semiconductor element portion is formed. A step of forming a separation groove having a depth, and a step of thinning the substrate from a second main surface side of the substrate to a predetermined thickness that does not reach the separation groove bottom formed on the first main surface side. , A step of forming a metal layer (PHS) to be a heat sink by a method such as vapor deposition, plating, etching, etc. in a place where the chip separation groove on the second main surface side is not formed, and from the window portion of this metal layer. And a step of separating the chip by etching or dicing the substrate until it reaches the separation groove, and it is possible to provide a semiconductor device having a PHS structure with excellent reproducibility and uniformity. .

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の一実施例における半導体装置の製造方
法を示す工程断面図
FIG. 1 is a process sectional view showing a method for manufacturing a semiconductor device according to an embodiment of the present invention.

【図2】従来の半導体装置の製造方法を示す工程断面図FIG. 2 is a process sectional view showing a conventional method for manufacturing a semiconductor device.

【符号の説明】[Explanation of symbols]

1 半導体素子部 2 GaAs基板(基板) 3 レジストパターン 4 ワックス材 5 支持板 6 Ni 7 Au 8 Au(ヒートシンクとなる金属層) 9 レジスト 1 Semiconductor Element Section 2 GaAs Substrate (Substrate) 3 Resist Pattern 4 Wax Material 5 Support Plate 6 Ni 7 Au 8 Au (Metal Layer as Heat Sink) 9 Resist

Claims (5)

【特許請求の範囲】[Claims] 【請求項1】 半導体素子部を形成した基板の第一の主
面の、チップ分離ラインにエッチングによって所定の幅
および深さの分離溝を形成する工程と、前記基板をその
基板の第二主面側から、第一主面側に形成された前記分
離溝底部に達しないように、所定の厚さになるまで薄く
する工程と、前記基板第二主面に蒸着,メッキ等の方法
によりヒートシンクとなる金属層を形成する工程と、そ
の金属層上の、前記第一主面に形成された分離溝に対応
する領域にパターンの窓が開くようにレジストパターン
を形成する工程と、その窓の部分の前記金属層を除去す
る工程と、その金属層が除去された領域の基板第二主面
から前記分離溝に達するまでエッチングすることによっ
て各チップに分離する工程とを有することを特徴とする
半導体装置の製造方法。
1. A step of forming a separation groove of a predetermined width and depth in a chip separation line on a first main surface of a substrate on which a semiconductor element portion is formed by etching, and using the substrate as a second main surface of the substrate. From the surface side to a predetermined thickness so as not to reach the bottom of the separation groove formed on the first main surface side, and a heat sink by a method such as vapor deposition or plating on the second main surface of the substrate. And a step of forming a resist pattern so that a window of the pattern is opened in a region corresponding to the separation groove formed on the first main surface on the metal layer, and a step of forming the window. A step of removing the metal layer in a portion and a step of separating each chip by etching from the second main surface of the substrate in the region where the metal layer is removed to reach the separation groove. How to manufacture semiconductor devices Law.
【請求項2】 その金属層が除去された領域の基板第二
主面から前記分離溝に達するまでエッチングすることに
よって各チップを分離する工程に代えて、その金属層が
除去された領域に沿って基板をダイシングし、各チップ
に分離する工程としたことを特徴とする請求項1記載の
半導体装置の製造方法。
2. Instead of the step of separating each chip by etching from the second main surface of the substrate in the region where the metal layer is removed to reach the separation groove, the region along the region where the metal layer is removed is replaced. 2. The method for manufacturing a semiconductor device according to claim 1, wherein a step of dicing the substrate to separate into chips is performed.
【請求項3】 半導体素子部を形成した基板の第一主面
の、チップ分離ラインにエッチングによって所定の幅お
よび深さの分離溝を形成する工程と、前記基板をその基
板の第二主面側から、第一主面側に形成された前記分離
溝底部に達しないように、所定の厚さになるまで薄くす
る工程と、前記基板第二主面に蒸着または無電界メッキ
によって金属薄膜を形成する工程と、その金属薄膜上
の、前記第一主面に形成された分離溝に対応する領域に
レジストが被覆するようにレジストパターンを形成する
工程と、そのレジストパターンをマスクとして選択的に
ヒートシンクとなる金属層をメッキによって形成する工
程と、前記レジストを除去した後にこの部分の金属薄膜
をエッチングによって除去する工程と、その金属薄膜が
除去された領域の基板第二主面から前記分離溝に達する
までエッチングすることによって各チップに分離する工
程とを有することを特徴とする半導体装置の製造方法。
3. A step of forming a separation groove of a predetermined width and depth in a chip separation line on a first main surface of a substrate on which a semiconductor element portion is formed by etching, and using the substrate as a second main surface of the substrate. Side, a step of thinning to a predetermined thickness so as not to reach the bottom of the separation groove formed on the first main surface side, and a metal thin film on the second main surface of the substrate by vapor deposition or electroless plating. A step of forming, a step of forming a resist pattern so that the resist covers the region corresponding to the separation groove formed on the first main surface on the metal thin film, and selectively using the resist pattern as a mask A step of forming a metal layer to be a heat sink by plating, a step of removing the metal thin film in this portion by etching after removing the resist, and a substrate in a region where the metal thin film is removed And a step of separating each chip by etching from the second main surface until the separation groove is reached.
【請求項4】 その金属薄膜が除去された領域の基板第
二主面から前記分離溝に達するまでエッチングすること
によって各チップに分離する工程に代えて、その金属薄
膜が除去された領域に沿って基板をダイシングし、各チ
ップに分離する工程としたことを特徴とする請求項3記
載の半導体装置の製造方法。
4. Instead of the step of separating each chip by etching from the second main surface of the substrate in the region where the metal thin film is removed to reach the separation groove, the metal thin film is removed along the region where the metal thin film is removed. 4. The method of manufacturing a semiconductor device according to claim 3, wherein the step of dicing the substrate to separate into chips is performed.
【請求項5】 基板をその基板の第二主面側から、第一
主面側に形成された前記分離溝底部に達しないように、
所定の厚さになるまで薄くする工程が、基板の第一主面
側にワックス材等により支持板を張り付けた後に、前記
基板をその基板の第二主面から、第一主面側に形成され
た分離溝の底部に達しないように、所定の厚さになるま
で薄くする工程としたことを特徴とする請求項1,2,
3または4記載の半導体装置の製造方法。
5. The substrate is arranged so as not to reach the bottom of the separation groove formed on the first main surface side from the second main surface side of the substrate.
The step of thinning to a predetermined thickness is such that after the support plate is attached to the first main surface side of the substrate with a wax material or the like, the substrate is formed from the second main surface of the substrate to the first main surface side. 2. The step of thinning until a predetermined thickness is reached so as not to reach the bottom of the formed separation groove.
3. The method for manufacturing a semiconductor device according to 3 or 4.
JP27693392A 1992-10-15 1992-10-15 Method for manufacturing semiconductor device Expired - Fee Related JP2922066B2 (en)

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Application Number Priority Date Filing Date Title
JP27693392A JP2922066B2 (en) 1992-10-15 1992-10-15 Method for manufacturing semiconductor device

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Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6184109B1 (en) 1997-07-23 2001-02-06 Kabushiki Kaisha Toshiba Method of dividing a wafer and method of manufacturing a semiconductor device
US6294439B1 (en) 1997-07-23 2001-09-25 Kabushiki Kaisha Toshiba Method of dividing a wafer and method of manufacturing a semiconductor device
US6337258B1 (en) 1999-07-22 2002-01-08 Kabushiki Kaisha Toshiba Method of dividing a wafer
US6461889B1 (en) 1998-08-17 2002-10-08 Nec Corporation Method of fabricating semiconductor device with diamond substrate
KR100411970B1 (en) * 1995-10-17 2004-03-30 미크로나스 게엠베하 Method of separating elements associated within a body, particularly electronic elements
US7452752B2 (en) 2003-11-27 2008-11-18 3M Innovative Properties Company Production method of semiconductor chip
US7534498B2 (en) 2002-06-03 2009-05-19 3M Innovative Properties Company Laminate body, method, and apparatus for manufacturing ultrathin substrate using the laminate body
US8038839B2 (en) 2002-06-03 2011-10-18 3M Innovative Properties Company Laminate body, method, and apparatus for manufacturing ultrathin substrate using the laminate body

Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100411970B1 (en) * 1995-10-17 2004-03-30 미크로나스 게엠베하 Method of separating elements associated within a body, particularly electronic elements
US6184109B1 (en) 1997-07-23 2001-02-06 Kabushiki Kaisha Toshiba Method of dividing a wafer and method of manufacturing a semiconductor device
US6294439B1 (en) 1997-07-23 2001-09-25 Kabushiki Kaisha Toshiba Method of dividing a wafer and method of manufacturing a semiconductor device
US6461889B1 (en) 1998-08-17 2002-10-08 Nec Corporation Method of fabricating semiconductor device with diamond substrate
US6337258B1 (en) 1999-07-22 2002-01-08 Kabushiki Kaisha Toshiba Method of dividing a wafer
US7534498B2 (en) 2002-06-03 2009-05-19 3M Innovative Properties Company Laminate body, method, and apparatus for manufacturing ultrathin substrate using the laminate body
US7988807B2 (en) 2002-06-03 2011-08-02 3M Innovative Properties Company Laminate body, method, and apparatus for manufacturing ultrathin substrate using the laminate body
US8038839B2 (en) 2002-06-03 2011-10-18 3M Innovative Properties Company Laminate body, method, and apparatus for manufacturing ultrathin substrate using the laminate body
US8789569B2 (en) 2002-06-03 2014-07-29 3M Innovative Properties Company Apparatus for manufacturing ultrathin substrate using a laminate body
US8800631B2 (en) 2002-06-03 2014-08-12 3M Innovative Properties Company Laminate body, method, and apparatus for manufacturing ultrathin substrate using the laminate body
US7452752B2 (en) 2003-11-27 2008-11-18 3M Innovative Properties Company Production method of semiconductor chip

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