JP2000012490A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JP2000012490A
JP2000012490A JP17241198A JP17241198A JP2000012490A JP 2000012490 A JP2000012490 A JP 2000012490A JP 17241198 A JP17241198 A JP 17241198A JP 17241198 A JP17241198 A JP 17241198A JP 2000012490 A JP2000012490 A JP 2000012490A
Authority
JP
Japan
Prior art keywords
semiconductor
substrate
semiconductor device
semiconductor substrate
manufacturing process
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP17241198A
Other languages
Japanese (ja)
Inventor
Hiroyuki Masato
宏幸 正戸
Yoshito Ikeda
義人 池田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP17241198A priority Critical patent/JP2000012490A/en
Publication of JP2000012490A publication Critical patent/JP2000012490A/en
Pending legal-status Critical Current

Links

Abstract

PROBLEM TO BE SOLVED: To provide a method for manufacturing a semiconductor device with high yield while protecting a semiconductor substrate against crack and warp. SOLUTION: A plurality of semiconductor elements 5 are formed on a semiconductor substrate 1 secured such that the surface arranged with the semiconductor elements 5 faces a supporting substrate 6. The semiconductor substrate 1 is divided for each semiconductor element 5 and the supporting substrate 6 is bonded to an expanding/contracting sheet 10. The supporting substrate 6 is divided for each semiconductor element 5 and separated from the expanding/contracting sheet 10 along with the semiconductor element 5. The semiconductor substrate 1 is formed on a package 11 and then the supporting substrate 6 is separated therefrom.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、半導体素子を歩留
まりよく製造し、パッケージに実装するための、半導体
装置の製造方法に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device for manufacturing a semiconductor element with a high yield and mounting it on a package.

【0002】[0002]

【従来の技術】まず、従来の半導体装置の製造方法につ
いて、図28ないし図37を用いて説明する。
2. Description of the Related Art First, a conventional method for manufacturing a semiconductor device will be described with reference to FIGS.

【0003】図28に示すように、GaAsで構成され
た厚さ600μmの半導体基板1上に、ソース電極2、
ゲート電極3、ドレイン電極4を形成してなる半導体素
子5を複数形成する。
As shown in FIG. 28, a source electrode 2 and a source electrode 2 are formed on a semiconductor substrate 1 made of GaAs and having a thickness of 600 μm.
A plurality of semiconductor elements 5 each including the gate electrode 3 and the drain electrode 4 are formed.

【0004】次に、図29に示すように、半導体基板1
と石英からなる支持基板6とをエレクトロンワックス7
により接着し、図30に示すように、半導体基板1の厚
さが50μmとなるまで半導体基板1の裏面を研磨す
る。その後、後に行うダイスボンド工程時の半導体基板
1の安定性および放熱性を向上するために、図31に示
すように、蒸着により半導体基板1上にCrやAu等で構成
される金属膜9を形成する。
[0004] Next, as shown in FIG.
And a support substrate 6 made of quartz and an electron wax 7
Then, as shown in FIG. 30, the back surface of the semiconductor substrate 1 is polished until the thickness of the semiconductor substrate 1 becomes 50 μm. Thereafter, in order to improve the stability and heat dissipation of the semiconductor substrate 1 in the die bonding step performed later, as shown in FIG. Form.

【0005】次に、図32に示すように、ワックスリム
ーバーにより、半導体基板1から支持基板6およびエレ
クトロンワックス7を分離する。
Next, as shown in FIG. 32, the support substrate 6 and the electron wax 7 are separated from the semiconductor substrate 1 by a wax remover.

【0006】次に、図33に示すように、伸縮性を有す
るダイシングシート10を半導体基板1の金属膜9が形
成された側に装着する。そして、ダイシングソー(図示
せず)により、図34に示すように半導体素子5毎に半
導体基板1および金属膜9を切断し、図35に示すよう
に切断により形成された個々の半導体基板1を金属膜9
とともにダイシングシート10から剥がし取る。
Next, as shown in FIG. 33, a dicing sheet 10 having elasticity is mounted on the side of the semiconductor substrate 1 on which the metal film 9 is formed. Then, the semiconductor substrate 1 and the metal film 9 are cut for each semiconductor element 5 as shown in FIG. 34 by a dicing saw (not shown), and the individual semiconductor substrates 1 formed by cutting as shown in FIG. Metal film 9
At the same time, it is peeled off from the dicing sheet 10.

【0007】最後に、図36に示すように半導体基板1
を半導体用のパッケージ11上に形成し、図37に示す
ように、ワイヤボンドにより、半導体素子5とパッケー
ジ11との配線を行う。
[0007] Finally, as shown in FIG.
Is formed on a semiconductor package 11, and wiring between the semiconductor element 5 and the package 11 is performed by wire bonding as shown in FIG.

【0008】[0008]

【発明が解決しようとする課題】しかしながら、従来の
半導体装置の製造方法では、支持基板およびエレクトロ
ンワックスをワックスリムーバーにより半導体基板から
分離する工程以降、半導体基板をパッケージ上に形成す
るまでの間の工程において、薄い半導体基板を支えるた
めの構造が存在せず、半導体基板に割れや反りが発生す
ることがあり、半導体装置の歩留まりが著しく悪くな
る。
However, in the conventional method of manufacturing a semiconductor device, the steps from the step of separating the support substrate and the electron wax from the semiconductor substrate by the wax remover to the step of forming the semiconductor substrate on the package are performed. In this case, there is no structure for supporting the thin semiconductor substrate, and the semiconductor substrate may be cracked or warped, thereby significantly reducing the yield of the semiconductor device.

【0009】なお、半導体基板を薄く形成するのは、半
導体素子で生じる熱を効率的に放出するためであるが、
半導体基板の厚さが150μm以下のとき、特に割れや
反りが発生しやすい。
The reason why the semiconductor substrate is formed thin is to efficiently release heat generated in the semiconductor element.
When the thickness of the semiconductor substrate is 150 μm or less, cracks and warpage are particularly likely to occur.

【0010】本発明は、半導体基板に割れや反りが発生
しにくく、歩留まりの良い半導体装置の製造方法を提供
することを目的とする。
An object of the present invention is to provide a method for manufacturing a semiconductor device which is less likely to crack or warp in a semiconductor substrate and has a good yield.

【0011】[0011]

【課題を解決するための手段】本発明の半導体措置の製
造方法は、半導体基板上に複数の半導体素子を形成し、
前記半導体素子が形成された前記半導体基板の表面と、
支持基板とが対向するように、前記半導体基板と前記支
持基板とを固着し、前記半導体基板を前記半導体素子毎
に分割し、前記支持基板を伸縮性シートに固着し、前記
支持基板を前記半導体素子毎に分割し、分割された前記
支持基板を前記半導体素子とともに前記伸縮性シートか
ら分離し、前記半導体基板をパッケージ上に形成し、そ
の後前記支持基板を前記半導体基板から分離する。
According to the present invention, there is provided a method for manufacturing a semiconductor device, comprising: forming a plurality of semiconductor elements on a semiconductor substrate;
A surface of the semiconductor substrate on which the semiconductor element is formed,
The semiconductor substrate and the support substrate are fixed so that the support substrate faces each other, the semiconductor substrate is divided for each of the semiconductor elements, the support substrate is fixed to an elastic sheet, and the support substrate is fixed to the semiconductor substrate. The support substrate is divided for each element, the divided support substrate is separated from the stretchable sheet together with the semiconductor element, the semiconductor substrate is formed on a package, and then the support substrate is separated from the semiconductor substrate.

【0012】本発明によれば、半導体基板は、パッケー
ジ上に形成される工程に至るまで、支持基板によって支
えられているために、割れや反りが発生しにくい。
According to the present invention, since the semiconductor substrate is supported by the support substrate until the step of forming on the package, cracks and warpages hardly occur.

【0013】[0013]

【発明の実施の形態】以下本発明の実施の形態につい
て、図1から図27を用いて説明する。
Embodiments of the present invention will be described below with reference to FIGS. 1 to 27.

【0014】(実施の形態1)図1ないし図12は、本
発明の実施の形態1における半導体装置の製造工程を示
す図である。まず、図1に示すように、径が3インチ、
厚さ600μmのGaAsで構成された半導体基板1上
に、ソース電極2、ゲート電極3、ドレイン電極4を形
成してなる半導体素子5を複数形成する。
(First Embodiment) FIGS. 1 to 12 are views showing a manufacturing process of a semiconductor device according to a first embodiment of the present invention. First, as shown in FIG.
A plurality of semiconductor elements 5 each having a source electrode 2, a gate electrode 3, and a drain electrode 4 are formed on a semiconductor substrate 1 made of GaAs having a thickness of 600 μm.

【0015】次に、図2に示すように、半導体基板1と
石英からなる支持基板6とをエレクトロンワックス7に
より接着し、図3に示すように、半導体基板1の厚さが
50μmとなるまで、半導体基板1の裏面を研磨する。
そして、図4に示すように、半導体基板1の裏面の個々
の半導体素子5に対応する部分にそれぞれフォトレジス
ト8を形成し、これをマスクとしてドライエッチングを
行うことにより、図5に示すように、半導体基板1が半
導体素子5毎に分割されるように半導体基板1の一部を
除去する。そして、後に行うダイスボンド工程時の半導
体基板1の密着性を向上するために、図6に示すよう
に、蒸着により半導体基板1上にCrやAu等で構成される
金属膜9を形成する。
Next, as shown in FIG. 2, the semiconductor substrate 1 and a support substrate 6 made of quartz are bonded by electron wax 7 until the thickness of the semiconductor substrate 1 becomes 50 μm as shown in FIG. Then, the back surface of the semiconductor substrate 1 is polished.
Then, as shown in FIG. 4, a photoresist 8 is formed on a portion corresponding to each semiconductor element 5 on the back surface of the semiconductor substrate 1 and dry etching is performed using the photoresist 8 as a mask, as shown in FIG. Then, a part of the semiconductor substrate 1 is removed so that the semiconductor substrate 1 is divided for each semiconductor element 5. Then, as shown in FIG. 6, a metal film 9 made of Cr, Au, or the like is formed on the semiconductor substrate 1 by vapor deposition in order to improve the adhesiveness of the semiconductor substrate 1 in a die bonding step performed later.

【0016】次に、図7および図8に示すように、支持
基板6を伸縮性を有するダイシングシート10に接着
し、支持基板6をダイシングソー(図示せず)により半
導体素子5毎に分割する。
Next, as shown in FIGS. 7 and 8, the support substrate 6 is bonded to a dicing sheet 10 having elasticity, and the support substrate 6 is divided into semiconductor elements 5 by a dicing saw (not shown). .

【0017】また、図9および図10に示すように、支
持基板6を半導体基板1および半導体素子5とともにダ
イシングシート10から取り剥がし、半導体基板1を半
導体用のパッケージ11上に、支持基板6が上側となる
ようにダイスボンドする。このとき、パッケージ11と
金属膜9との間にAuSn箔や半田等、低温で溶融する
金属を形成すれば、パッケージ11と金属膜9との密着
性が良好となる。その後、図11に示すように支持基板
6およびエレクトロンワックス7をワックスリムーバー
により半導体基板1から分離する。
As shown in FIGS. 9 and 10, the support substrate 6 is peeled off from the dicing sheet 10 together with the semiconductor substrate 1 and the semiconductor element 5, and the semiconductor substrate 1 is placed on a semiconductor package 11, and the support substrate 6 is removed. Die bond so that it is on the upper side. At this time, if a low melting metal such as AuSn foil or solder is formed between the package 11 and the metal film 9, the adhesion between the package 11 and the metal film 9 is improved. Thereafter, as shown in FIG. 11, the support substrate 6 and the electron wax 7 are separated from the semiconductor substrate 1 by a wax remover.

【0018】最後に、図12に示すように、ワイヤボン
ドにより、半導体素子5とパッケージ11との配線を行
う。
Finally, as shown in FIG. 12, wiring between the semiconductor element 5 and the package 11 is performed by wire bonding.

【0019】本発明の実施の形態1における半導体装置
の製造方法は、半導体基板1をパッケージ11に固定す
るまで、半導体基板1が支持基板6に固定されているた
め、半導体基板1に割れや反りが発生しにくい。このた
め、半導体装置の歩留まりが飛躍的に向上する。
In the method of manufacturing a semiconductor device according to the first embodiment of the present invention, the semiconductor substrate 1 is fixed to the support substrate 6 until the semiconductor substrate 1 is fixed to the package 11, so that the semiconductor substrate 1 is cracked or warped. Is less likely to occur. For this reason, the yield of semiconductor devices is dramatically improved.

【0020】なお、本発明は、半導体基板1をSi、I
nP、サファイア等、GaAs以外の材料を用いて構成
しても、同様の効果を有するものである。
In the present invention, the semiconductor substrate 1 is made of Si, I
The same effect can be obtained by using a material other than GaAs, such as nP or sapphire.

【0021】また、本実施の形態においては、半導体素
子5として、ソース電極2、ゲート電極3、ドレイン電
極4を有する電界効果型トランジスタを用いたが、バイ
ポーラトランジスタや、容量素子等を用いた場合も同様
の効果を得ることができる。
In this embodiment, a field effect transistor having a source electrode 2, a gate electrode 3, and a drain electrode 4 is used as the semiconductor element 5, but a bipolar transistor, a capacitor, or the like is used. Can obtain the same effect.

【0022】同様に、支持基板6の材料として、石英の
他、ガラス、Si等の材料を用いても同様の効果が得ら
れる。
Similarly, the same effect can be obtained by using a material such as glass or Si in addition to quartz as the material of the support substrate 6.

【0023】(実施の形態2)図13ないし図27は、
本発明の実施の形態1における半導体装置の製造方法に
かかる工程を示す図である。まず、図13に示すよう
に、径が3インチ、厚さ600μmのGaAsで構成さ
れた半導体基板1上に、ソース電極2、ゲート電極3、
ドレイン電極4を形成してなる半導体素子5を複数形成
する。
(Embodiment 2) FIG. 13 to FIG.
FIG. 5 is a diagram illustrating a process relating to the method for manufacturing the semiconductor device in the first embodiment of the present invention. First, as shown in FIG. 13, a source electrode 2, a gate electrode 3,
A plurality of semiconductor elements 5 each having the drain electrode 4 formed thereon are formed.

【0024】次に、図14に示すように、半導体基板1
と石英からなる支持基板6とをエレクトロンワックス7
により接着し、図15に示すように、半導体基板1の裏
面を厚さが50μmとなるまで研磨する。そして、図1
6に示すように、厚さ500オングストロームのチタン
と厚さ2000オングストロームの金を半導体基板1上
に蒸着してなる金属膜9を形成する。
Next, as shown in FIG.
And a support substrate 6 made of quartz and an electron wax 7
Then, as shown in FIG. 15, the back surface of the semiconductor substrate 1 is polished until the thickness becomes 50 μm. And FIG.
As shown in FIG. 6, a metal film 9 is formed by evaporating titanium having a thickness of 500 angstroms and gold having a thickness of 2000 angstroms on the semiconductor substrate 1.

【0025】次に、図17に示すように、金属膜9の表
面であって、半導体素子5に対応する部分以外の領域
に、フォトレジスト8を形成し、図18に示すように、
フォトレジスト8が形成された部分以外の領域に、厚さ
20μm〜30μmの金で構成される厚膜メッキ12を
メッキ法で形成し、アセトンによりフォトレジスト8を
除去する。金属膜9は、厚膜メッキ12の種金として、
また、厚膜メッキ12は、半導体素子5のヒートシンク
として作用する。
Next, as shown in FIG. 17, a photoresist 8 is formed on the surface of the metal film 9 except for the portion corresponding to the semiconductor element 5, and as shown in FIG.
A thick film plating 12 made of gold having a thickness of 20 μm to 30 μm is formed in a region other than the portion where the photoresist 8 is formed by a plating method, and the photoresist 8 is removed with acetone. The metal film 9 serves as seed metal for the thick film plating 12.
Further, the thick film plating 12 functions as a heat sink of the semiconductor element 5.

【0026】次に、図19に示すように、厚膜メッキ1
2をマスクとして金属膜9をKIエッチングにより除去
し、これにより露出した部分の半導体基板1を、図20
に示すようにドライエッチングにより除去する。
Next, as shown in FIG.
The metal film 9 is removed by KI etching using the mask 2 as a mask, and the exposed portion of the semiconductor substrate 1 is removed as shown in FIG.
As shown in FIG.

【0027】次に、図21および図22に示すように、
支持基板6を伸縮性を有するダイシングシート10に接
着し、支持基板6をダイシングソーにより半導体素子5
毎に分割する。
Next, as shown in FIGS. 21 and 22,
The support substrate 6 is adhered to a dicing sheet 10 having elasticity, and the support substrate 6 is bonded to the semiconductor element 5 using a dicing saw.
Divide each time.

【0028】さらに、図23および図24に示すよう
に、支持基板6を半導体基板1および半導体素子5とと
もにダイシングシート10から取り剥がし、半導体基板
1を半導体用のパッケージ11上に、支持基板6が上側
となるようにダイスボンドする。このとき、パッケージ
11と金属膜9との間にAuSn箔や半田等、低温で溶
融する金属を形成すれば、パッケージ11と金属膜9と
の密着性が良好となる。その後、図25に示すように支
持基板6およびエレクトロンワックス7をワックスリム
ーバーにより半導体基板1から分離する。
Further, as shown in FIGS. 23 and 24, the supporting substrate 6 is peeled off from the dicing sheet 10 together with the semiconductor substrate 1 and the semiconductor element 5, and the semiconductor substrate 1 is placed on a semiconductor package 11, and the supporting substrate 6 Die bond so that it is on the upper side. At this time, if a low melting metal such as AuSn foil or solder is formed between the package 11 and the metal film 9, the adhesion between the package 11 and the metal film 9 is improved. Thereafter, as shown in FIG. 25, the support substrate 6 and the electron wax 7 are separated from the semiconductor substrate 1 by a wax remover.

【0029】最後に、図26に示すように、ワイヤボン
ドにより、半導体素子5とパッケージ11との配線を行
う。
Finally, as shown in FIG. 26, wiring between the semiconductor element 5 and the package 11 is performed by wire bonding.

【0030】実施の形態2においては、半導体基板1に
ヒートシンクとして作用する厚膜メッキ12を形成する
ので、半導体装置の放熱性が向上する。
In the second embodiment, since the thick film plating 12 acting as a heat sink is formed on the semiconductor substrate 1, the heat dissipation of the semiconductor device is improved.

【0031】なお、実施の形態2における他の半導体装
置の製造方法として、基板にバイアホールを形成した半
導体装置の製造方法について説明する。
As another method of manufacturing a semiconductor device according to the second embodiment, a method of manufacturing a semiconductor device in which a via hole is formed in a substrate will be described.

【0032】図15に示した工程において、半導体基板
1にソース電極2に到達するバイアホールを設けておけ
ば、完成した半導体装置は、図27に示した構成とな
る。このとき、ソース電極2は、半導体基板1を通して
直接接地されているので、ソース電極2にワイヤボンデ
ィングを施す必要がなく、したがって寄生インダクタン
スの小さい半導体装置を得ることができる。
In the step shown in FIG. 15, if a via hole reaching the source electrode 2 is provided in the semiconductor substrate 1, the completed semiconductor device has the structure shown in FIG. At this time, since the source electrode 2 is directly grounded through the semiconductor substrate 1, it is not necessary to perform wire bonding to the source electrode 2, and therefore, a semiconductor device with small parasitic inductance can be obtained.

【0033】[0033]

【発明の効果】以上説明したように、本発明の半導体装
置の製造方法は、半導体基板がパッケージ上に形成され
る工程に至るまで、半導体基板が支持基板によって支え
られているために、半導体基板に割れや反りが発生しに
くい。したがって、半導体装置の歩留まりが著しく向上
する。
As described above, in the method of manufacturing a semiconductor device according to the present invention, the semiconductor substrate is supported by the support substrate until the semiconductor substrate is formed on the package. Cracks and warpage hardly occur. Therefore, the yield of the semiconductor device is significantly improved.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の実施の形態1における半導体装置の製
造工程を示す図
FIG. 1 is a view showing a manufacturing process of a semiconductor device according to a first embodiment of the present invention;

【図2】本発明の実施の形態1における半導体装置の製
造工程を示す図
FIG. 2 is a view showing a manufacturing process of the semiconductor device according to the first embodiment of the present invention;

【図3】本発明の実施の形態1における半導体装置の製
造工程を示す図
FIG. 3 is a diagram showing a manufacturing process of the semiconductor device according to the first embodiment of the present invention;

【図4】本発明の実施の形態1における半導体装置の製
造工程を示す図
FIG. 4 is a view showing a manufacturing process of the semiconductor device according to the first embodiment of the present invention;

【図5】本発明の実施の形態1における半導体装置の製
造工程を示す図
FIG. 5 is a diagram showing a manufacturing process of the semiconductor device according to the first embodiment of the present invention;

【図6】本発明の実施の形態1における半導体装置の製
造工程を示す図
FIG. 6 is a diagram illustrating a manufacturing process of the semiconductor device according to the first embodiment of the present invention;

【図7】本発明の実施の形態1における半導体装置の製
造工程を示す図
FIG. 7 is a view showing a manufacturing process of the semiconductor device according to the first embodiment of the present invention;

【図8】本発明の実施の形態1における半導体装置の製
造工程を示す図
FIG. 8 is a diagram showing a manufacturing process of the semiconductor device according to the first embodiment of the present invention;

【図9】本発明の実施の形態1における半導体装置の製
造工程を示す図
FIG. 9 is a view showing a manufacturing process of the semiconductor device according to the first embodiment of the present invention;

【図10】本発明の実施の形態1における半導体装置の
製造工程を示す図
FIG. 10 is a diagram showing a manufacturing process of the semiconductor device according to the first embodiment of the present invention;

【図11】本発明の実施の形態1における半導体装置の
製造工程を示す図
FIG. 11 is a diagram showing a manufacturing process of the semiconductor device according to the first embodiment of the present invention;

【図12】本発明の実施の形態1における半導体装置の
製造工程を示す図
FIG. 12 is a view showing a manufacturing process of the semiconductor device according to the first embodiment of the present invention;

【図13】本発明の実施の形態2における半導体装置の
製造工程を示す図
FIG. 13 is a diagram illustrating a manufacturing process of the semiconductor device according to the second embodiment of the present invention;

【図14】本発明の実施の形態2における半導体装置の
製造工程を示す図
FIG. 14 is a view showing a manufacturing process of the semiconductor device according to the second embodiment of the present invention;

【図15】本発明の実施の形態2における半導体装置の
製造工程を示す図
FIG. 15 is a diagram illustrating a manufacturing process of the semiconductor device according to the second embodiment of the present invention;

【図16】本発明の実施の形態2における半導体装置の
製造工程を示す図
FIG. 16 is a diagram illustrating a manufacturing process of the semiconductor device according to the second embodiment of the present invention;

【図17】本発明の実施の形態2における半導体装置の
製造工程を示す図
FIG. 17 is a diagram illustrating a manufacturing process of the semiconductor device according to the second embodiment of the present invention;

【図18】本発明の実施の形態2における半導体装置の
製造工程を示す図
FIG. 18 is a diagram illustrating a manufacturing process of the semiconductor device according to the second embodiment of the present invention;

【図19】本発明の実施の形態2における半導体装置の
製造工程を示す図
FIG. 19 is a diagram showing a manufacturing process of the semiconductor device according to the second embodiment of the present invention;

【図20】本発明の実施の形態2における半導体装置の
製造工程を示す図
FIG. 20 is a diagram showing a manufacturing process of the semiconductor device according to the second embodiment of the present invention;

【図21】本発明の実施の形態2における半導体装置の
製造工程を示す図
FIG. 21 is a diagram illustrating a manufacturing process of the semiconductor device according to the second embodiment of the present invention;

【図22】本発明の実施の形態2における半導体装置の
製造工程を示す図
FIG. 22 is a diagram illustrating a manufacturing process of the semiconductor device according to the second embodiment of the present invention;

【図23】本発明の実施の形態2における半導体装置の
製造工程を示す図
FIG. 23 is a diagram illustrating a manufacturing process of the semiconductor device according to the second embodiment of the present invention;

【図24】本発明の実施の形態2における半導体装置の
製造工程を示す図
FIG. 24 is a diagram illustrating a manufacturing process of the semiconductor device according to the second embodiment of the present invention;

【図25】本発明の実施の形態2における半導体装置の
製造工程を示す図
FIG. 25 is a diagram showing a manufacturing step of the semiconductor device according to the second embodiment of the present invention;

【図26】本発明の実施の形態2における半導体装置の
製造工程を示す図
FIG. 26 is a diagram illustrating a manufacturing process of the semiconductor device according to the second embodiment of the present invention;

【図27】本発明の実施の形態2における他の半導体装
置の製造工程を示す図
FIG. 27 is a view showing a manufacturing process of another semiconductor device according to the second embodiment of the present invention;

【図28】従来の半導体装置の製造工程を示す図FIG. 28 is a diagram showing a manufacturing process of a conventional semiconductor device.

【図29】従来の半導体装置の製造工程を示す図FIG. 29 is a view showing a manufacturing process of a conventional semiconductor device.

【図30】従来の半導体装置の製造工程を示す図FIG. 30 is a view showing a manufacturing process of a conventional semiconductor device.

【図31】従来の半導体装置の製造工程を示す図FIG. 31 is a view showing a manufacturing process of a conventional semiconductor device.

【図32】従来の半導体装置の製造工程を示す図FIG. 32 is a view showing a manufacturing process of a conventional semiconductor device.

【図33】従来の半導体装置の製造工程を示す図FIG. 33 is a diagram showing a manufacturing process of a conventional semiconductor device.

【図34】従来の半導体装置の製造工程を示す図FIG. 34 is a diagram showing a manufacturing process of a conventional semiconductor device.

【図35】従来の半導体装置の製造工程を示す図FIG. 35 is a view showing a manufacturing process of a conventional semiconductor device.

【図36】従来の半導体装置の製造工程を示す図FIG. 36 is a view showing a manufacturing process of a conventional semiconductor device.

【図37】従来の半導体装置の製造工程を示す図FIG. 37 is a diagram showing a manufacturing process of a conventional semiconductor device.

【符号の説明】[Explanation of symbols]

1 半導体基板 2 ソース電極 3 ゲート電極 4 ドレイン電極 5 半導体素子 6 支持基板 7 エレクトロンワックス 8 フォトレジスト 9 金属膜 10 ダイシングシート 11 パッケージ 12 厚膜メッキ DESCRIPTION OF SYMBOLS 1 Semiconductor substrate 2 Source electrode 3 Gate electrode 4 Drain electrode 5 Semiconductor element 6 Support substrate 7 Electron wax 8 Photoresist 9 Metal film 10 Dicing sheet 11 Package 12 Thick film plating

───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.7 識別記号 FI テーマコート゛(参考) H01L 29/80 U ──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. 7 Identification symbol FI Theme coat ゛ (Reference) H01L 29/80 U

Claims (3)

【特許請求の範囲】[Claims] 【請求項1】 半導体基板上に複数の半導体素子を形成
し、前記半導体素子が形成された前記半導体基板の表面
と、支持基板とが対向するように、前記半導体基板と前
記支持基板とを固着し、前記半導体基板を前記半導体素
子毎に分割し、前記支持基板を伸縮性シートに固着し、
前記支持基板を前記半導体素子毎に分割し、分割された
前記支持基板を前記半導体素子とともに前記伸縮性シー
トから分離し、前記半導体基板をパッケージ上に形成
し、その後前記支持基板を前記半導体基板から分離する
ことを特徴とする半導体装置の製造方法。
1. A semiconductor device comprising: a plurality of semiconductor elements formed on a semiconductor substrate; and a semiconductor substrate and the support substrate fixed to each other such that a surface of the semiconductor substrate on which the semiconductor elements are formed faces a support substrate. Then, the semiconductor substrate is divided for each of the semiconductor elements, the support substrate is fixed to an elastic sheet,
The support substrate is divided for each of the semiconductor elements, the divided support substrate is separated from the stretchable sheet together with the semiconductor elements, the semiconductor substrate is formed on a package, and then the support substrate is separated from the semiconductor substrate. A method for manufacturing a semiconductor device, comprising: separating a semiconductor device;
【請求項2】 前記半導体基板上に金属膜を形成する工
程を有することを特徴とする請求項1記載の半導体装置
の製造方法。
2. The method according to claim 1, further comprising a step of forming a metal film on the semiconductor substrate.
【請求項3】 前記半導体基板にバイアホールを形成す
る工程を有することを特徴とする請求項1または請求項
2に記載の半導体装置の製造方法。
3. The method according to claim 1, further comprising a step of forming a via hole in the semiconductor substrate.
JP17241198A 1998-06-19 1998-06-19 Manufacture of semiconductor device Pending JP2000012490A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP17241198A JP2000012490A (en) 1998-06-19 1998-06-19 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP17241198A JP2000012490A (en) 1998-06-19 1998-06-19 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JP2000012490A true JP2000012490A (en) 2000-01-14

Family

ID=15941469

Family Applications (1)

Application Number Title Priority Date Filing Date
JP17241198A Pending JP2000012490A (en) 1998-06-19 1998-06-19 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JP2000012490A (en)

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