JPH0613203A - Manufacture of semiconductor ceramic element - Google Patents

Manufacture of semiconductor ceramic element

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Publication number
JPH0613203A
JPH0613203A JP19313292A JP19313292A JPH0613203A JP H0613203 A JPH0613203 A JP H0613203A JP 19313292 A JP19313292 A JP 19313292A JP 19313292 A JP19313292 A JP 19313292A JP H0613203 A JPH0613203 A JP H0613203A
Authority
JP
Japan
Prior art keywords
electrode
semiconductor ceramic
barrier
resistance
exceeding
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP19313292A
Other languages
Japanese (ja)
Inventor
Hideaki Niimi
秀明 新見
Yasunobu Yoneda
康信 米田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Murata Manufacturing Co Ltd
Original Assignee
Murata Manufacturing Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Murata Manufacturing Co Ltd filed Critical Murata Manufacturing Co Ltd
Priority to JP19313292A priority Critical patent/JPH0613203A/en
Publication of JPH0613203A publication Critical patent/JPH0613203A/en
Pending legal-status Critical Current

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Abstract

PURPOSE:To abolish the barrier without fail further enabling the resistance to be lowered by impressing a specific pulse between an electrode and a semiconductor ceramic. CONSTITUTION:Both surfaces of semiconductor ceramic manufactured by baking a molded body at 1350 deg.C for two hours in atmosphere are printed in an electrode paste comprising Zn added Ag paste to form an ohmic electrode by baking e.g. at 800 deg.C for two hours. Next, the space between the electrode and the semiconductor ceramic is impressed with a pulse voltage exceeding 100V. When this impressed voltage is lowered down to the level not exceeding 100V, the barrier can not be abolished without fail thereby making it unable to gain the diminishing effect of the resistance value. On the other hand, although the upper limit of this impressed voltage fluctuates depending upon the characteristics of ceramic, it is recommemded that the pulse voltage not to break down the inner grain boundry barrier not exceeding e.g. 100kV as well as the impression time not to cause the breakdown due to thermal strain e.g. not exceeding 0.1sec are to be adopted. Through these procedures, the semiconductor ceramic element capable of abolishing the barrier in the interface between the semiconductor ceramic and the conductive electrode without fail also having the positive resistance temperature characteristics to make the lower resistance feasible can be manufactured.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、正の抵抗温度特性を有
する半導体セラミック素子の製造方法に関し、特に半導
体磁器と導電性電極との界面のバリアを確実に除去で
き、ひいては低抵抗化を可能にできるようにした方法に
関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor ceramic element having a positive resistance temperature characteristic, and in particular, it can surely remove a barrier at an interface between a semiconductor ceramic and a conductive electrode, and eventually a resistance can be reduced. Regarding the method that was made possible.

【0002】[0002]

【従来の技術】一般に電気抵抗値が温度によって変化す
る正の抵抗温度特性を有するBaTiO3 系半導体セラ
ミック素子は、キュリー点以上で抵抗値が急激に変化す
る特性を有しており、例えば電気回路の過電流保護素子
として、あるいはテレビのブラウン管枠の消磁素子とし
て、多くの分野で使用されている。このようなBaTi
3 系半導体セラミック素子では、半導体磁器と電極と
の界面に存在するバリアを除去することにより、室温で
の比抵抗を小さくするようにしている。このバリアを除
去するために、従来、例えばオーミック性電極に採用さ
れるAg等にZnやSn等の還元性金属を添加する方法
が提案されている。
2. Description of the Related Art Generally, a BaTiO 3 type semiconductor ceramic element having a positive resistance temperature characteristic in which an electric resistance value changes with temperature has a characteristic in which the resistance value rapidly changes at a Curie point or higher. It is used in many fields as an overcurrent protection device for the above, or as a degaussing device for a CRT frame of a television. Such BaTi
In the O 3 -based semiconductor ceramic element, the barrier existing at the interface between the semiconductor ceramic and the electrode is removed to reduce the specific resistance at room temperature. In order to remove this barrier, conventionally, for example, a method of adding a reducing metal such as Zn or Sn to Ag or the like employed in an ohmic electrode has been proposed.

【0003】[0003]

【発明が解決しようとする課題】しかしながら、上記電
極に還元性金属を添加してバリアを除去する従来の半導
体セラミック素子の製造方法では、バリア除去のための
熱処理条件が極めて難しいことからバリアが残存し易
く、その結果抵抗値を低くすることが困難であるという
問題がある。
However, in the conventional method for manufacturing a semiconductor ceramic element in which a reducing metal is added to the above electrode to remove the barrier, the heat treatment condition for removing the barrier is extremely difficult, and the barrier remains. Therefore, there is a problem that it is difficult to reduce the resistance value as a result.

【0004】本発明は上記従来の状況に鑑みてなされた
もので、簡単な方法でバリアを確実に除去でき、ひいて
は低抵抗化を可能にできる半導体セラミック素子を提供
することを目的としている。
The present invention has been made in view of the above conventional circumstances, and an object of the present invention is to provide a semiconductor ceramic element which can surely remove the barrier by a simple method and can lower the resistance.

【0005】[0005]

【課題を解決するための手段】そこで本発明は、半導体
磁器に導電性電極を形成してなる正の抵抗温度特性を有
する半導体セラミック素子の製造方法において、上記電
極と半導体磁器との間に100V以上のパルス電圧を印加す
ることを特徴としている。
Therefore, the present invention provides a method for manufacturing a semiconductor ceramic element having positive resistance temperature characteristics, which is obtained by forming a conductive electrode on a semiconductor porcelain, and provides 100 V between the electrode and the semiconductor porcelain. The feature is that the above pulse voltage is applied.

【0006】ここで、上記印加電圧を100V以上としたの
は、これより電圧を低くするとバリアを確実に除去でき
ず、抵抗値の低減効果が得られないからである。また、
上記印加電圧の上限については、セラミックの特性に依
存して変化することから一概に決められないが、例えば
100KV を越えるパルス電圧を印加した場合、セラミック
内部の粒界障壁まで破壊されるおそれがあることから、
これ以上は好ましくない。さらに、電圧の印加時間の長
さについては特に限定されるものではないが、0.1 秒よ
り長くするとセラミックが発熱し易く、その結果熱歪に
よって破壊される場合があることから、これ以下にする
のが好ましい。
Here, the applied voltage is set to 100 V or more because if the voltage is set lower than this, the barrier cannot be removed reliably and the effect of reducing the resistance cannot be obtained. Also,
The upper limit of the applied voltage cannot be unconditionally determined because it changes depending on the characteristics of the ceramic.
If a pulse voltage exceeding 100 KV is applied, the grain boundary barrier inside the ceramic may be destroyed.
No more is preferred. Further, the length of the voltage application time is not particularly limited, but if it is longer than 0.1 seconds, the ceramic is likely to generate heat, and as a result, it may be destroyed by thermal strain. Is preferred.

【0007】[0007]

【作用】本発明に係る半導体セラミック素子の製造方法
によれば、電極と半導体磁器との間に100V以上のパルス
電圧を印加したので、これにより半導体磁器と電極との
界面に形成されるバリアを簡単な方法で、かつ確実に除
去できることから、抵抗値を大幅に低減でき、品質に対
する信頼性を向上できる。
According to the method for manufacturing a semiconductor ceramic element of the present invention, a pulse voltage of 100 V or more is applied between the electrode and the semiconductor porcelain, so that the barrier formed at the interface between the semiconductor porcelain and the electrode is thereby prevented. Since it can be removed reliably by a simple method, the resistance value can be greatly reduced and the reliability of quality can be improved.

【0008】[0008]

【実施例】以下、本発明の実施例を説明する。本実施例
では、本発明の半導体セラミック素子を製造し、これに
より得られた素子の効果を確認するために行った試験に
ついて説明する。まず、本実施例の半導体セラミック素
子の一製造方法について説明する。原料として、BaC
3 ,CaCO3 ,TiO2 ,Y2 3 ,SiO2 ,M
nCO3 を用い、これらが以下の組成となるように調合
する。 (Ba0.876 Ca0.120.004 )TiO3 +0.0008Mn
+0.01SiO2 上記原料を、純水及びジルコニアボールとともにポリエ
チレン製ポットに入れて5時間粉砕混合した後、乾燥さ
せて1100℃で2時間仮焼成する。
EXAMPLES Examples of the present invention will be described below. In this example, a test conducted to manufacture the semiconductor ceramic device of the present invention and confirm the effect of the device thus obtained will be described. First, a method for manufacturing the semiconductor ceramic device of this embodiment will be described. As a raw material, BaC
O 3 , CaCO 3 , TiO 2 , Y 2 O 3 , SiO 2 , M
Using nCO 3 , these are formulated to have the following composition. (Ba 0.876 Ca 0.12 Y 0.004 ) TiO 3 +0.0008 Mn
+ 0.01SiO 2 The above raw materials are put in a polyethylene pot together with pure water and zirconia balls, pulverized and mixed for 5 hours, dried, and calcinated at 1100 ° C. for 2 hours.

【0009】次いで、この仮焼成体を粉砕して仮焼成粉
を形成し、この仮焼成粉に有機バインダを混合してスラ
リーを形成する。このスラリーをプレスで加圧し、これ
により直径10mmφ×厚さ0.6mmtの成形体を形成する。
Next, the calcined body is crushed to form a calcined powder, and the calcined powder is mixed with an organic binder to form a slurry. This slurry is pressed by a press to form a compact having a diameter of 10 mmφ and a thickness of 0.6 mmt.

【0010】上記成形体を、大気中にて1350℃で2時間
焼成し、半導体磁器を得る。そして、この半導体磁器の
両面に、AgペーストにZnを添加してなる電極ペース
トを印刷し、これを800 ℃で2時間焼き付けてオーミッ
ク性電極を形成する。これにより本実施例の半導体セラ
ミック素子が製造される。
The above-mentioned molded body is fired in the atmosphere at 1350 ° C. for 2 hours to obtain a semiconductor porcelain. Then, an electrode paste obtained by adding Zn to Ag paste is printed on both sides of this semiconductor porcelain and baked at 800 ° C. for 2 hours to form ohmic electrodes. As a result, the semiconductor ceramic device of this example is manufactured.

【0011】[0011]

【表1】 [Table 1]

【0012】次に、上記方法により得られた半導体セラ
ミック素子の試験について説明する。この試験は、表1
に示すように、上記電極ペーストのZn添加量を0〜5
mol%の範囲で変化させて各試料を作成した。そして各
試料に10KVのパルス電圧を印加し、このパルス印加前と
印加後の室温での抵抗値(比抵抗)と抵抗温度係数とを
測定した。この抵抗温度係数は、次式により算出した。 抵抗温度係数=(2.303/T2−T1)×100 T1:抵抗が室温抵抗の10倍になる温度 T2:抵抗が室温抵抗の100 倍になる温度 また、比較するために、バリアを形成しないIn−Ga
合金を電極として採用し、これについても同様の測定を
行った。
Next, the test of the semiconductor ceramic device obtained by the above method will be described. This test is shown in Table 1.
As shown in FIG.
Each sample was prepared by changing it in the range of mol%. A pulse voltage of 10 KV was applied to each sample, and the resistance value (specific resistance) and the temperature coefficient of resistance at room temperature before and after the application of the pulse were measured. The temperature coefficient of resistance was calculated by the following equation. Temperature coefficient of resistance = (2.303 / T2-T1) x 100 T1: Temperature at which resistance becomes 10 times room temperature resistance T2: Temperature at which resistance becomes 100 times room temperature resistance In addition, for comparison, In- Ga
An alloy was adopted as the electrode, and the same measurement was performed for this.

【0013】表1からも明らかなように、Znの添加量
を増やすほど抵抗値(比抵抗、以下同じ)は50〜17Ω・
cmと低くなるものの、In−Ga電極の抵抗値までは下
がらない。これに対して、パルス電圧を印加するといず
れの試料もZnの添加量に係わらず抵抗値が15Ω・cmと
大幅に低下しており、In−Ga電極と同等の値が得ら
れている。このことからバリアが確実に除去されている
ことがわかる。しかも抵抗温度係数では、パルス印加後
においても印加前と同等の値が得られている。
As is apparent from Table 1, the resistance value (specific resistance, the same applies hereinafter) is 50 to 17 Ω as the amount of Zn added increases.
Although it is as low as cm, it does not fall to the resistance value of the In-Ga electrode. On the other hand, when a pulse voltage is applied, the resistance value of all the samples is significantly reduced to 15 Ω · cm regardless of the amount of Zn added, and a value equivalent to that of the In-Ga electrode is obtained. From this, it can be seen that the barrier is surely removed. In addition, the temperature coefficient of resistance is equal to that before the pulse application even after the pulse application.

【0014】[0014]

【表2】 [Table 2]

【0015】この試験は、表2に示すように、Znの添
加量を0とした試料を作成し、各試料に印加するパルス
電圧を0〜100KV の範囲で変化させた場合の、室温抵抗
値と抵抗温度係数を測定した。
In this test, as shown in Table 2, room temperature resistance values were prepared when samples were prepared in which the amount of Zn added was 0 and the pulse voltage applied to each sample was changed in the range of 0 to 100 KV. And the temperature coefficient of resistance was measured.

【0016】表2からも明らかなように、パルス電圧が
100V以下の各試料では、抵抗値が30Ω・cmとバリアが完
全に除去されていない。これに対して、印加電圧が100V
以上の各試料では、いずれも抵抗値は19〜15Ω・cmと低
減しており、顕著な抵抗低減効果が得られていることが
わかる。
As is clear from Table 2, the pulse voltage is
In each sample of 100V or less, the resistance value is 30Ω · cm and the barrier is not completely removed. In contrast, the applied voltage is 100V
In each of the above samples, the resistance value was reduced to 19 to 15 Ω · cm, and it is clear that a remarkable resistance reduction effect was obtained.

【0017】なお、上記実施例では、電極にAgを採用
した場合を例にとって説明したが、本発明によれば、電
極としてPt,Pd,Cuを用いた場合も同様の効果が
得られる。
In the above embodiment, the case where Ag is used for the electrode has been described as an example, but according to the present invention, the same effect can be obtained when Pt, Pd, Cu is used as the electrode.

【0018】[0018]

【発明の効果】以上のように本発明に係る半導体セラミ
ック素子の製造方法によれば、電極と半導体磁器との間
に100V以上のパルス電圧を印加したので、バリアを確実
に除去でき、抵抗値を大幅に小さくできる効果がある。
As described above, according to the method for manufacturing a semiconductor ceramic element of the present invention, since a pulse voltage of 100 V or more is applied between the electrode and the semiconductor porcelain, the barrier can be reliably removed and the resistance value can be increased. There is an effect that can be significantly reduced.

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】 半導体磁器に導電性電極を形成してなる
正の抵抗温度特性を有する半導体セラミック素子の製造
方法において、上記電極と半導体磁器との間に100V以上
のパルス電圧を印加することを特徴とする半導体セラミ
ック素子の製造方法。
1. A method of manufacturing a semiconductor ceramic element having positive resistance temperature characteristics, which comprises forming a conductive electrode on a semiconductor porcelain, wherein a pulse voltage of 100 V or more is applied between the electrode and the semiconductor porcelain. A method for manufacturing a semiconductor ceramic device characterized by the above.
【請求項2】 請求項1において、上記電極が、Pt,
Ag,Pd,Cuのうちいずれかを主成分としているこ
とを特徴とする半導体セラミック素子の製造方法。
2. The electrode according to claim 1, wherein the electrode is Pt,
A method of manufacturing a semiconductor ceramic element, characterized in that any one of Ag, Pd, and Cu is contained as a main component.
JP19313292A 1992-06-25 1992-06-25 Manufacture of semiconductor ceramic element Pending JPH0613203A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP19313292A JPH0613203A (en) 1992-06-25 1992-06-25 Manufacture of semiconductor ceramic element

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP19313292A JPH0613203A (en) 1992-06-25 1992-06-25 Manufacture of semiconductor ceramic element

Publications (1)

Publication Number Publication Date
JPH0613203A true JPH0613203A (en) 1994-01-21

Family

ID=16302809

Family Applications (1)

Application Number Title Priority Date Filing Date
JP19313292A Pending JPH0613203A (en) 1992-06-25 1992-06-25 Manufacture of semiconductor ceramic element

Country Status (1)

Country Link
JP (1) JPH0613203A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1994024680A1 (en) * 1993-04-14 1994-10-27 Kabushiki Kaisha Komatsu Seisakusho Positive characteristic thermistor
JP2004342658A (en) * 2003-05-13 2004-12-02 Nichicon Corp Method for manufacturing positive temperature coefficient thermistor element

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1994024680A1 (en) * 1993-04-14 1994-10-27 Kabushiki Kaisha Komatsu Seisakusho Positive characteristic thermistor
JP2004342658A (en) * 2003-05-13 2004-12-02 Nichicon Corp Method for manufacturing positive temperature coefficient thermistor element
JP4554893B2 (en) * 2003-05-13 2010-09-29 ニチコン株式会社 Method for manufacturing positive temperature coefficient thermistor element

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