JPH06112347A - Package for accommodating semiconductor element - Google Patents

Abstract

PURPOSE:To radiate outside efficiently heat generated from a semiconductor element accommodated inside and, moreover, to prevent cracking of a part of an insulating base or a sealing layer constituting a package. CONSTITUTION:This package has an insulating base 2 which is constituted of ceramic of aluminum nitride material and accommodates a semiconductor element 5 inside, a cover body 3 which is so provided on the insulating base 2 as to cover the semiconductor element 5, and a sealing layer 9 which joins the insulating base 2 and the cover body 3 made of metal together. In a temperature range from normal temperatures or above to a sealing temperature of the sealing layer 9 or below, the thermal expansion coefficient of the cover body 3 made of metal is smaller than the thermal expansion coefficient of the insulating base 2.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor element housing package, and more particularly to a semiconductor element housing package in which an insulating substrate for housing a semiconductor element is made of aluminum nitride ceramics.

[0002]

2. Description of the Related Art Generally, a package for housing a semiconductor element is
It has an insulating base made of alumina ceramics or the like. A recess for accommodating a semiconductor element is formed in a substantially central portion of the upper surface of the insulating base. Further, a metallic lid is joined to the upper surface of the insulating base by a sealing layer made of gold-tin eutectic solder so as to cover the semiconductor element housed in the recess.

By the way, recently, the degree of integration of semiconductor elements has increased,
The densification is rapidly progressing, and as a result, the amount of heat generated when a semiconductor element is operated is becoming large.
However, since the insulating substrate that constitutes the conventional semiconductor device housing package is made of alumina ceramics, its thermal conductivity is as low as 20 W / m · K. Therefore, the heat generated by the semiconductor element cannot be efficiently dissipated to the outside, and the semiconductor element may reach a high temperature to cause malfunction or thermal destruction.

For this reason, it has been proposed that the insulating base of the package for housing the semiconductor element be made of aluminum nitride ceramics. In this case, the thermal conductivity is about 8
Since it is 0 W / m · K, which is higher than that of alumina ceramics, the heat generated by the semiconductor element can be efficiently dissipated to the outside.

[0005]

The coefficient of thermal expansion of the aluminum nitride ceramics used as the insulating substrate is 3.8 to 4.3 × 10 ⁻⁶ / ° C. (20 to 350 ° C.), and the metallic lid is used. The thermal expansion coefficient of Kovar that composes the body is 4.
It is ^{6 to} 5.0 × 10 ⁻⁶ / ° C. (20 to 350 ° C.). The gold-tin alloy forming the sealing layer is 17.5 × 10 ⁻⁶ /
℃. As described above, the thermal expansion coefficients of the sealing layer and the insulating substrate are very different from each other. For this reason, when an insulating substrate is made of aluminum nitride ceramics and the lid is made of metal and is joined by a sealing layer made of solder of a gold-tin alloy, heat at the time of joining and when the semiconductor element operates When heat is applied, a large stress is generated due to the difference in thermal expansion coefficient between the insulating substrate and the sealing layer. When such a stress is generated, cracks may occur on the insulating substrate side and the sealing layer side because the lid side has high strength. In this case, there is a problem that the semiconductor element cannot be hermetically sealed.

An object of the present invention is to efficiently dissipate heat generated by a semiconductor element and prevent cracks from occurring in an insulating substrate or the like.

[0007]

A package for accommodating a semiconductor element according to the present invention comprises an insulating base made of aluminum nitride ceramics for accommodating a semiconductor element therein, and an insulating base covering the semiconductor element. It is provided with a metallic lid and a sealing layer for joining the insulating base and the metallic lid. In the temperature range from room temperature to the sealing temperature of the sealing layer, the coefficient of thermal expansion of the metallic lid is smaller than that of the insulating substrate.

[0008]

In the package for housing a semiconductor element according to the present invention, the coefficient of thermal expansion of the metallic lid is smaller than the coefficient of thermal expansion of the insulating substrate in the temperature range from room temperature to the sealing temperature of the sealing layer. Here, as described above, when the insulating base made of aluminum nitride ceramics and the metallic lid are joined, the insulating base and the sealing layer are cracked.
In particular, the thermal expansion coefficient of the sealing layer (mainly made of metal) is largely different from that of the insulating substrate. In this case, by making the thermal expansion coefficient of the metallic lid smaller than that of the insulating base, the thermal stress generated in the sealing layer is absorbed and relaxed by the metallic lid, and the insulating base and the sealing layer are cracked. Is less likely to occur.

[0009]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows a semiconductor device housing package according to an embodiment of the present invention. The package 1 mainly includes an insulating base 2, a lid 3, and a plurality of external lead terminals 4.
And have. The insulating substrate 2 is made of aluminum nitride ceramics and has a coefficient of thermal expansion of 3.8 to 4.3.
× 10 ⁻⁶ / ° C. (20 to 350 ° C.). A recess 2a for accommodating the semiconductor element 5 is formed substantially in the center of the upper surface of the insulating base 2. The semiconductor element 5 is fixed to the bottom surface of the recess 2a with an adhesive such as glass, resin, or solder.

The insulating substrate 2 is formed as follows. First, for example, aluminum nitride, yttria,
A ceramic green sheet is obtained by adding a suitable binder and a solvent to powder such as calcia and mixing them to form a slurry, which is then subjected to a conventionally known doctor blade method. Next, the ceramic green sheet is subjected to an appropriate punching process to laminate a plurality of sheets. Then, it is fired at a temperature of about 1800 ° C.

A plurality of metallized wiring layers 6 are formed from the periphery of the recess 2a of the insulating base 2 to the outer peripheral portion. The electrode of the semiconductor element 5 is electrically connected to the peripheral portion of the recess 2 a of the metallized wiring layer 6 via the bonding wire 7. The external lead terminals 4 are connected to the outer peripheral portion of the metallized wiring layer 6 via a brazing material such as silver brazing.

The external lead terminal 4 is made of an iron alloy type metal material such as 42 alloy or Kovar, for example, iron 51.0 to 64.0% by weight, nickel 29.0.
It is formed of an alloy of 34.0% by weight and cobalt 7.0 to 15.0% by weight. In this case, the external lead terminal 4
Has a thermal expansion coefficient of 4.0 to 6.0 × 10 ⁻⁶ / ° C. (20 to
400 ° C.). Therefore, the thermal stress generated due to the difference in the coefficient of thermal expansion from the insulating base 2 can be reduced, and the external lead terminal 4 can be firmly connected to the metallized wiring layer 6.

A metallized layer 8 is formed on the upper surface of the insulating substrate 2, and a metallic lid 3 is fixed to the upper portion of the metallized layer 8 with a sealing layer 9 interposed therebetween. The sealing layer 9 is gold-
It is made of tin alloy and its coefficient of thermal expansion is 1
It is 7.5 × 10 ⁻⁶ / ° C. Further, the metallic lid 3 is made of, for example, iron 53 to 64% by weight, nickel 29 to 34% by weight,
It is made of an alloy containing 5 to 13% by weight of cobalt and has a thermal expansion coefficient of 3.0 to 3.8 × 10 ⁻⁶ / ° C. (20 to 350 ° C.). That is, the thermal expansion coefficient of the insulating base 2 is 3.8 to 4.
It is smaller than 3 × 10 ⁻⁶ / ° C. (20 to 350 ° C.).

In this embodiment, the coefficient of thermal expansion of the metallic lid 3 is smaller than that of the insulating base 2 in the range of room temperature to the sealing temperature of gold-tin alloy (20 to 350 ° C.). Therefore, a tensile stress is generated in the sealing layer 9 due to the difference in the coefficient of thermal expansion during operation of the semiconductor element, etc.
A compressive stress in the opposite direction is generated on the side, and the stress generated in the sealing layer 9 is absorbed and relaxed. Therefore, it is possible to suppress the occurrence of cracks on the sealing layer 9 or the insulator 2 side.

Further, since the insulating base 2 is made of aluminum nitride ceramics having a good thermal conductivity, the heat generated from the semiconductor element 5 can be efficiently dissipated to the outside, and malfunction of the semiconductor element 5 or Less heat destruction. When the thermal expansion coefficient of the metallic lid 3 exceeds the thermal expansion coefficient of the insulating substrate 2 (3.8 × 10 ⁻⁶ / ° C. (20 to 350 ° C.)), or the thermal expansion coefficient of the lid 3 is 3 or more. 0.0 x 10
Below ⁻⁶ / ° C. (20 to 350 ° C.), not only the tensile stress of the gold-tin alloy forming the sealing layer 9 but also the stress of the lid 3 is applied to the insulating substrate 2, and the sealing layer 9 is cracked. Easy to enter. Therefore, the thermal expansion coefficient of the lid 3 is 3.0 to 3.
The range of 8 × 10 ⁻⁶ / ° C. (20 to 350 ° C.) is preferable.

[0016]

As described above, according to the present invention, the coefficient of thermal expansion of the metallic lid is smaller than that of the insulating base. Therefore, even if thermal stress is generated in the sealing layer, the thermal stress is increased by the compressive stress of the lid. It is possible to suppress stress from being absorbed and relaxed and to prevent cracks from being generated in the sealing layer and the insulating substrate.

[Brief description of drawings]

FIG. 1 is a vertical cross-sectional configuration diagram of a package for housing a semiconductor device according to an embodiment of the present invention.

[Explanation of symbols]

 1 Package for Semiconductor Element Storage 2 Insulating Base 3 Metal Lid 5 Semiconductor Element 9 Encapsulation Layer

Claims (1)

[Claims] 1. An insulating base made of aluminum nitride ceramics for housing a semiconductor element therein, a metal lid provided on the insulating base so as to cover the semiconductor element, the insulating base and a metal lid. A sealing layer for joining a body, wherein the thermal expansion coefficient of the metal lid is smaller than the thermal expansion coefficient of the insulating substrate in a range of room temperature or higher and a sealing temperature of the sealing layer or lower. Package for semiconductor device storage.