JPH0595053A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To enable the voltage application from the rear side of a semiconductor chip, in a semiconductor integrated circuit device where the semiconductor chip mounted on a package substrate through a CCB bump is sealed with a cap. CONSTITUTION:A cap 11 is joined by sealing solder 12a to the main face of a package board 2 where a semiconductor chip 7 is mounted through a CCB bump 6 so as to seal the semiconductor chip 7. And in a chip carrier 11 where the bottom of the cap 11 and rear of the semiconductor chip 7 are joined with a heat conductive solder 12b, the sealing solder 12a and the heat conductive solder 12b are connected electrically through metallized layers 13a, 13d, and 13c, and the sealing solder 12a and the electrode 3b made on the rear of the package board 2 are connected electrically through the inner layer wiring 4a made in the package board 2.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device technique, and more particularly to a technique effectively applied to a semiconductor integrated circuit device using a flip chip method.

[0002]

2. Description of the Related Art As an example of a semiconductor integrated circuit device using a flip chip method, a CCB (Cont.
There is a chip carrier in which a semiconductor chip mounted via bumps is hermetically sealed with a cap.

The chip carrier is described, for example, in Japanese Patent Application Laid-Open Nos. 62-249429, 63-310139 and Japanese Patent Application No. 3-49808.

FIG. 8 shows a cross section of the chip carrier 20 described in the above-mentioned JP-A-62-2449429 and JP-A-63-310139.

The package substrate 21 is made of mullite or the like, and has electrodes 22a and 2 on its main surface and back surface, respectively.
2b is formed.

A semiconductor chip 24 is electrically connected to the electrodes 22a on the main surface of the package substrate 21 via CCB bumps 23.

The semiconductor chip 24 is made of silicon (Si) single crystal and hermetically sealed by a cap 25. The cap 25 is made of aluminum nitride (AlN) or the like, and is joined to the main surface of the package substrate 21 by the sealing solder 26.

A metallization layer 27a for improving the wettability of the sealing solder 26 is formed on the lower surface of the leg portion of the cap 25 and the peripheral portion of the main surface of the package substrate 21.

Further, the lower surface of the cap 25 and the back surface of the semiconductor chip 24 are joined by heat transfer solder 28, and the heat generated in the semiconductor chip 24 during circuit operation causes the heat transfer solder 28 and the cap 25 to pass. The structure is such that it is diffused to the outside through.

The cap 2 to which the semiconductor chip 24 is joined
A metallized layer 27 b is formed on the lower surface of the No. 5 to improve the wettability of the heat transfer solder 28.

Although not shown, the above-mentioned Japanese Patent Application No. 3-4.
No. 9808 describes a chip carrier having a structure in which the metallized layer on the lower surface of the leg portion of the cap and the metallized layer on the lower surface of the cap to which the semiconductor chip is joined are partially continuously connected. ..

In this case, when the solder preform sandwiched between the lower surface of the cap and the back surface of the semiconductor chip is heated and melted in the semiconductor chip encapsulation process, a part of the molten solder travels on the surface of the metallized layer. It quickly flows between the lower surface of the leg portion of the cap and the peripheral portion of the main surface of the package substrate.

As a result, the assembly time of the chip carrier can be shortened, the load applied to the cap during the semiconductor chip sealing step can be reduced, and the CCB bumps between the semiconductor chip and the package substrate can be prevented from being crushed. It is possible to improve the assembly yield of chip carriers.

[0014]

However, the present inventor has found that the above-mentioned conventional technique has the following problems.

As one of the semiconductor integrated circuit device technologies, there is a semiconductor chip having an SOI (Silicon On Insulator) structure, for example.

The semiconductor chip having the SOI structure is a semiconductor chip having a structure in which a thin semiconductor layer is formed on an insulating layer formed on a semiconductor substrate and a predetermined semiconductor integrated circuit element is formed on the semiconductor layer.

When such a semiconductor chip having an SOI structure is used as a chip carrier, the semiconductor layer on the main surface side of the semiconductor chip faces the main surface side of the package substrate, and the semiconductor substrate on the back surface side of the semiconductor chip transfers heat. The structure is such that it is bonded to the lower surface of the cap with solder for use.

When a semiconductor chip having an SOI structure is used as a chip carrier, the semiconductor layer on the main surface side of the semiconductor chip and the semiconductor substrate on the back surface side of the semiconductor chip are insulated from each other by the insulating layer. The semiconductor substrate on the back surface side of is in a floating state.

However, when the semiconductor substrate forming the semiconductor chip having the SOI structure is in a floating state, the following various problems occur.

For example, when a semiconductor integrated circuit formed on a semiconductor layer is driven, an induced current flows through a semiconductor substrate by being induced by a current flowing through a wiring forming the semiconductor integrated circuit. Since this induced current flows in the opposite direction to the current flowing through the wiring, there arises a problem that the operation speed of the semiconductor integrated circuit is delayed.

Further, for example, a high-frequency voltage generated by the potential fluctuation of the semiconductor substrate, that is, noise propagates to the semiconductor layer through the insulating layer, which causes a problem of hindering the operation of the semiconductor integrated circuit formed on the semiconductor layer. ..

Further, for example, an n-channel MOS is formed in the semiconductor layer.
When the potential of the semiconductor substrate is set to be positive when the FET is formed, the electrons in the semiconductor layer are attracted to the semiconductor substrate side, and as a result, the threshold voltage of the n-channel MOS FET is changed. There arises a problem that the electrical characteristics of the semiconductor integrated circuit element formed on the semiconductor layer vary depending on the potential of the semiconductor substrate.

Therefore, in order to avoid the above problem, SO
When the semiconductor chip having the I structure is used as a chip carrier, it is necessary to apply a predetermined voltage to the semiconductor substrate forming the semiconductor chip to stabilize the potential of the semiconductor substrate.

By the way, in the conventional chip carrier, no consideration is given to the application of a predetermined voltage from the back surface side of the semiconductor chip. Therefore, when a predetermined voltage is applied to the semiconductor substrate forming the SOI structure semiconductor chip. Has a structure in which a power supply electrode connected to the semiconductor substrate is provided on the main surface side of the semiconductor chip and a predetermined voltage is applied to the semiconductor substrate from there.

In that case, however, a step for forming the power supply electrode, for example, a hole reaching the semiconductor substrate is punched in the semiconductor layer and the insulating layer, or an insulating film is formed on the side wall of the hole by an etch back method or the like. Since a step of forming or burying low-resistance polysilicon in the hole is required, the number of manufacturing steps of the semiconductor chip increases, the manufacturing becomes complicated, and it becomes difficult to secure the yield of the semiconductor chip. Occurs.

The present invention has been made in view of the above problems, and an object thereof is to provide a semiconductor chip in a semiconductor integrated circuit device in which a semiconductor chip mounted on a package substrate via CCB bumps is sealed with a cap. It is to provide a technique capable of applying a predetermined voltage from the back surface side of the.

Another object of the present invention is to manufacture an SOI structure semiconductor chip in a semiconductor integrated circuit device in which an SOI structure semiconductor chip mounted on a package substrate via CCB bumps is sealed with a cap. It is an object of the present invention to provide a technique capable of stabilizing the potential of a semiconductor substrate that constitutes an SOI structure semiconductor chip without complicating it.

The above and other objects and novel features of the present invention will be apparent from the description of the specification and the accompanying drawings.

[0029]

Among the inventions disclosed in the present application, a brief description will be given to the outline of typical ones.
It is as follows.

That is, the invention according to claim 1 is CCB
The cap is joined to the main surface of the package substrate on which the semiconductor chip is mounted via the bump by the solder for sealing to seal the semiconductor chip, and the lower surface of the cap and the back surface of the semiconductor chip are heat transfer solder. A semiconductor integrated circuit device bonded by means of electrically connecting the sealing solder and the heat transfer solder, and packaging the sealing solder and an electrode formed on the back surface of the package substrate. The semiconductor integrated circuit device structure is electrically connected through inner layer wiring formed on the substrate.

[0031]

According to the invention described in claim 1, a predetermined voltage is applied to the back surface of the semiconductor chip from the electrodes on the back surface of the package board through the inner layer wiring inside the package board, the sealing solder and the heat transfer solder. It becomes possible to do. That is, it becomes possible to apply a predetermined voltage from the back surface side of the semiconductor chip.

Therefore, even when the semiconductor chip having the SOI structure is used, it is not necessary to provide the power supply electrode for applying a predetermined voltage to the semiconductor substrate of the semiconductor chip on the main surface side of the semiconductor chip. That is, it is possible to reduce the process for forming the power supply electrode.

Further, the potential of the semiconductor substrate forming the semiconductor chip having the SOI structure can be stabilized,
It is possible to stabilize the operation of the semiconductor integrated circuit formed on the semiconductor chip.

[0034]

FIG. 1 is a sectional view of a semiconductor integrated circuit device according to an embodiment of the present invention, and FIG. 2 is a main part of the semiconductor integrated circuit device for explaining a modified example of a joint portion between a semiconductor chip and a package substrate. Sectional view, FIG. 3 is an overall plan view of the lower surface of the cap,
4 is a sectional view of the semiconductor integrated circuit device of FIG. 1 mounted on a module substrate, and FIGS. 5 to 7 are sectional views of the semiconductor integrated circuit device of FIG. 1 during an assembling process.

The semiconductor integrated circuit device of the first embodiment is a chip carrier 1 as shown in FIG. 1, for example.

The package substrate 2 constituting the chip carrier 1 is made of a ceramic material such as mullite, and has electrodes 3a and 3 on its main surface and back surface, respectively.
b is formed.

The electrodes 3a and 3b are electrically connected by the inner layer wiring 4 formed inside the package substrate 2. The inner layer wiring 4 is made of a refractory metal such as tungsten (W).

The electrodes 3b on the back surface of the package substrate 2 are
The CCB bump 5 is joined.

The CCB bump 5 is made of, for example, a tin (Sn) / Ag alloy (melting point: about 221 to 222 ° C.) containing about 3.0% by weight of silver (Ag).

The electrode 3a on the main surface of the package substrate 2
A CCB bump 6 having a diameter smaller than that of the CCB bump 5 on the back surface side of the package substrate 2 is bonded to the. The CCB bump 6 contains lead (P) containing, for example, about 2% by weight of Sn.
b) / Sn alloy (melting point: about 320 to 327 ° C.).

The CCB bumps 6 are joined to a BLM (Ball Limiting Metalization) pattern 8 formed on the main surface of the semiconductor chip 7. That is, the semiconductor chip 7
Are mounted on the main surface of the package substrate 2 via the CCB bumps 6.

Although not shown, the BLM pattern 8 is, for example, a chromium (Cr) layer, a copper (Cu) layer and a gold (Au) layer.
The layers are sequentially stacked from the main surface side of the semiconductor chip 7.

The semiconductor chip 7 has, for example, an SOI structure. That is, the semiconductor chip 7 includes the semiconductor substrate 7a on the back surface side and the semiconductor substrate 7a (the lower surface in FIG. 1).
And the semiconductor layer 7c formed on the insulating layer 7b (the lower surface in FIG. 1).

The semiconductor substrate 7a and the semiconductor layer 7c are made of, for example, Si single crystal, and the insulating layer 7b is made of, for example, silicon dioxide (SiO ₂ ).

On the semiconductor layer 7c, for example, BiC-MO is used.
A semiconductor integrated circuit that operates at high speed such as an S (Bipolar C-MOS) circuit is formed.

If necessary, the semiconductor chip 7 and the package substrate 2 may be electrically connected as shown in FIG.

That is, a thin film wiring board 9 made of, for example, a polyimide resin is interposed between the main surface of the semiconductor chip 7 and the main surface of the package substrate 2, and the inner layer wiring 10 formed inside the thin film wiring board 9 serves as a semiconductor chip. 7 and the package substrate 2 may be electrically connected. The inner layer wiring 10 is made of, for example, aluminum (Al) or Cu, and is patterned by, for example, a photolithography technique.

On the other hand, the semiconductor chip 7 is hermetically sealed by the cap 11. The cap 11 is, for example, A
It is made of a ceramic having a high thermal conductivity such as 1N, and is joined to the main surface of the package substrate 2 by the sealing solder 12a. The sealing solder 12a is, for example, a Pb / Sn alloy (melting point: 290 to 30 containing about 10 wt% Sn).
0 ° C).

Metallized layers (first metallized layers) 13a and 13b are formed on the lower surface of the leg portion of the cap 11 and the peripheral portion of the main surface of the package substrate 2 in order to improve the wettability of the sealing solder 12a. Has been done.

Metallized layer 1 on the lower surface of the leg of the cap 11
3a is, for example, titanium (Ti) / nickel (Ni) / A
It is composed of a laminated metal film of u. Further, the metallized layer 13b at the peripheral portion of the main surface of the package substrate 2 is composed of, for example, a W / Ni / Au laminated metal film.

The back surface of the semiconductor chip 7 is joined to the bottom surface of the cap 9 by the heat transfer solder 12b.
As a result, the heat generated in the semiconductor chip 7 during circuit operation is dissipated from the surface of the cap 11 via the heat transfer solder 12b. The heat transfer solder 12b is, for example, the sealing solder 12a.
It is composed of the same Pb / Sn alloy.

On the lower surface of the cap 11 to which the back surface of the semiconductor chip 7 is joined, a metallization layer (second metallization layer) 1 is formed in order to improve the wettability of the heat transfer solder 12b.
3c is formed. The metallized layer 13c is formed of, for example, a Ti / Ni / Au laminated metal film.

The metallized layer 13a on the lower surface of the leg portion of the cap 11 and the metallized layer 13c on the lower surface of the cap 11 to which the semiconductor chip 7 is bonded are as shown in FIGS.
As shown in, the connection is made via the metallized layer 13d provided on the lower surface and the inner wall surface of the cap 11, for example.

That is, the metallized layer 13a and the metallized layer 13c are continuous through the metallized layer 13d, whereby the sealing solder 12a and the heat transfer solder 12 are formed.
b is electrically connected.

The metallized layers 13a, 13c and 13d are
For example, patterns are formed from the same laminated metal film formed in the same process. Therefore, the metallization layer 13
The manufacturing of the cap 11 is not complicated because the a, 13c, and 13d are formed.

In this embodiment, the metallized layer 13d is formed at the center position of each side of the cap 11, as shown in FIG.

By the way, in this embodiment, the metallization layer 13b formed on the peripheral portion of the main surface of the package substrate 2 is used.
However, it is electrically connected to the electrode 3b on the back surface of the package substrate 2 through the inner layer wiring 4a inside the package substrate 2.

That is, in the chip carrier 1 of this embodiment, from the electrode 3b on the back surface of the package substrate 2 to the inner layer wiring 4a, the metallization layer 13b, the sealing solder 12a, the metallization layers 13a, 13d, 13c and the heat transfer solder. 1
The semiconductor substrate 7a on the back side of the semiconductor chip 7 through 2b
It is possible to apply a predetermined voltage to.

By applying a predetermined voltage to the semiconductor substrate 7a from the back surface of the semiconductor chip 7, the potential of the semiconductor substrate 7a can be stabilized.

This makes it possible to suppress the phenomenon in which an induced current is generated in the semiconductor substrate 7a when the semiconductor integrated circuit formed on the semiconductor layer 7c is driven, for example.

Further, it is possible to suppress the phenomenon that noise generated in the semiconductor substrate 7a due to the potential fluctuation of the semiconductor substrate 7a propagates through the insulating layer 7b to the semiconductor layer 7c in which the semiconductor integrated circuit is formed. ing.

Further, for example, the semiconductor layer 7 is caused by the potential of the semiconductor substrate 7a not being intended by the designer.
It is also possible to suppress a phenomenon in which electrical characteristics such as a threshold voltage of a MOS.FET (not shown) formed in c change.

In the chip carrier 1 of this embodiment, a power supply electrode (not shown) for applying a predetermined voltage to the semiconductor substrate 7a on the back surface of the semiconductor chip 7 is provided on the main surface side of the semiconductor chip 7. There is no need to provide it.

Therefore, several hundred BLs are originally formed on the main surface side of the semiconductor chip 7 for the power supply electrode.
Since the M pattern 8 is unnecessary, the layout rule of the BLM pattern 8 and the wiring (not shown) formed on the semiconductor layer 7c can be relaxed.

In addition, a step for forming the power supply electrode, for example, a hole reaching the semiconductor substrate 7a is formed in the semiconductor layer 7c and the insulating layer 7b, and an insulating film is formed on the side wall of the hole by an etch back method. There is no need for steps such as forming or burying low resistance polysilicon or the like in the holes. Therefore, the number of manufacturing steps of the semiconductor chip 7 can be reduced, and the manufacturing of the semiconductor chip 7 can be simplified.

The inner layer wiring 4a for electrically connecting the metallization layer 13b formed on the peripheral portion of the main surface of the package substrate 2 and the electrode 3b formed on the back surface of the package substrate 2 is
For example, it is made of the same metal as the inner layer wiring 4 and is formed at the same time when the inner layer wiring 4 is formed. Therefore, the manufacturing of the package substrate 2 does not become complicated due to the formation of the inner layer wiring 4a.

Incidentally, such a chip carrier 1 is mounted on the module substrate 14 via the CCB bumps 5 on the back surface of the package substrate 2, as shown in FIG.

Next, an example of a method of manufacturing the semiconductor integrated circuit device of the first embodiment will be described with reference to FIGS.

First, as shown in FIG. 5, the semiconductor chip 7 is mounted on the package substrate 2 via the CCB bumps 6.

In this step, B of the semiconductor chip 7 is
The CCB bumps 6 formed on the LM pattern 8 and the electrodes 3a of the package substrate 2 are aligned and superposed, and then the package substrate 2 is transported into a reflow furnace (not shown) and is then placed in the reflow furnace. The temperature is set to be slightly higher than the melting temperature of the solder of the CCB bump 6 and the solder is melted, so that the semiconductor chip 7 is mounted on the package substrate 2.

Subsequently, as shown in FIG. 6, a temporary fixing body 15 having a concave cross section is prepared, and the cap 11 is housed in the concave portion. At this time, the lower surface of the cap 11 faces upward.

After that, the solder preform 12 is placed in the recess of the lower surface of the cap 11, and then the package substrate 2 shown in FIG. At this time, the back surface of the semiconductor chip 7 mounted on the package substrate 2 faces downward.

The solder preform 12 is, for example, 1
Pb / Sn alloy containing about 0 wt% Sn (melting point:
290 to 300 ° C.).

Next, the temporary fixed body 15 is conveyed into the reflow furnace, the temperature inside the furnace is set to be slightly higher than the melting temperature of the solder preform 12, and the solder preform 12 is melted.

At this time, a predetermined load is applied from the back surface side of the package substrate 2.

Then, the melted solder becomes the metallized layer 1
3c wets and spreads along the surface of the metallization layer 13c, and a part of it spreads along the surface of the metallization layer 13d and quickly flows into the gap between the peripheral portion of the main surface of the package substrate 2 and the lower surface of the leg portion of the cap 11, as shown in FIG. , The solder 12a for sealing.

As a result, the step of sealing the semiconductor chip 7 can be shortened. Further, since the amount of load applied to the package substrate 2 at the time of sealing can be reduced, the CCB bumps 6 can be prevented from being crushed and the like, and the manufacturing yield of the chip carriers 1 can be improved.

After that, CCB is formed on the back surface of the package substrate 2.
The bumps 5 are formed and the chip carrier 1 shown in FIG. 1 is manufactured.

As described above, according to this embodiment, the following effects can be obtained.

(1) The solder 12a for sealing in the chip carrier 1 and the solder 12b for heat transfer joined to the back surface of the semiconductor chip 7 are electrically connected through the metallized layers 12a, 12c, 12d and sealed. By electrically connecting the metallization layer 12b joined to the fixing solder 12a and the electrode 3b on the back surface of the package substrate 2 through the inner layer wiring 4a, the semiconductor on the back surface of the semiconductor chip 7 from the electrode 3b on the back surface of the package substrate 2 is connected. Since a predetermined voltage can be applied to the substrate 7a, the potential of the semiconductor substrate 7a can be stabilized.

(2) Due to the above (1), it is possible to suppress the phenomenon that an induced current flows through the semiconductor substrate 7a when the semiconductor integrated circuit formed on the semiconductor layer 7c of the semiconductor chip 7 is driven. Therefore, it is possible to suppress the delay in the operating speed of the semiconductor integrated circuit due to the induced current.

(3). By the above (1), for example, the semiconductor substrate 7
It is also possible to suppress the phenomenon that noise generated in the semiconductor substrate 7a due to the potential fluctuation of a propagates to the semiconductor layer 7c in which the semiconductor integrated circuit is formed via the insulating layer 7b. Therefore, it is possible to suppress malfunction of the semiconductor integrated circuit due to the noise.

(4). By the above (1), for example, the semiconductor substrate 7
It is also possible to suppress a phenomenon in which electrical characteristics such as the threshold voltage of the MOS • FET formed in the semiconductor layer 7c change due to the potential of a becoming a potential not intended by the designer. Become.

(5) The operations of the semiconductor integrated circuit formed on the semiconductor chip 7 can be stabilized by the above (1) to (4). That is, the reliability of the chip carrier 1 can be improved.

(6) Because of the above (1), it is not necessary to provide a power supply electrode on the main surface side of the semiconductor chip 7 for applying a predetermined potential to the semiconductor substrate 7a on the back surface side of the semiconductor chip 7. Normally, the semiconductor chip 7 is used for the power supply electrode.
The BLM pattern 8 formed by several hundreds on the main surface side of is unnecessary. Therefore, the BLM pattern 8 and the semiconductor layer 7c
It is possible to relax the layout rule of the wiring formed above.

(7). Since it is not necessary to provide a power supply electrode for supplying a predetermined potential to the semiconductor substrate 7a on the rear surface side of the semiconductor chip 7, the power supply electrode is formed on the main surface side of the semiconductor chip 7. The process for doing so is unnecessary, the number of manufacturing steps of the semiconductor chip 7 can be reduced, and the manufacturing of the semiconductor chip 7 can be simplified.

Although the invention made by the present inventor has been specifically described based on the embodiments, the present invention is not limited to the embodiments and various modifications can be made without departing from the scope of the invention. Needless to say.

For example, in the above-mentioned embodiment, the case where the semiconductor chip is a semiconductor chip having an SOI structure has been described. However, the present invention is not limited to this, and it may be a normal semiconductor chip consisting of only a semiconductor substrate. In this case, the layout rule of the BLM pattern and the wiring on the semiconductor substrate can be relaxed, as in the above-described embodiment.

Further, in the above-mentioned embodiment, the case where the BLM pattern is composed of Cr / Cu / Au has been described, but the present invention is not limited to this, and various modifications are possible, for example, Ti / Ni / Au laminated layers. It may be formed of a metal film or a laminated metal film of Ti / platinum (Pt) / Au.

In the above description, the case where the invention made by the present inventor is mainly applied to a semiconductor integrated circuit device in which a BiC-MOS circuit is formed on a semiconductor chip, which is the field of application of the invention, has been described. The present invention is not limited to the above and can be variously applied, such as a semiconductor integrated circuit device in which an ECL circuit or a CMOS circuit is formed on a semiconductor chip,
It can also be applied to other semiconductor integrated circuit devices.

[0091]

The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows.
It is as follows.

That is, according to the invention of claim 1,
It is possible to supply a predetermined voltage from the electrodes on the back surface of the package substrate to the back surface of the semiconductor chip through the inner layer wiring inside the package substrate, the solder for sealing, and the solder for heat transfer. That is, it becomes possible to supply a predetermined voltage from the back surface side of the semiconductor chip.

Therefore, even when the semiconductor chip having the SOI structure is used, it is not necessary to provide a power supply electrode for supplying a predetermined voltage to the semiconductor substrate of the semiconductor chip on the main surface side of the semiconductor chip. That is, it is possible to reduce the process for forming the power supply electrode.

Further, since the potential of the semiconductor substrate forming the semiconductor chip having the SOI structure can be stabilized,
It is possible to stabilize the operation of the semiconductor integrated circuit formed on the semiconductor chip.

Therefore, even when the semiconductor chip having the SOI structure is used, the potential of the semiconductor substrate forming the semiconductor chip can be stabilized without complicating the manufacturing of the semiconductor chip, and the semiconductor chip can be manufactured. It is possible to stabilize the operation of the formed semiconductor integrated circuit.

[Brief description of drawings]

FIG. 1 is a cross-sectional view of essential parts of a semiconductor integrated circuit device that is an embodiment of the present invention.

FIG. 2 is a main-portion cross-sectional view of a semiconductor integrated circuit device for explaining a modified example of a bonding portion between a semiconductor chip and a package substrate.

FIG. 3 is an overall plan view of the lower surface of the cap.

4 is a cross-sectional view of the semiconductor integrated circuit device of FIG. 1 mounted on a module substrate.

5 is a sectional view of the semiconductor integrated circuit device of FIG. 1 during an assembling process.

6 is a cross-sectional view of the semiconductor integrated circuit device of FIG. 1 subsequent to FIG. 5 during an assembling process.

7 is a cross-sectional view of the semiconductor integrated circuit device of FIG. 1 subsequent to FIG. 6 during an assembling process.

FIG. 8 is a partially cutaway sectional view of a conventional chip carrier.

[Explanation of symbols]

 1 chip carrier (semiconductor integrated circuit device) 2 package substrate 3a electrode 3b electrode 4 inner layer wiring 4a inner layer wiring 5 CCB bump 6 CCB bump 7 semiconductor chip 7a semiconductor substrate 7b insulating layer 7c semiconductor layer 8 BLM pattern 9 thin film wiring board 10 inner layer wiring 11 Cap 12 Solder Preform 12a Sealing Solder 12b Heat Transfer Solder 13a Metallized Layer (First Metallized Layer) 13b Metallized Layer (First Metallized Layer) 13c Metallized Layer (Second Metallized Layer) 13d Metallized Layer 14 Module Substrate 15 Temporary fixed body 20 Chip carrier 21 Package substrate 22a Electrode 22b Electrode 23 CCB bump 24 Semiconductor chip 25 Cap 26 Sealing solder 27a Metallized layer 27b Metallized layer 28 Heat transfer solder

Claims (4)

[Claims] 1. A semiconductor chip is sealed by bonding a cap to a main surface of a package substrate on which a semiconductor chip is mounted via CCB bumps with a solder for sealing.
A semiconductor integrated circuit device in which the bottom surface of the cap and the back surface of the semiconductor chip are joined by heat transfer solder,
The sealing solder and the heat transfer solder are electrically connected, and the sealing solder and the electrodes formed on the back surface of the package substrate are electrically connected through inner layer wiring formed on the package substrate. A semiconductor integrated circuit device characterized by being connected. 2. A first metallization layer for improving the wettability of the sealing solder is provided on each of the peripheral portion of the main surface of the package substrate and the lower surface of the leg portion of the cap, and the semiconductor chip is A second metallization layer for improving the wettability of the heat transfer solder is provided on the lower surface of the cap to be joined, and the first metallization layer and the second metallization layer on the lower surface of the leg portion of the cap are partially formed. 2. The semiconductor integrated circuit device according to claim 1, wherein the sealing solder and the heat transfer solder are electrically connected to each other by continuously connecting with each other. 3. A semiconductor integrated circuit device according to claim 2, wherein the first metallized layer and the second metallized layer are made of the same conductor film formed in the same step. 4. The semiconductor chip is an SOI structure semiconductor chip in which a predetermined semiconductor integrated circuit element is formed in a semiconductor layer formed on a semiconductor substrate with an insulating layer interposed therebetween. 2. The semiconductor integrated circuit device according to 2 or 3.