JPH06188288A - Semiconductor integrated circuit device - Google Patents
Semiconductor integrated circuit deviceInfo
- Publication number
- JPH06188288A JPH06188288A JP4338332A JP33833292A JPH06188288A JP H06188288 A JPH06188288 A JP H06188288A JP 4338332 A JP4338332 A JP 4338332A JP 33833292 A JP33833292 A JP 33833292A JP H06188288 A JPH06188288 A JP H06188288A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor
- integrated circuit
- semiconductor integrated
- semiconductor chip
- circuit device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73253—Bump and layer connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1517—Multilayer substrate
- H01L2924/15172—Fan-out arrangement of the internal vias
- H01L2924/15174—Fan-out arrangement of the internal vias in different layers of the multilayer substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/1615—Shape
- H01L2924/16152—Cap comprising a cavity for hosting the device, e.g. U-shaped cap
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、半導体製造技術におけ
る半導体集積回路装置に関して、前記半導体集積回路装
置に実装される半導体チップの配線修復や配線追加を行
う技術に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device in a semiconductor manufacturing technique, and to a technique for repairing or adding wiring to a semiconductor chip mounted on the semiconductor integrated circuit device.
【０００２】[0002]
【従来の技術】従来の半導体集積回路装置の実装構造の
１つに、ＣＣＢ（Controlled Collapse Bonding ）バン
プを介してパッケージ基板に実装された半導体チップを
キャップにより気密封止したチップキャリア（Chip Car
rier）がある。このチップキャリアについては、例えば
特開昭６２−２４９４２９号、特開昭６３−３１０１３
９号公報において記載されている。2. Description of the Related Art One of conventional mounting structures for semiconductor integrated circuit devices is a chip carrier (Chip Car) in which a semiconductor chip mounted on a package substrate via CCB (Controlled Collapse Bonding) bumps is hermetically sealed by a cap.
rier). Regarding this chip carrier, for example, JP-A-62-2449429 and JP-A-63-31013.
No. 9 publication.
【０００３】図３は、前記文献に記載された従来の半導
体集積回路装置（以下、チップキャリアと呼ぶ）の構造
の一例を示す部分断面図である。FIG. 3 is a partial sectional view showing an example of the structure of a conventional semiconductor integrated circuit device (hereinafter referred to as a chip carrier) described in the above document.
【０００４】図３を用いて前記チップキャリア２０の構
成を説明すると、前記チップキャリア２０は、ムライト
などのセラミック材料からなるパッケージ基板２１の主
面に形成された電極２２ａ上に、ＣＣＢバンプ２３を介
して実装された半導体チップ２４をキャップ２５で気密
封止したものである。The structure of the chip carrier 20 will be described with reference to FIG. 3. The chip carrier 20 has a CCB bump 23 formed on an electrode 22a formed on the main surface of a package substrate 21 made of a ceramic material such as mullite. The semiconductor chip 24 mounted via the above is hermetically sealed with a cap 25.
【０００５】ここで、前記キャップ２５は、例えば熱伝
導特性に優れた窒化アルミニウム（ＡｌＮ）からなり、
封止用はんだ２６を介してパッケージ基板２１の主面に
接合されている。また、キャップ２５の下面と半導体チ
ップ２４の裏面（上面）とは、伝熱用はんだ２７を介し
て接合されており、前記半導体チップ２４から発生した
熱が伝熱用はんだ２７を経てキャップ２５から外部に放
散される構造になっている。Here, the cap 25 is made of, for example, aluminum nitride (AlN) having excellent heat conduction characteristics,
It is joined to the main surface of the package substrate 21 via the sealing solder 26. Further, the lower surface of the cap 25 and the back surface (upper surface) of the semiconductor chip 24 are joined via the heat transfer solder 27, and the heat generated from the semiconductor chip 24 passes from the cap 25 via the heat transfer solder 27. It has a structure that is diffused to the outside.
【０００６】さらに、チップキャリア２０は、パッケー
ジ基板２１の下面の電極２２ｂに接続された他のＣＣＢ
バンプ２９を介して図示しないモジュール基板に実装さ
れる。また、前記パッケージ基板２１の内部には、タン
グステン（Ｗ）からなる内部配線２８が形成されてお
り、この内部配線２８を通じてパッケージ基板２１の主
面および下面の電極２２ａと、２２ｂ間とが電気的に接
続されている。Further, the chip carrier 20 has another CCB connected to the electrode 22b on the lower surface of the package substrate 21.
It is mounted on a module substrate (not shown) via the bumps 29. Further, an internal wiring 28 made of tungsten (W) is formed inside the package substrate 21, and the electrodes 22a on the main surface and the lower surface of the package substrate 21 are electrically connected to each other through the internal wiring 28. It is connected to the.
【０００７】以上のように、チップキャリアにおいて
は、半導体チップの素子形成面上に設けたＣＣＢバンプ
（はんだバンプ）電極を介して半導体チップと外部回路
との間を電気的に接続する方法（フリップチップ方式）
が採用されてきている。前記フリップチップ方式は、半
導体チップの周辺部だけでなく、その内部領域にも端子
を設けることができるので、端子数を増やすことができ
る。また、ワイヤボンディング方式と比べて配線長が短
くなるので、信号伝送遅延を低減し、動作速度を高速化
することができる。さらに、半導体素子から発する熱を
半導体チップの裏面から効率良く発散させることもでき
る。As described above, in the chip carrier, the method of electrically connecting the semiconductor chip and the external circuit through the CCB bump (solder bump) electrode provided on the element formation surface of the semiconductor chip (flip Chip method)
Has been adopted. In the flip chip method, the terminals can be provided not only in the peripheral portion of the semiconductor chip but also in the internal region thereof, so that the number of terminals can be increased. In addition, since the wiring length is shorter than that of the wire bonding method, the signal transmission delay can be reduced and the operating speed can be increased. Further, the heat generated from the semiconductor element can be efficiently dissipated from the back surface of the semiconductor chip.
【０００８】したがって、これらの利点を備える前記フ
リップチップ方式は、大規模化、大電力化、多端子化す
る半導体装置の実装方式としてますます重要なものにな
ってきている。Therefore, the flip-chip method having these advantages is becoming more and more important as a mounting method for a semiconductor device which is large-scaled, has a large power consumption, and has a large number of terminals.
【０００９】一方、半導体集積装置の大規模化、複雑化
に伴い、ＬＳＩ回路に冗長回路を付加し、テスト後に前
記冗長回路のつなぎ替えを行なったり、チップ完成後に
論理修復を行なう技術が不可欠になってきている。前記
冗長回路を付加する方式には、ＬＳＩ内の配線（多結晶
Ｓｉ，Ｃｒ等）を電気的に溶断したり、レーザ溶断する
方式がある。また、論理修復を行う技術としては、完成
後のＬＳＩ上にレーザＣＶＤ（Chemical Vapor Deposit
ion)法により金属配線（Ｍｏ，Ｃｒ等）を形成する方法
がある。On the other hand, with the increase in scale and complexity of semiconductor integrated devices, a technique of adding a redundant circuit to an LSI circuit, connecting the redundant circuit after a test, and performing a logical repair after a chip is completed is indispensable. It has become to. As a method of adding the redundant circuit, there is a method of electrically fusing the wiring (polycrystalline Si, Cr, etc.) in the LSI or laser fusing. Further, as a technique for performing logic restoration, laser CVD (Chemical Vapor Deposit) is performed on the completed LSI.
There is a method of forming metal wiring (Mo, Cr, etc.) by the ion method.
【００１０】[0010]
【発明が解決しようとする課題】ところが、前述した従
来技術においては、溶断した配線部やレーザＣＶＤによ
り形成した金属配線部の長期信頼性が問題となる。特
に、ＬＳＩチップがモールド等による非気密構造となる
半導体集積回路装置の場合には、前記金属配線部の腐食
による断線や短絡不良が発生し、前記信頼性に対する問
題が顕著に現れることがある。However, in the above-mentioned conventional technique, the long-term reliability of the fused wiring portion or the metal wiring portion formed by laser CVD becomes a problem. In particular, in the case of a semiconductor integrated circuit device in which an LSI chip has a non-airtight structure by molding or the like, disconnection or short circuit failure may occur due to corrosion of the metal wiring portion, and the reliability problem may be prominent.
【００１１】また、従来の冗長回路付加方式やレーザＣ
ＶＤ法による金属配線形成方式においては、その回路の
設計および製造が非常に複雑である。The conventional redundant circuit addition system and laser C
In the metal wiring forming method by the VD method, the circuit design and manufacture are very complicated.
【００１２】本発明の目的は、ＣＣＢバンプ構造を備え
る半導体集積回路装置における冗長回路接続部や論理修
復部の信頼性を向上させることと、前記半導体集積回路
装置の設計や製造を簡便化することであり、さらに、大
規模化する前記半導体集積回路装置に適応した構造を提
供することにある。An object of the present invention is to improve the reliability of a redundant circuit connection portion and a logic restoration portion in a semiconductor integrated circuit device having a CCB bump structure, and to simplify the design and manufacture of the semiconductor integrated circuit device. It is another object of the present invention to provide a structure adapted to the semiconductor integrated circuit device which becomes larger in scale.
【００１３】本発明の前記ならびにその他の目的と新規
な特徴は、本明細書の記述および添付図面から明らかに
なるであろう。The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.
【００１４】[0014]
【課題を解決するための手段】本願において開示される
発明のうち、代表的なものの概要を簡単に説明すれば、
以下のとおりである。Among the inventions disclosed in the present application, a brief description will be given to the outline of typical ones.
It is as follows.
【００１５】すなわち、半導体チップの表面上に例えば
冗長回路用もしくは論理追加修復用の電極が設けられ、
前記電極がボンディングワイヤの少なくとも一部によっ
て接続されるものである。That is, for example, an electrode for a redundant circuit or an additional logical repair is provided on the surface of the semiconductor chip,
The electrodes are connected by at least a part of the bonding wires.
【００１６】また、前記ボンディングワイヤは絶縁被覆
を施されたものである。Further, the bonding wire has an insulating coating.
【００１７】[0017]
【作用】前記した手段によれば、冗長回路用もしくは論
理追加修復用の電極がボンディングワイヤの少なくとも
一部による接続のため、半導体集積回路装置の設計や製
造を簡便化することができる。According to the above-mentioned means, the electrodes for the redundant circuit or the additional logical repair are connected by at least a part of the bonding wires, so that the design and manufacture of the semiconductor integrated circuit device can be simplified.
【００１８】また、前記ボンディングワイヤは絶縁被覆
を施されているため、配線部の腐食が発生しにくくな
る。Further, since the bonding wire is provided with an insulating coating, corrosion of the wiring portion is unlikely to occur.
【００１９】[0019]
【実施例】図１は本発明の一実施例である半導体集積回
路装置（気密封止型チップキャリア）の構造を示す部分
断面図である。1 is a partial sectional view showing the structure of a semiconductor integrated circuit device (hermetically sealed chip carrier) according to an embodiment of the present invention.
【００２０】図１に示す本実施例のチップキャリア（半
導体集積回路装置）１の構成を説明すると、パッケージ
基板２は、例えばムライト等のようなセラミックス材料
からなり、その主面および裏面にはそれぞれ電極３ａ，
３ｂが形成されている。また、前記電極３ａ，３ｂは、
パッケージ基板２の内部に形成された内部配線４によっ
て電気的に接続されている。なお、内部配線４は、例え
ばタングステン（Ｗ）等のような高融点金属からなるも
のである。The structure of the chip carrier (semiconductor integrated circuit device) 1 of the present embodiment shown in FIG. 1 will be described. The package substrate 2 is made of a ceramic material such as mullite, and has a main surface and a back surface, respectively. Electrode 3a,
3b is formed. Further, the electrodes 3a and 3b are
It is electrically connected by the internal wiring 4 formed inside the package substrate 2. The internal wiring 4 is made of a refractory metal such as tungsten (W).
【００２１】さらに、前記パッケージ基板２の主面の電
極３ａには、ＣＣＢ（Controlled Collapse Bonding ）
バンプ６が接合されている。前記ＣＣＢバンプ６は、例
えば１〜５重量％程度の錫（Ｓｎ）を含有する鉛（Ｐ
ｂ）／Ｓｎ合金（融点：３２０〜３３０℃程度）からな
り、配置されるピッチは約２００μｍ、高さは約１００
μｍである。Further, CCB (Controlled Collapse Bonding) is provided on the electrode 3a on the main surface of the package substrate 2.
The bump 6 is joined. The CCB bumps 6 contain lead (P) containing, for example, about 1 to 5% by weight of tin (Sn).
b) / Sn alloy (melting point: about 320 to 330 ° C.), arranged pitch is about 200 μm, and height is about 100
μm.
【００２２】また、前記パッケージ基板２の裏面の電極
３ｂには、他のＣＣＢバンプ５が接合されている。前記
ＣＣＢバンプ５は、例えば３．５重量％程度の銀（Ａ
ｇ）を含有する錫（Ｓｎ）／Ａｇ合金（融点：２００〜
２５０℃程度）からなるものである。Another CCB bump 5 is bonded to the electrode 3b on the back surface of the package substrate 2. The CCB bump 5 has, for example, about 3.5% by weight of silver (A
g)) containing tin (Sn) / Ag alloy (melting point: 200-
About 250 ° C.).
【００２３】ここで、前記ＣＣＢバンプ６は、半導体チ
ップ７の主面に形成されたクロム（Ｃｒ）／ニッケル
（Ｎｉ）／金（Ａｕ）からなるバンプ用下地金属である
ＣＣＢバンプ電極６ａに接続されている。すなわち、パ
ッケージ基板２の主面の電極３ａには、ＣＣＢバンプ６
を介して半導体チップ７が電気的に接続されている。前
記半導体チップ７は、例えばＳｉ単結晶からなり、その
主面には、例えばＢｉＣ−ＭＯＳ回路によって構成され
た論理付きＳＲＡＭ（Static RAM）等のような図示しな
い半導体集積回路装置が形成されている。Here, the CCB bump 6 is connected to a CCB bump electrode 6a which is a base metal for bumps made of chromium (Cr) / nickel (Ni) / gold (Au) formed on the main surface of the semiconductor chip 7. Has been done. That is, the CCB bump 6 is formed on the electrode 3a on the main surface of the package substrate 2.
The semiconductor chip 7 is electrically connected via. The semiconductor chip 7 is made of, for example, Si single crystal, and a semiconductor integrated circuit device (not shown) such as an SRAM with logic (Static RAM) formed of, for example, a BiC-MOS circuit is formed on its main surface. .
【００２４】また、半導体チップ７は、キャップ８によ
って気密封止されている。前記キャップ８は、例えば窒
化アルミニウム（ＡｌＮ）からなり、封止用はんだ９ａ
を介してパッケージ基板２の主面に接合されている。前
記封止用はんだ９ａは、例えば１０重量％程度のＳｎを
含有するＰｂ／Ｓｎ合金（融点：２９０〜３００℃程
度）からなるものである。The semiconductor chip 7 is hermetically sealed by a cap 8. The cap 8 is made of, for example, aluminum nitride (AlN), and has a solder 9a for sealing.
It is bonded to the main surface of the package substrate 2 via. The sealing solder 9a is made of, for example, a Pb / Sn alloy (melting point: about 290 to 300 ° C.) containing about 10 wt% Sn.
【００２５】なお、キャップ８とパッケージ基板２との
接合部において、前記キャップ８および前記パッケージ
基板２のそれぞれの表面には、封止用はんだ９ａの接合
のために、例えばチタン（Ｔｉ）／ニッケル（Ｎｉ）／
金（Ａｕ）からなる図示しない接合用金属層が形成され
ている。At the joint between the cap 8 and the package substrate 2, for example, titanium (Ti) / nickel is formed on the respective surfaces of the cap 8 and the package substrate 2 for joining the sealing solder 9a. (Ni) /
A bonding metal layer (not shown) made of gold (Au) is formed.
【００２６】さらに、半導体チップ７の裏面は、伝熱用
はんだ９ｂを介してキャップ８の下面と接合されてお
り、これにより、回路動作時に半導体チップ７において
発生した熱が伝熱用はんだ９ｂを経てキャップ８の表面
から放散される構造となっている。Further, the back surface of the semiconductor chip 7 is joined to the bottom surface of the cap 8 via the heat transfer solder 9b, whereby heat generated in the semiconductor chip 7 during circuit operation is transferred to the heat transfer solder 9b. After that, the structure is such that it is diffused from the surface of the cap 8.
【００２７】ここで、前記伝熱用はんだ９ｂは、例えば
封止用はんだと同一のＰｂ／Ｓｎ合金からなるものであ
るが、前記キャップ８の下面においても、伝熱用はんだ
９ｂ接合のために、前記同様図示しない接合用金属層が
形成されている。Here, the heat transfer solder 9b is made of, for example, the same Pb / Sn alloy as the sealing solder, but the heat transfer solder 9b is joined to the lower surface of the cap 8 as well. Similarly to the above, a bonding metal layer (not shown) is formed.
【００２８】ところで、本実施例においては、前記半導
体チップ７の表面上に設けられた冗長回路用もしくは論
理追加修復用のワイヤボンディング電極６ｂにボンディ
ングワイヤ１６が接続されている。前記ワイヤボンディ
ング電極６ｂは、ＣＣＢバンプ６と同様にクロム（Ｃ
ｒ）／ニッケル（Ｎｉ）／金（Ａｕ）からなり、また、
前記ボンディングワイヤ１６は金（Ａｕ）線からなるも
のであるが、前記ボンディングワイヤ１６のワイヤルー
プ高さは、ＣＣＢバンプ６の高さより低くなるように約
８０μｍとした。By the way, in the present embodiment, the bonding wire 16 is connected to the wire bonding electrode 6b for redundant circuit or for logical additional repair provided on the surface of the semiconductor chip 7. The wire bonding electrode 6b is made of chromium (C) as in the CCB bump 6.
r) / nickel (Ni) / gold (Au), and
The bonding wire 16 is made of gold (Au) wire, and the wire loop height of the bonding wire 16 is set to about 80 μm so as to be lower than the height of the CCB bump 6.
【００２９】本実施例による作用効果は、冗長回路もし
くは論理追加修復のために半導体チップ７の表面上に設
けられた電極が、ワイヤボンディング法により接続され
ることであり、その結果、簡便なプロセスおよび高信頼
配線が実現できることである。The effect of this embodiment is that the electrodes provided on the surface of the semiconductor chip 7 for repairing the redundant circuit or additional logic are connected by the wire bonding method, and as a result, a simple process is performed. It is also possible to realize highly reliable wiring.
【００３０】以上、本発明者によってなされた発明を実
施例に基づき具体的に説明したが、本発明は前記実施例
に限定されるものではなく、その要旨を逸脱しない範囲
で種々変更可能であることは言うまでもない。The invention made by the present inventor has been specifically described above based on the embodiments, but the present invention is not limited to the embodiments and various modifications can be made without departing from the scope of the invention. Needless to say.
【００３１】例えば、本実施例においては、前記ボンデ
ィングワイヤを金線としたが、他の材料であるアルミニ
ウム線や銅合金線等を用いても良い。For example, in the present embodiment, the bonding wire is a gold wire, but other material such as aluminum wire or copper alloy wire may be used.
【００３２】また、前記ボンディングワイヤに絶縁被覆
を施したものを用いれば、前記ボンディングワイヤとＣ
ＣＢバンプとの接触による電気的な短絡不良を防止でき
る。If an insulating coating is used on the bonding wire, the bonding wire and C
It is possible to prevent an electrical short circuit failure due to contact with the CB bump.
【００３３】さらに、本実施例においては、キャップを
設けて半導体チップを気密封止する構造に適用したが、
モールド等による非気密構造の場合においても本実施例
と同様の効果が得られ、配線寿命の向上を図ることがで
きる。Further, in the present embodiment, the cap is provided and the semiconductor chip is hermetically sealed.
Even in the case of a non-airtight structure such as a mold, the same effect as this embodiment can be obtained, and the life of the wiring can be improved.
【００３４】また、半導体チップ上の冗長回路用もしく
は論理追加修復用の電極を接続する方法は、本実施例の
図１に示したような２個のワイヤボンディング電極６ｂ
間をボンディングワイヤ１６の両端によってワイヤリン
グ接続する方法とは別に、図２に示すようにボンディン
グワイヤ１６の一部によって２個の前記ワイヤボンディ
ング電極６ｂ間を接続する方法であってもよい。Further, the method of connecting the electrodes for the redundant circuit or the additional logical repair on the semiconductor chip is the two wire bonding electrodes 6b as shown in FIG. 1 of this embodiment.
Apart from the method of connecting the two ends of the bonding wire 16 by wiring, a method of connecting the two wire bonding electrodes 6b by a part of the bonding wire 16 may be used as shown in FIG.
【００３５】[0035]
【発明の効果】本願において開示される発明のうち、代
表的なものによって得られる効果を簡単に説明すれば、
下記のとおりである。The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows.
It is as follows.
【００３６】（１）．半導体集積回路装置に備えられる
半導体チップの表面上に設けられた例えば冗長回路用も
しくは論理追加修復用の電極が、ワイヤボンディングに
よって接続されるため、前記接続部の信頼性を向上させ
ることができる。(1). Since, for example, an electrode for a redundant circuit or an electrode for additional logical repair provided on the surface of a semiconductor chip included in the semiconductor integrated circuit device is connected by wire bonding, the reliability of the connecting portion can be improved.
【００３７】（２）．前記電極間がワイヤボンディング
による接続のため、前記半導体集積回路装置の設計や製
造を簡便化することができる。(2). Since the electrodes are connected by wire bonding, the design and manufacturing of the semiconductor integrated circuit device can be simplified.
【００３８】（３）．前記ワイヤボンディング時に用い
られるワイヤが絶縁被覆を施されているため、配線部の
腐食が発生しにくくなり、配線寿命の向上を図ることが
できる。(3). Since the wire used for the wire bonding has an insulating coating, corrosion of the wiring portion is less likely to occur, and the life of the wiring can be improved.
【図１】本発明の一実施例である半導体集積回路装置の
構造を示す部分断面図である。FIG. 1 is a partial cross-sectional view showing the structure of a semiconductor integrated circuit device which is an embodiment of the present invention.
【図２】本発明の他の実施例である半導体集積回路装置
の構造を示す部分断面図である。FIG. 2 is a partial cross-sectional view showing the structure of a semiconductor integrated circuit device which is another embodiment of the present invention.
【図３】従来の半導体集積回路装置の構造を示す部分断
面図である。FIG. 3 is a partial cross-sectional view showing the structure of a conventional semiconductor integrated circuit device.
１，２０ チップキャリア（半導体集積回路装置） ２，２１ パッケージ基板 ３ａ，３ｂ，２２ａ，２２ｂ 電極 ４，２８ 内部配線 ５，６，２３，２９ ＣＣＢバンプ ６ａ ＣＣＢバンプ電極 ６ｂ ワイヤボンディング電極 ７，２４ 半導体チップ ８，２５ キャップ ９ａ，２６ 封止用はんだ ９ｂ，２７ 伝熱用はんだ １６ ボンディングワイヤ 1, 20 Chip carrier (semiconductor integrated circuit device) 2, 21 Package substrate 3a, 3b, 22a, 22b Electrode 4,28 Internal wiring 5, 6, 23, 29 CCB bump 6a CCB bump electrode 6b Wire bonding electrode 7,24 Semiconductor Chip 8,25 Cap 9a, 26 Sealing solder 9b, 27 Heat transfer solder 16 Bonding wire
Claims (2)
ッケージ基板にフェイスダウン実装された半導体集積回
路装置であって、前記半導体チップの表面上に設けられ
た電極が、ボンディングワイヤの少なくとも一部によっ
て接続されていることを特徴とする半導体集積回路装
置。1. A semiconductor integrated circuit device in which a semiconductor chip is mounted facedown on a package substrate via CCB bumps, wherein electrodes provided on the surface of the semiconductor chip are connected by at least a part of a bonding wire. A semiconductor integrated circuit device characterized by being provided.
アルミニウムまたは銅合金からなり、前記ボンディング
ワイヤに絶縁被覆が施されていることを特徴とする請求
項１記載の半導体集積回路装置。2. The semiconductor integrated circuit device according to claim 1, wherein the bonding wire is made of gold, aluminum, or a copper alloy, and the bonding wire is covered with an insulating coating.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4338332A JPH06188288A (en) | 1992-12-18 | 1992-12-18 | Semiconductor integrated circuit device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4338332A JPH06188288A (en) | 1992-12-18 | 1992-12-18 | Semiconductor integrated circuit device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH06188288A true JPH06188288A (en) | 1994-07-08 |
Family
ID=18317158
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4338332A Pending JPH06188288A (en) | 1992-12-18 | 1992-12-18 | Semiconductor integrated circuit device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH06188288A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7439193B2 (en) | 2005-02-25 | 2008-10-21 | Seiko Epson Corporation | Patterning method for fabricating high resolution structures |
| WO2020225852A1 (en) * | 2019-05-07 | 2020-11-12 | 三菱電機株式会社 | Semiconductor device and method for manufacturing same |
-
1992
- 1992-12-18 JP JP4338332A patent/JPH06188288A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7439193B2 (en) | 2005-02-25 | 2008-10-21 | Seiko Epson Corporation | Patterning method for fabricating high resolution structures |
| WO2020225852A1 (en) * | 2019-05-07 | 2020-11-12 | 三菱電機株式会社 | Semiconductor device and method for manufacturing same |
| JPWO2020225852A1 (en) * | 2019-05-07 | 2021-10-21 | 三菱電機株式会社 | Semiconductor devices and their manufacturing methods |
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