JP2002373910A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JP2002373910A
JP2002373910A JP2002168959A JP2002168959A JP2002373910A JP 2002373910 A JP2002373910 A JP 2002373910A JP 2002168959 A JP2002168959 A JP 2002168959A JP 2002168959 A JP2002168959 A JP 2002168959A JP 2002373910 A JP2002373910 A JP 2002373910A
Authority
JP
Japan
Prior art keywords
semiconductor
layer
semiconductor chip
electrode
chip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2002168959A
Other languages
Japanese (ja)
Other versions
JP4754763B2 (en
Inventor
Kazutaka Shibata
和孝 柴田
Shigeyuki Ueda
茂幸 上田
Toshio Enami
俊夫 江南
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Rohm Co Ltd
Original Assignee
Rohm Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Rohm Co Ltd filed Critical Rohm Co Ltd
Priority to JP2002168959A priority Critical patent/JP4754763B2/en
Publication of JP2002373910A publication Critical patent/JP2002373910A/en
Application granted granted Critical
Publication of JP4754763B2 publication Critical patent/JP4754763B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
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    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device capable of improving integration by attaining the structure of joining a wire such as a gold wire for performing wire bonding and an electrode pad without inviting the application of a pressure due to the excessive rise of a temperature or ultrasonic waves or the like, and enabling element formation on the lower side of the electrode pad as well. SOLUTION: On the surface of a semiconductor substrate for which a circuit element is formed in a semiconductor layer, the electrode pad 13a for wire bonding is provided through an insulation film 17a or in contact with the semiconductor substrate. An Au layer 19a and an Sn layer 19b are provided on the surface of the electrode pad and the connection part of the wire 6 for wire bonding, and the electrode pad 13a is connected through an Au-Sn alloy layer.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【０００１】[0001]

【発明の属する技術分野】本発明は、複数の半導体チッ
プを対面させて電気的に接続する、いわゆるチップオン
チップ（chip on chip、以下ＣＯＣという）タイプの半
導体装置に関する。さらに詳しくは、マルチチップ化
し、第１の半導体チップの表面に複数個の第２の半導体
チップが直接接続される場合に、第２の半導体チップ間
同士で接続する配線が、第１の半導体の内部設計に依存
することなく、第２の半導体チップ間で自由に接続を変
更し得る半導体装置に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a so-called chip-on-chip (hereinafter, referred to as COC) type semiconductor device in which a plurality of semiconductor chips are faced and electrically connected. More specifically, when a plurality of second semiconductor chips are directly connected to the surface of the first semiconductor chip by forming a multi-chip, the wiring connected between the second semiconductor chips is formed of the first semiconductor chip. The present invention relates to a semiconductor device capable of freely changing a connection between second semiconductor chips without depending on an internal design.

【０００２】[0002]

【従来の技術】従来、たとえばメモリ素子とその論理回
路の組合せなどのように、回路の組合せにより半導体装
置が構成される場合、立体化による占有面積の縮小化、
高周波回路の寄生容量などの低減化、回路の一部の汎用
化（たとえばメモリ素子部を汎用化して駆動回路部分を
用途に応じて変更する）、大集積回路では、その回路部
分により製造条件の厳しさが異なり１チップ化が困難な
場合があるなどのため、半導体回路を複数個のチップに
より製造し、一方の半導体チップ（親チップ）上に他の
半導体チップ（子チップ）を接続する構造の、ＣＯＣタ
イプの半導体装置が用いられることがある。近年では、
図１１に示されるように、この子チップが複数個設けら
れるマルチチップ化の傾向にある。2. Description of the Related Art Conventionally, when a semiconductor device is constituted by a combination of circuits such as a combination of a memory element and its logic circuit, the occupation area is reduced by three-dimensionalization.
Reduction of parasitic capacitance and the like in high-frequency circuits, generalization of a part of the circuit (for example, generalization of the memory element portion and change of the drive circuit portion according to the application), and in the case of large integrated circuits, A structure in which a semiconductor circuit is manufactured by a plurality of chips and one semiconductor chip (parent chip) is connected to another semiconductor chip (child chip) because the degree of rigor varies and it may be difficult to make one chip. Of these, a COC type semiconductor device may be used. in recent years,
As shown in FIG. 11, there is a tendency for a multi-chip configuration in which a plurality of the sub chips are provided.

【０００３】図１１において、第１半導体チップ（親チ
ップ）１の電極端子１２上に第２半導体チップ（子チッ
プ）２ａ、２ｂの電極端子２２が、それぞれのバンプ電
極１１、２１を介して接続されている。親チップ１は、
リードフレームからなる図示しないアイランドにボンデ
ィングされ、親チップ１の外周側に設けられる図示しな
い各電極パッドは、アイランドの周囲に設けられる図示
しないリードとそれぞれ金線などのワイヤにより電気的
に接続され、その周囲が図示しない樹脂によりモールド
される。なお、１７はパシベーション膜である。In FIG. 11, electrode terminals 22 of second semiconductor chips (child chips) 2a and 2b are connected to electrode terminals 12 of a first semiconductor chip (parent chip) 1 via bump electrodes 11 and 21, respectively. Have been. Parent chip 1
Each electrode pad (not shown) provided on the outer peripheral side of the parent chip 1 is electrically connected to a lead (not shown) provided around the island by a wire such as a gold wire. The periphery is molded with a resin (not shown). Reference numeral 17 denotes a passivation film.

【０００４】このように、ＣＯＣタイプの半導体装置
は、親チップ１と子チップ間はそれぞれ電極端子上に設
けられるバンプ電極１１、２１などを介して接続され、
親チップ１の周囲に設けられる電極パッドを介して、外
部リードとワイヤを介して接続されている。したがっ
て、親チップ１と子チップ２間の信号伝達に関しては、
それぞれのバンプ電極を介して信号の授受が行われる。
しかし、複数個ある子チップ２ａ、２ｂ間で信号の授受
を行う場合、親チップ１の半導体層中、または半導体層
表面の絶縁膜中に配線を形成しておき、その配線の一部
を電極端子として絶縁膜から露出させ、前述の子チップ
の電極端子と接続することによりお互いに信号の授受を
行っている。As described above, in the COC type semiconductor device, the parent chip 1 and the child chip are connected via the bump electrodes 11 and 21 provided on the electrode terminals, respectively.
It is connected to external leads via wires via electrode pads provided around the parent chip 1. Therefore, regarding the signal transmission between the parent chip 1 and the child chip 2,
Signals are exchanged via the respective bump electrodes.
However, when transmitting and receiving signals between a plurality of child chips 2a and 2b, wiring is formed in the semiconductor layer of the parent chip 1 or in an insulating film on the surface of the semiconductor layer, and a part of the wiring is formed as an electrode. Signals are mutually transmitted and received by being exposed from the insulating film as terminals and being connected to the above-mentioned electrode terminals of the child chip.

【０００５】[0005]

【発明が解決しようとする課題】前述のように、ＣＯＣ
タイプの半導体装置で、親チップと子チップ間で信号の
授受を行う場合には、親チップと子チップとのバンプ電
極により接続することで問題ないが、複数個ある子チッ
プ間で信号を授受する場合、一々親チップ内に形成され
る配線を介して行わなければならない。そのため、せっ
かく親チップなどを汎用化して、用途に応じた回路を子
チップで形成するような場合でも、搭載する子チップに
応じて、親チップ内に配線を形成する必要があり、親チ
ップの汎用化に制約を受けるという問題がある。As described above, the COC
In the case of sending and receiving signals between a parent chip and a child chip in a semiconductor device of the type, there is no problem by connecting them with bump electrodes between the parent chip and the child chip, but signals are transmitted and received between a plurality of child chips. In this case, it must be performed via wirings formed in the parent chip. For this reason, even if the parent chip is generalized and the circuit according to the application is formed by the child chip, it is necessary to form wiring in the parent chip according to the mounted child chip. There is a problem that generalization is restricted.

【０００６】さらに、子チップの１つに外部から信号を
伝達する必要のある場合があるが、その場合でも、親チ
ップの電極パッドを介して親チップ内の配線を通じて子
チップに伝達しなければならず、親チップの汎用性の妨
げとなっている。Further, there is a case where it is necessary to transmit a signal from the outside to one of the child chips. Even in such a case, the signal must be transmitted to the child chip through the wiring in the parent chip through the electrode pads of the parent chip. Instead, it hinders the versatility of the parent chip.

【０００７】さらに、前述の親チップと子チップとの接
続は、Ａｕなどのバンプ電極を介して行われるため、４
５０℃程度の高温で行わないと、良好な電気的接続が得
られない。しかし、その際、半導体基板も高温になると
共に、バンプ電極にかかる圧力が半導体基板にもかかる
ため、バンプ電極の下側には、双方のチップ共に素子を
形成することができず、半導体基板の利用効率が低下す
るという問題がある。Further, since the connection between the above-mentioned parent chip and the child chip is made through bump electrodes such as Au, the connection between the parent chip and the child chip is not possible.
Unless performed at a high temperature of about 50 ° C., good electrical connection cannot be obtained. However, at this time, the temperature of the semiconductor substrate also becomes high, and the pressure applied to the bump electrode is also applied to the semiconductor substrate. Therefore, both chips cannot form an element under the bump electrode. There is a problem that utilization efficiency is reduced.

【０００８】本発明の目的は、ワイヤボンディングする
ための金線などのワイヤと電極パッドとの接合を温度の
過度な上昇や超音波などによる圧力の印加を招かないで
行い得る構造とし、その電極パッドの下側にも素子形成
を可能として、集積度を向上し得る半導体装置を提供す
ることにある。SUMMARY OF THE INVENTION An object of the present invention is to provide a structure in which a wire such as a gold wire for wire bonding can be bonded to an electrode pad without causing an excessive rise in temperature or application of pressure by ultrasonic waves or the like. It is an object of the present invention to provide a semiconductor device capable of improving the degree of integration by forming an element below a pad.

【０００９】[0009]

【課題を解決するための手段】本発明による半導体装置
は、半導体層に回路素子が形成された半導体基板と、該
半導体基板の表面に絶縁膜を介して、または半導体基板
と接触して設けられるワイヤボンディング用の電極パッ
ドと、該電極パッドに外部リードと接続するためボンデ
ィングされるワイヤとを有する半導体装置であって、前
記電極パッド表面にＡｕ層とＳｎ層とが設けられ、前記
ワイヤと電極パッドとの接続部がＡｕ-Ｓｎ合金層を介
して接続されている。A semiconductor device according to the present invention is provided with a semiconductor substrate having circuit elements formed on a semiconductor layer, and provided on the surface of the semiconductor substrate via an insulating film or in contact with the semiconductor substrate. What is claimed is: 1. A semiconductor device comprising: an electrode pad for wire bonding; and a wire bonded to the electrode pad for connection to an external lead, wherein an Au layer and a Sn layer are provided on the surface of the electrode pad. The connection portion with the pad is connected via an Au-Sn alloy layer.

【００１０】この構造にすることにより、ワイヤボンデ
ィングの際に、超音波によりボンディングパッド部を擦
る必要がなくなり、圧力も殆どかからないで接続作業を
することができるため、ワイヤボンディングをする電極
パッドの下の半導体層に、トランジスタなどの素子を形
成しても、ボンディングの際に素子が損傷するという問
題はなくなる。その結果、同じ半導体チップ内に沢山の
素子を形成することができ、集積度を向上させることが
できる。With this structure, it is not necessary to rub the bonding pad portion by ultrasonic waves during wire bonding, and the connection operation can be performed with little pressure. Even if an element such as a transistor is formed in the semiconductor layer, there is no problem that the element is damaged during bonding. As a result, many elements can be formed in the same semiconductor chip, and the degree of integration can be improved.

【００１１】[0011]

【発明の実施の形態】つぎに、図面を参照しながら本発
明の半導体装置について説明をする。本発明による半導
体装置は、図１にその一実施形態である断面構造ならび
に配線部の断面および平面の説明図が示されるように、
第１半導体チップ１の表面側に複数個の第２半導体チッ
プ２ａ、２ｂがバンプ電極１１、２１を介して接合され
る場合に、複数個の第２半導体チップのうち、２個の第
２半導体チップ２ａ、２ｂの電極端子２２ａ、２２ｂ同
士を直接接続する配線９が、第１半導体チップ１のパシ
ベーション膜１７の最表面に形成されている。Next, a semiconductor device according to the present invention will be described with reference to the drawings. The semiconductor device according to the present invention, as shown in FIG.
When a plurality of second semiconductor chips 2a and 2b are bonded to the front side of the first semiconductor chip 1 via bump electrodes 11 and 21, two second semiconductor chips of the plurality of second semiconductor chips are used. The wiring 9 for directly connecting the electrode terminals 22 a and 22 b of the chips 2 a and 2 b is formed on the outermost surface of the passivation film 17 of the first semiconductor chip 1.

【００１２】図１に示される例では、その配線部の拡大
説明図が図１（ｂ）に示されるように、第１半導体チッ
プ１および第２半導体チップ２ａ、２ｂ共に、バンプ電
極１１、２１が５〜３０μｍ程度の厚さに形成され、第
１半導体チップ１のバンプ電極１１の形成と同時に、第
２半導体チップ２ａ、２ｂ間で直接接続する必要のある
電極端子２１ａ、２１ｂに対応する電極端子１２ａ間に
配線９が形成されている。バンプ電極１１、２１自身
は、従来と同様に形成され、たとえば図１（ｂ）に示さ
れるように、Ａｌなどからなる電極端子１２上に、バリ
アメタル層１４がスパッタリング、真空蒸着などにより
２層または３層構造で成膜してパターニングすることに
より形成される。バリアメタル層１４の第１層にはＴｉ
またはＣｒが、第２層にはＷ、Ｐｔ、Ａｇ、Ｃｕ、Ｎｉ
などが、第３層にはＡｕなどが用いられ、全体で０.２
〜２μｍ程度の厚さに形成される。そして、その上にバ
ンプ電極１１が、Ａｕ、Ｃｕなどの金属を電解メッキな
どの方法により前述の厚さに形成される。なお、第２半
導体チップ２のバンプ電極２１も同様に形成される。な
お、図１では、電極端子が直接半導体層に設けられてい
るように示されているが、半導体層に接続される場合
も、層間絶縁膜内の配線に接続される場合もある。In the example shown in FIG. 1, as shown in FIG. 1B, an enlarged explanatory view of a wiring portion thereof, both the first semiconductor chip 1 and the second semiconductor chips 2a, 2b have bump electrodes 11, 21. Are formed to a thickness of about 5 to 30 μm, and at the same time as the formation of the bump electrodes 11 of the first semiconductor chip 1, the electrodes corresponding to the electrode terminals 21a and 21b which need to be directly connected between the second semiconductor chips 2a and 2b. The wiring 9 is formed between the terminals 12a. The bump electrodes 11 and 21 are formed in the same manner as in the prior art. For example, as shown in FIG. 1B, two layers of a barrier metal layer 14 are formed on an electrode terminal 12 made of Al or the like by sputtering or vacuum deposition. Alternatively, it is formed by forming a film with a three-layer structure and patterning. The first layer of the barrier metal layer 14 includes Ti
Or, Cr is W, Pt, Ag, Cu, Ni in the second layer.
Au or the like is used for the third layer.
It is formed to a thickness of about 2 μm. Then, a bump electrode 11 is formed thereon with a metal such as Au, Cu or the like to the above-mentioned thickness by a method such as electrolytic plating. Note that the bump electrodes 21 of the second semiconductor chip 2 are formed in the same manner. Although FIG. 1 shows that the electrode terminal is provided directly on the semiconductor layer, the electrode terminal may be connected to the semiconductor layer or may be connected to a wiring in the interlayer insulating film.

【００１３】このバンプ電極１１を形成する際に、第２
半導体チップ２ａ、２ｂを直接接続する必要のある電極
端子２２ａ、２２ｂに対応する第１半導体チップ１の電
極端子１２ａ同士が連結されるように、バリアメタル層
１４およびバンプ電極材料が設けられることにより、配
線９が形成されている。したがって、バリアメタル層１
４をパターニングする際に、配線が形成されるようにパ
ターニングするだけで、従来のバンプ電極１１形成工程
の作業だけで同時に配線９を形成することができる。こ
の配線９は、バンプ電極１１のように幅広に形成する必
要はなく、図１（ｃ）に配線９部の平面説明図が示され
るように、配線部の幅が狭くなるようにパターニングさ
れてもよい。When forming the bump electrode 11, the second
The barrier metal layer 14 and the bump electrode material are provided so that the electrode terminals 12a of the first semiconductor chip 1 corresponding to the electrode terminals 22a and 22b which need to directly connect the semiconductor chips 2a and 2b are connected. And the wiring 9 are formed. Therefore, the barrier metal layer 1
When patterning the wiring 4, the wiring 9 can be simultaneously formed only by the conventional bump electrode 11 forming process simply by patterning so that the wiring is formed. The wiring 9 does not need to be formed as wide as the bump electrode 11, and is patterned so that the width of the wiring portion is reduced as shown in a plan view of the wiring 9 portion in FIG. Is also good.

【００１４】バンプ１１、２１の接続部は、図２に説明
図が示されるように、Ａｕからなるバンプ電極１１上に
Ｓｎ被膜１１ａが設けられることにより、Ａｕの融点
は、１０６４℃程度（同一金属同士であるため、加圧し
ながら加熱することにより、４５０℃程度で融着する）
であるのに対して、Ｓｎの融点は、２３２℃程度であ
り、２３０℃程度になると溶融し、Ａｕと共晶を形成し
て合金化し、２８０℃程度でＡｕ-Ｓｎ合金からなる合
金層３がその接合面に形成されて、両者のバンプ電極１
１、２１が溶着する。すなわち、半導体基板に形成され
る回路素子などに対しては支障のない低い温度で両バン
プ電極１１、２１を融着させることができる。As shown in FIG. 2, the connection between the bumps 11 and 21 is provided with a Sn coating 11a on the bump electrode 11 made of Au, so that the melting point of Au is about 1064 ° C. (Because they are metals, they are fused at about 450 ° C by heating while applying pressure.)
On the other hand, the melting point of Sn is about 232 ° C., melting at about 230 ° C., forming a eutectic with Au and alloying, and forming an alloy layer 3 of Au—Sn alloy at about 280 ° C. Are formed on the joint surface, and both bump electrodes 1 are formed.
1, 21 are welded. That is, the two bump electrodes 11 and 21 can be fused at a low temperature that does not hinder the circuit elements formed on the semiconductor substrate.

【００１５】このように、バンプ電極１１、２１には融
点の高い金属を用い、融点の低い金属と合金化しやすい
金属被膜をその接合面に設けて合金化させることによ
り、低い温度で接着することができ、しかもバンプとし
ては融点の高い金属で高い強度を維持することができ
る。すなわち、ハンダ付けの温度に対しては支障のない
低い温度で両バンプ電極１１、２１を融着させることが
できる。なお、配線９上にはＳｎ被膜が設けられないよ
うにしてもよいし、設けられても構わない。また、第２
半導体チップ側のバンプ電極のみにＳｎ被膜を設けるよ
うにしてもよい。また、この観点からは、ＡｕとＳｎと
に限られるものではない。As described above, a metal having a high melting point is used for the bump electrodes 11 and 21, and a metal film which is easily alloyed with a metal having a low melting point is provided on the joint surface and alloyed, so that the bonding is performed at a low temperature. In addition, a metal having a high melting point as a bump can maintain high strength. That is, the two bump electrodes 11 and 21 can be fused at a low temperature that does not hinder the soldering temperature. Note that the Sn film may not be provided on the wiring 9 or may be provided. Also, the second
The Sn coating may be provided only on the bump electrodes on the semiconductor chip side. In addition, from this viewpoint, it is not limited to Au and Sn.

【００１６】前述の図２に示されるように、Ｓｎ被膜１
１ａは一方のバンプ電極１１のみに形成されることが、
接合面の合金層を形成しやすいため好ましい。すなわ
ち、ＡｕとＳｎとの接触部が合金化して接合するため、
両方のバンプにＳｎ被膜が設けられていると、Ｓｎ被膜
とＳｎ被膜との接触部が直ちには接合せず、バンプ電極
表面のＡｕ層とＳｎ被膜との接触部から合金化し、Ａｕ
が接合部に拡散して合金化することにより接合するた
め、Ａｕ層とＳｎ被膜とが接触するように形成されるこ
とが好ましい。しかし、両方のバンプ電極に設けるＳｎ
被膜を非常に薄くすることにより、容易にＡｕが拡散す
るため、両方のバンプ電極に形成してもよい。また、接
合するバンプ電極同士に大小がある場合、小さい方のバ
ンプ電極にＳｎ被膜を設ける方が、接合部の合金化部分
が少なく、後で分離する可能性のある場合には都合がよ
い。As shown in FIG. 2, the Sn coating 1
1a is formed on only one bump electrode 11,
This is preferable because an alloy layer on the joint surface can be easily formed. That is, since the contact portion between Au and Sn is alloyed and joined,
If the Sn film is provided on both bumps, the contact portion between the Sn film and the Sn film does not immediately join, but is alloyed from the contact portion between the Au layer and the Sn film on the surface of the bump electrode.
Is diffused into the bonding portion to form an alloy, so that the Au layer and the Sn coating are preferably in contact with each other. However, Sn provided on both bump electrodes
Since Au is easily diffused by making the coating very thin, it may be formed on both bump electrodes. Further, when the bump electrodes to be bonded are large or small, it is more convenient to provide the Sn coating on the smaller bump electrode when there is a small alloyed portion at the bonding portion and there is a possibility that the bump electrodes will be separated later.

【００１７】一方、接合した２つの半導体チップを取り
外す可能性がなく、しっかりと接続するためには、図３
に示されるように、バンプ電極１１の上面だけではな
く、側面周囲全体も被覆するようにＳｎ被膜１１ａを形
成することにより、合金化すれば合金層３は小さいバン
プ電極１１の周囲から大きい方のバンプ電極２１にフィ
レット３ａを形成し、強力に接合することができる。な
お、図３において、電極パッドなどは省略して図示する
と共に、図２と同じ部分には同じ符号を付してある。ま
た、前述のバンプ電極の上面のみにＳｎ被膜を設ける場
合でも、バンプ電極に大小がある場合、大きい方のバン
プ電極に形成すれば、接着強度を強くすることができ
る。On the other hand, there is no possibility of removing the two bonded semiconductor chips, and in order to connect them firmly, it is necessary to use the semiconductor device shown in FIG.
As shown in FIG. 2, by forming the Sn coating 11a so as to cover not only the upper surface of the bump electrode 11 but also the entire periphery of the side surface, the alloy layer 3 can be alloyed from the periphery of the smaller bump electrode 11 by alloying. The fillet 3a can be formed on the bump electrode 21 and can be strongly bonded. In FIG. 3, the electrode pads and the like are omitted from the illustration, and the same parts as those in FIG. 2 are denoted by the same reference numerals. Further, even when the Sn film is provided only on the upper surface of the above-mentioned bump electrode, if the bump electrode is large or small, the bonding strength can be increased by forming it on the larger bump electrode.

【００１８】前述の合金層は、完全な共晶合金になる
と、Ａｕ８０ｗｔ％（重量％、以下同じ）、Ｓｎ２０ｗ
ｔ％になるが、接合時に充分に温度を上げる訳ではない
ため、接合部は完全な共晶合金にはなりにくい。しか
し、完全な共晶合金にならなくても、Ａｕが６５ｗｔ％
以上であれば、強固な接合が得られると共に、分離する
場合でも３００℃程度に加熱することにより、接合部の
みを分離することができる。また、合金層を形成しない
で、Ａｕ層のみが存在することが、機械的強度が強く好
ましい。ＳｎよりＡｕの拡散が１０倍程度以上大きいた
め、たとえば接合時の温度、時間、Ｓｎ層の量などの調
整により、Ａｕが６５ｗｔ％以上の合金層で、Ａｕ層が
１００ｗｔ％の部分が残るように接合することができ
る。さらに好ましくは、Ａｕ-Ｓｎ共晶層が０.８μｍ以
上５μｍ以下であることが好ましい。このようにするに
は、Ｓｎ被膜の厚さを０.１〜４μｍ程度にすることに
より得られる。この際、完全なＡｕ層を残すためには、
Ａｕ層（バンプ電極）の厚さを厚く形成することにより
得られる。When the above-mentioned alloy layer becomes a complete eutectic alloy, Au 80% by weight (% by weight, the same applies hereinafter), Sn20w
However, since the temperature is not sufficiently increased at the time of joining, it is difficult for the joint to become a perfect eutectic alloy. However, even if it does not become a perfect eutectic alloy, Au is 65 wt%
Above, a strong bond can be obtained, and even in the case of separation, only the bonded portion can be separated by heating to about 300 ° C. Further, it is preferable that only the Au layer be present without forming the alloy layer because of its high mechanical strength. Since the diffusion of Au is about 10 times or more larger than that of Sn, by adjusting the temperature, time, amount of Sn layer, and the like at the time of bonding, for example, an alloy layer containing 65% by weight or more of Au and a portion of 100% by weight of Au remain. Can be joined. More preferably, the Au—Sn eutectic layer has a thickness of 0.8 μm or more and 5 μm or less. This can be achieved by setting the thickness of the Sn coating to about 0.1 to 4 μm. At this time, in order to leave a complete Au layer,
It can be obtained by forming a thick Au layer (bump electrode).

【００１９】第１半導体チップ１は、たとえばデジタル
信号プロセッサなどの論理回路などが半導体基板に形成
され、その表面には層間絶縁膜や配線膜などが設けら
れ、最終的にメモリ素子などの第２半導体チップ２との
接続用電極端子１２と、外部リードとの接続用の電極パ
ッド１３がＡｌなどによりその表面に形成されている。
この際、その表面に接続する第２半導体チップと直接に
は接続する必要はないが、複数の第２半導体チップ２
ａ、２ｂ間で接続する電極端子２２ａ、２２ｂに対応す
る部分にも電極端子１２ａを形成しておく。この電極端
子１２、１２ａ上に前述のようにバリアメタル層１４を
介してバンプ電極１１が形成されると共に、第２半導体
チップ２ａ、２ｂ間で接続する電極端子２２ａ、２２ｂ
に対応する電極端子１２ａ同士を接続する配線９を、バ
ンプ電極１１と同じ材料で同時に形成する。なお、通常
の第２半導体チップ２ａ、２ｂと直接接続する電極端子
１２には、配線は形成されないで、バンプ電極１１のみ
が形成される。この回路素子（半導体素子）や半導体基
板の表面に形成される配線、電極端子、絶縁膜などは、
通常の半導体装置の製造工程と同様に形成される。な
お、通常のシリコン基板でなくても、ＧａＡｓなど化合
物半導体基板に形成されてもよい。The first semiconductor chip 1 has, for example, a logic circuit such as a digital signal processor formed on a semiconductor substrate, and an interlayer insulating film or a wiring film provided on the surface thereof. Electrode terminals 12 for connection to the semiconductor chip 2 and electrode pads 13 for connection to external leads are formed on the surface of Al or the like.
At this time, it is not necessary to directly connect to the second semiconductor chip connected to the surface, but a plurality of second semiconductor chips 2
The electrode terminals 12a are also formed in portions corresponding to the electrode terminals 22a and 22b to be connected between a and 2b. The bump electrodes 11 are formed on the electrode terminals 12 and 12a via the barrier metal layer 14 as described above, and the electrode terminals 22a and 22b are connected between the second semiconductor chips 2a and 2b.
Are formed simultaneously with the same material as the bump electrode 11. Note that no wiring is formed on the electrode terminals 12 directly connected to the normal second semiconductor chips 2a and 2b, and only the bump electrodes 11 are formed. Wiring, electrode terminals, insulating films, etc. formed on the surface of this circuit element (semiconductor element) or semiconductor substrate
It is formed in the same manner as in a normal semiconductor device manufacturing process. In addition, it may be formed not on a normal silicon substrate but on a compound semiconductor substrate such as GaAs.

【００２０】第２半導体チップ２は、たとえばメモリ素
子がマトリクス状に形成されたもので、第１半導体チッ
プ１と接続される部分、複数個ある第２半導体チップ同
士で接続される部分、外部リードなどに接続される部分
などが電極端子２２として半導体基板の表面に形成さ
れ、その電極端子２２の表面にも前述の第１半導体チッ
プ１と同様に、Ａｕなどによりバンプ電極２１が形成さ
れている。このバンプ電極２１の表面にも、前述のＳｎ
被膜が形成されていてもよい。また、第１半導体チップ
１にはＳｎ皮膜が形成されないで、第２半導体チップ２
のバンプ電極２１のみにＳｎ被膜が形成されてもよい。
この第２半導体チップ２は、このようなＩＣでなくて
も、トランジスタ、ダイオード、キャパシタなどのディ
スクリート部品などで、半導体基板に形成されないもの
でもかまわない。とくに、静電破壊防止用の複合半導体
装置にする場合、ディスクリートの保護ダイオードなど
を第２半導体チップとして搭載することが、大容量の保
護素子を内蔵することができるため好ましい。The second semiconductor chip 2 has, for example, memory elements formed in a matrix, and is connected to the first semiconductor chip 1, a portion connected between a plurality of second semiconductor chips, and external leads. A portion connected to the like is formed on the surface of the semiconductor substrate as the electrode terminal 22, and the bump electrode 21 is also formed of Au or the like on the surface of the electrode terminal 22, similarly to the first semiconductor chip 1 described above. . The above-mentioned Sn
A coating may be formed. Further, the Sn film is not formed on the first semiconductor chip 1 and the second semiconductor chip 2
The Sn film may be formed only on the bump electrode 21 of FIG.
The second semiconductor chip 2 is not limited to such an IC, but may be a discrete component such as a transistor, a diode, or a capacitor, which is not formed on a semiconductor substrate. In particular, in the case of a composite semiconductor device for preventing electrostatic breakdown, it is preferable to mount a discrete protection diode or the like as the second semiconductor chip because a large-capacity protection element can be incorporated.

【００２１】この第１半導体チップ１と第２半導体チッ
プ２のバンプ電極１１、２１同士の接続は、たとえば第
１半導体チップ１を加熱し得る基板ステージ上に載置し
て、マウンターにより第２半導体チップ２をそのバンプ
同士が一致するように位置合せをして、加圧しながら３
００℃程度に加熱することにより、融着することができ
る。The connection between the bump electrodes 11 and 21 of the first semiconductor chip 1 and the second semiconductor chip 2 is performed, for example, by mounting the semiconductor chip on a substrate stage capable of heating the first semiconductor chip 1 and mounting the second semiconductor chip 1 by a mounter. The chip 2 is positioned so that the bumps thereof coincide with each other, and 3
By heating to about 00 ° C., fusion can be performed.

【００２２】第１および第２の半導体チップ１、２の隙
間には、後述するように、エポキシ樹脂、エポキシ-フ
ェノール樹脂またはエラストマーなどからなる絶縁性樹
脂が充填される。この接合された半導体チップ１、２
ａ、２ｂは、通常の半導体装置の製造と同様に、リード
フレームからなるダイアイランド４上にボンディングさ
れ、さらに各リード５と金線などのワイヤ６によりボン
ディングされ、モールド成形により樹脂パッケージ８が
形成される。そして、リードフレームから各リードが切
断分離された後に、フォーミングされることにより、図
１（ａ）に示されるような形状の半導体装置が得られ
る。The gap between the first and second semiconductor chips 1 and 2 is filled with an insulating resin such as an epoxy resin, an epoxy-phenol resin or an elastomer, as described later. The joined semiconductor chips 1 and 2
a and 2b are bonded on a die island 4 composed of a lead frame, and further bonded with each lead 5 and a wire 6 such as a gold wire, as in the manufacture of a normal semiconductor device, and a resin package 8 is formed by molding. Is done. Then, after each lead is cut and separated from the lead frame, forming is performed, whereby a semiconductor device having a shape as shown in FIG. 1A is obtained.

【００２３】図１に示される例は、第２半導体チップ２
ａ、２ｂの電極端子の接続部のみが示されているが、図
４に、第１半導体チップ１の平面説明図が示されるよう
に、第１半導体チップ１の電極パッド１３ａから、第１
半導体チップ１の内部配線を経由しないで、直接第２半
導体チップ２ｂ、２ｃに接続する配線９ｃを形成するこ
ともできるが、この点については後述する図９で詳述す
る。すなわち、図４に示される例では、たとえば３個の
第２半導体チップ２ａ〜２ｃが搭載される構造になって
おり、第２半導体チップ２ａ、２ｂ、２ｃ間、および第
２半導体チップ２ｂ、２ｃと電極パッド１３ａ間での電
極端子の接続が複数組形成されており、このような場合
でも、その第２半導体チップ２ａと２ｂ、２ｂと２ｃ同
士で接続する電極端子に対応する第１半導体チップ１の
電極端子１２ａ間、および電極端子１２ｂと電極パッド
１３ａとの間を接続する配線９、９ｃが、そのバンプ電
極１１と同時に形成されている。なお、図４では、バン
プ電極１１の下側の電極端子１２、１２ａ、１２ｂの符
号も付してある。図４において、１３は通常の外部リー
ドと接続用の電極パッドである。The example shown in FIG.
Although only the connection portions of the electrode terminals a and 2b are shown, as shown in the plan view of the first semiconductor chip 1 in FIG.
The wiring 9c connected directly to the second semiconductor chips 2b and 2c can be formed without passing through the internal wiring of the semiconductor chip 1, but this will be described in detail in FIG. 9 described later. That is, in the example shown in FIG. 4, for example, three second semiconductor chips 2a to 2c are mounted, and between the second semiconductor chips 2a, 2b and 2c, and between the second semiconductor chips 2b and 2c A plurality of pairs of electrode terminals are formed between the first semiconductor chip and the electrode pads 13a. Even in such a case, the first semiconductor chip corresponding to the electrode terminals connected between the second semiconductor chips 2a and 2b, 2b and 2c Wirings 9 and 9c connecting between the one electrode terminal 12a and between the electrode terminal 12b and the electrode pad 13a are formed simultaneously with the bump electrode 11. In FIG. 4, reference numerals for the lower electrode terminals 12, 12 a, and 12 b are also given. In FIG. 4, reference numeral 13 denotes a normal external lead and an electrode pad for connection.

【００２４】本発明の半導体装置によれば、第１半導体
チップ上に複数個の第２半導体チップを接続するＣＯＣ
タイプで、第２半導体チップ同士を接続する必要のある
電極端子を、それぞれの電極端子に対応する第１半導体
チップの部分に電極端子を形成しておき、その電極端子
にバンプを形成する際、またはバンプと接合し得る金属
膜を形成する際に、そのバンプまたは金属膜と同じ材料
で、同時にその電極端子間を接続する配線を形成し、バ
ンプ電極により第１半導体チップと第２半導体チップと
を接合することにより、第２半導体チップ間の接続を行
っているため、第２半導体チップの内容を変えることに
より第２半導体チップ間の接続関係が変化させても、第
１半導体チップの配線設計などを変更することなく、バ
ンプ形成の際のパターニングを変えるだけで所望の接続
をすることができる。According to the semiconductor device of the present invention, a COC for connecting a plurality of second semiconductor chips on a first semiconductor chip is provided.
In the type, the electrode terminals required to connect the second semiconductor chips to each other, the electrode terminals are formed in portions of the first semiconductor chip corresponding to the respective electrode terminals, and when forming the bumps in the electrode terminals, Alternatively, when forming a metal film that can be bonded to the bump, a wiring for simultaneously connecting the electrode terminals is formed using the same material as the bump or the metal film, and the first semiconductor chip and the second semiconductor chip are connected to each other by the bump electrode. The connection between the second semiconductor chips is performed by joining the first and second semiconductor chips. Therefore, even if the connection relationship between the second semiconductor chips is changed by changing the contents of the second semiconductor chips, the wiring design of the first semiconductor chip is changed. A desired connection can be made only by changing the patterning at the time of forming the bump without changing the configuration.

【００２５】すなわち、半導体層、またはその表面の絶
縁膜中に配線を形成する方法では、第１半導体装置の設
計を変形する必要があり、第１半導体チップの設計を変
更しなければならないが、本発明によれば、パシベーシ
ョン膜の最表面に接続用の配線を形成しているため、バ
ンプ電極またはバンプ電極と接合し得る金属膜を設ける
際に所望のパターンの配線を形成するだけで、第１半導
体チップの設計仕様を全然変更する必要がない。That is, in the method of forming the wiring in the semiconductor layer or the insulating film on the surface thereof, it is necessary to modify the design of the first semiconductor device and change the design of the first semiconductor chip. According to the present invention, the wiring for connection is formed on the outermost surface of the passivation film. Therefore, when providing a bump electrode or a metal film that can be bonded to the bump electrode, only a wiring of a desired pattern is formed. There is no need to change the design specifications of one semiconductor chip at all.

【００２６】前述の例では、第１半導体チップ１および
第２半導体チップ２（２ａ、２ｂ）の両方の電極端子に
バンプ電極１１、２１が形成されていたが、バンプ電極
はその接続部にあれば一方だけでもよい。また、配線９
は、前述のようにバンプ電極１１の厚さと同じ厚さにす
る必要はなく、通常の配線と同様の数μｍ以下でよい。
この観点から、たとえば図５に示されるように、バンプ
電極は第２半導体チップ２（２ａ、２ｂ）のみに設け、
第１半導体チップ１には、バリア層１４と第２半導体チ
ップ２のバンプ電極と同じ材料であるＡｕ膜１５を形成
し、配線９もバリア層１４とＡｕ膜１５により形成され
てもよい。In the above-described example, the bump electrodes 11, 21 are formed on both the electrode terminals of the first semiconductor chip 1 and the second semiconductor chip 2 (2a, 2b). Only one may be used. In addition, wiring 9
It is not necessary to make the thickness the same as the thickness of the bump electrode 11 as described above, and it may be several μm or less as in the case of ordinary wiring.
From this viewpoint, for example, as shown in FIG. 5, the bump electrodes are provided only on the second semiconductor chip 2 (2a, 2b),
An Au film 15 made of the same material as the barrier layer 14 and the bump electrode of the second semiconductor chip 2 may be formed on the first semiconductor chip 1, and the wiring 9 may be formed by the barrier layer 14 and the Au film 15.

【００２７】すなわち、図５において、第２半導体チッ
プ２ａ、２ｂ間を直接接続する電極端子２２ａ、２２ｂ
に対応する第１の半導体チップ１における電極端子１２
ａの上およびその間には、バリアメタル層１４を介し
て、たとえばＡｕなどからなる０.２〜０.７μｍ程度の
厚さの金属膜（Ａｕ膜）１５が設けられている（バリア
層１４は前述の例と同じ）。そして、第２半導体チップ
２には、前述と同様にＡｕからなるバンプ電極２１およ
びＳｎ被膜２３が形成されており、そのバンプ電極２１
と電極端子１２ａ上のＡｕ膜１５とが融着する構造にな
っている。この例では、バンプ電極２１上にＳｎ被膜２
３が形成されているが、このようにバンプ電極２１上ま
たはＡｕ膜１５上にＳｎ被膜が形成されることにより、
バンプとの融着温度を下げることができる。なお、図示
しない第１半導体チップ１と第２半導体チップ２との間
で接続する電極端子１２も同様にバリア層１４およびＡ
ｕ膜１５が形成され、Ｓｎ被膜などを介して第２半導体
チップ２側に設けられるバンプ電極２１とにより融着さ
れる。That is, in FIG. 5, the electrode terminals 22a, 22b for directly connecting the second semiconductor chips 2a, 2b are provided.
Terminal 12 in the first semiconductor chip 1 corresponding to
A metal film (Au film) 15 made of, for example, Au or the like and having a thickness of about 0.2 to 0.7 μm is provided on and between the layers a through the barrier metal layer 14. Same as previous example). The bump electrode 21 made of Au and the Sn film 23 are formed on the second semiconductor chip 2 as described above.
And the Au film 15 on the electrode terminals 12a are fused. In this example, the Sn coating 2 is formed on the bump electrode 21.
3 are formed. By forming the Sn film on the bump electrode 21 or the Au film 15 in this manner,
The fusion temperature with the bump can be reduced. In addition, the electrode terminals 12 connected between the first semiconductor chip 1 and the second semiconductor chip 2 (not shown) also have barrier layers 14 and A
A u film 15 is formed, and is fused with a bump electrode 21 provided on the second semiconductor chip 2 side via a Sn film or the like.

【００２８】また、図６に示される例は、両方にバンプ
電極がなく、配線同士のみで接続する例である。すなわ
ち、第１半導体チップ１の配線９ａと第２半導体チップ
２の配線９ｂとがその一部の表面にＳｎ被膜が形成さ
れ、他の部分には、たとえばポリイミド、ＳｉＯ2など
の絶縁膜３１が設けられることにより、Ｓｎ被膜の設け
られた部分のみで接合部３２が形成され、接続すること
ができる。この構造では、配線のＡｕ層がバンプのよう
に厚くなく、薄くなるため、接合後にＳｎが拡散しない
Ａｕ層のみの部分ができない可能性が大きいが、わざわ
ざバンプ電極を形成しなくてもよいため、工数低減を図
れると共に、絶縁層を介して接合されるため、接合部の
みに力がかかるという問題もなくなる。The example shown in FIG. 6 is an example in which both have no bump electrodes and are connected only by wiring. That is, the Sn film is formed on a part of the surface of the wiring 9a of the first semiconductor chip 1 and the wiring 9b of the second semiconductor chip 2, and the insulating film 31 such as polyimide or SiO 2 is formed on the other part. With the provision, the bonding portion 32 is formed only at the portion where the Sn coating is provided, and the connection can be made. In this structure, the Au layer of the wiring is not thick and thin like a bump, so that there is a high possibility that only the Au layer where Sn does not diffuse after bonding will not be formed, but it is not necessary to form the bump electrode. In addition, since the number of steps can be reduced, and the bonding is performed via the insulating layer, the problem that a force is applied only to the bonding portion is eliminated.

【００２９】前述のように、第１半導体チップ１と第２
半導体チップ２との間隙部には、絶縁性樹脂が充填され
ることが好ましい。すなわち、図７に示されるように、
第１半導体チップ１と第２半導体チップ２とを接合した
後に、その間隙部にポリイミドなどからなる絶縁性樹脂
を滴下して硬化させることにより、アンダーフィル（絶
縁性樹脂層）７を形成する。このようなアンダーフィル
７が形成されることにより、面全体で両チップが接触す
るため、パンプ電極の下側の半導体層に形成される素子
に損傷を来すという問題がなくなる。すなわち、半導体
チップ周囲がモールド樹脂によりパッケージングされる
際に、半導体チップ間の隙間にはモールド樹脂が侵入し
難い。そのため、隙間が生じていると樹脂パッケージ８
により両半導体チップが押し付けられ、バンプ電極部分
のみでその圧力を吸収する必要があるため、前述のよう
な問題が生じるが、アンダーフィル７が設けられること
により、そのような問題を引き起こすことがなくなる。As described above, the first semiconductor chip 1 and the second semiconductor chip 1
It is preferable that the gap between the semiconductor chip 2 and the semiconductor chip 2 is filled with an insulating resin. That is, as shown in FIG.
After the first semiconductor chip 1 and the second semiconductor chip 2 are joined, an underfill (insulating resin layer) 7 is formed by dropping and curing an insulating resin made of polyimide or the like in the gap. By forming such an underfill 7, the two chips are in contact with each other over the entire surface, so that the problem of damaging elements formed in the semiconductor layer below the pump electrode is eliminated. That is, when the periphery of the semiconductor chip is packaged with the mold resin, the mold resin does not easily enter the gap between the semiconductor chips. Therefore, if there is a gap, the resin package 8
As a result, both semiconductor chips are pressed together, and it is necessary to absorb the pressure only in the bump electrode portion. Therefore, the above-described problem occurs. However, the provision of the underfill 7 does not cause such a problem. .

【００３０】この場合、ポリイミド（弾性率４.５ＧＰ
ａ）を用いることがＡｕの弾性率と近いため好ましい。
アンダーフィル７の弾性率がバンプ電極１１、２１と近
いと、バンプ電極を融着してから温度が下がった場合で
も、バンプ電極にかかる圧縮力と半導体チップの他の部
分にかかる圧縮力とが均等になるため、力が分散してバ
ンプ電極と共に面として第２半導体チップ２を支持する
ことができ、バンプ電極部分のみに特別な力がかかるこ
とがなくなる。In this case, polyimide (elastic modulus 4.5 GP)
It is preferable to use a) because it is close to the elastic modulus of Au.
If the elastic modulus of the underfill 7 is close to that of the bump electrodes 11 and 21, the compressive force applied to the bump electrodes and the compressive force applied to other parts of the semiconductor chip will be reduced even when the temperature is lowered after fusing the bump electrodes. Because of the uniformity, the force is dispersed and the second semiconductor chip 2 can be supported as a surface together with the bump electrodes, so that no special force is applied only to the bump electrode portions.

【００３１】さらに、アンダーフィル７として使用する
樹脂は、熱収縮率（熱膨張率）が４％以下のものを使用
することが好ましい。熱収縮率が大きいと、硬化時に３
００℃程度に上げた温度が室温に下がったときに、バン
プ電極であるＡｕの熱収縮率より大きくなり、バンプ電
極部分のみに圧縮力として働き、その下の半導体層への
ダメージが大きくなるからである。Further, the resin used as the underfill 7 preferably has a heat shrinkage (coefficient of thermal expansion) of 4% or less. If the heat shrinkage is large, 3
When the temperature raised to about 00 ° C. drops to room temperature, the heat shrinkage of Au, which is a bump electrode, becomes larger than that of Au, which acts as a compressive force only on the bump electrode portion, and the damage to the underlying semiconductor layer increases. It is.

【００３２】また、図１に示される例では、電極パッド
１２ａ表面と絶縁膜１７表面とで段差があり、その上に
設けられる配線９も平坦にならないため、接合を行いに
くいという問題がある。これを解消するため、図８に示
されるように、絶縁膜１７上に、たとえばポリイミドな
どからなる絶縁膜３３を形成してから、配線９を形成す
ることにより平坦な配線９となり、接合しやすくなると
いうメリットがある。Also, in the example shown in FIG. 1, there is a step between the surface of the electrode pad 12a and the surface of the insulating film 17, and the wiring 9 provided thereon is not flat, so that there is a problem that it is difficult to perform bonding. In order to solve this, as shown in FIG. 8, an insulating film 33 made of, for example, polyimide is formed on the insulating film 17, and then the wiring 9 is formed to form a flat wiring 9, which facilitates bonding. There is a merit of becoming.

【００３３】上述の各例は、子チップである第２半導体
チップ同士を配線で接続する例であったが、第２半導体
チップに直接外部から信号を伝達したい場合もある。そ
のような場合でも、従来は、親チップである第１半導体
チップにその接続用配線を絶縁膜内、または半導体層中
に形成しておき、その配線端部の電極端子に第２半導体
チップの電極端子を接続しなければならなかった。この
ような問題を解決する実施形態が図９に示されている。
すなわち、第１半導体チップ１および第２半導体チップ
２の接続は図１に示される例と同様であるが、第１半導
体チップ１の外部接続用電極パッド１３ａに接続して、
絶縁膜１７の最表面に図１に示される配線９と同様の配
線９ｃが形成され、第２半導体チップ２ｃが接続される
ことにより、電極パッド１３ａに接続される外部リード
から直接第２半導体チップ２ｃに信号を伝達することが
できる。なお、６は外部リードと接続するワイヤであ
り、この配線９ｃおよび電極パッド１３ａは、図４の平
面説明図に同じ符号で示されている部分と対応する。In each of the above examples, the second semiconductor chips, which are the child chips, are connected to each other by wiring. However, there are cases where it is desired to transmit a signal from the outside directly to the second semiconductor chip. Even in such a case, conventionally, the connection wiring is formed in the first semiconductor chip, which is the parent chip, in the insulating film or in the semiconductor layer, and the electrode terminal at the end of the wiring is connected to the second semiconductor chip. The electrode terminals had to be connected. An embodiment for solving such a problem is shown in FIG.
That is, the connection between the first semiconductor chip 1 and the second semiconductor chip 2 is the same as that of the example shown in FIG. 1, but the connection to the external connection electrode pad 13a of the first semiconductor chip 1 is performed.
The wiring 9c similar to the wiring 9 shown in FIG. 1 is formed on the outermost surface of the insulating film 17, and the second semiconductor chip 2c is connected, so that the second semiconductor chip is directly connected to the external lead connected to the electrode pad 13a. 2c can be transmitted. Reference numeral 6 denotes a wire connected to an external lead, and the wiring 9c and the electrode pad 13a correspond to the portions indicated by the same reference numerals in the plan view of FIG.

【００３４】なお、このワイヤ６をボンディングする電
極パッド１３ａにも、図９に示されるように、配線９ｃ
を連続して形成し、Ａｕ層およびＳｎ被膜を形成してお
くことにより、ワイヤボンディングの際に、超音波など
で表面を擦りながらボンディングしなくても、容易にワ
イヤボンディングすることができる。As shown in FIG. 9, the electrode pad 13a for bonding the wire 6 also has a wiring 9c.
Are formed continuously, and the Au layer and the Sn film are formed in advance, so that wire bonding can be easily performed without bonding while rubbing the surface with ultrasonic waves or the like at the time of wire bonding.

【００３５】この構造にすることにより、親チップであ
る第１半導体チップの設計変更をすることなく、子チッ
プである第２半導体チップの変更により、直接第２半導
体チップに信号を外部から伝達する必要のある場合で
も、第１半導体チップの外表面に配線を形成することに
より、直接信号を伝達できるようになる。なお、この配
線９ｃも、前述の図１に示される配線９と同様に、バン
プ形成の際に同時に形成することができる。According to this structure, a signal is directly transmitted from the outside to the second semiconductor chip by changing the second semiconductor chip as the child chip without changing the design of the first semiconductor chip as the parent chip. Even if necessary, a signal can be directly transmitted by forming a wiring on the outer surface of the first semiconductor chip. Note that this wiring 9c can be formed simultaneously with the formation of the bump, similarly to the wiring 9 shown in FIG.

【００３６】このワイヤボンディングをする外部接続用
電極パッド１３ａの表面にＡｕ層とＳｎ被膜とを設ける
方法は、ＣＯＣタイプの半導体装置に限らず、また、絶
縁膜最表面に配線を形成する半導体装置に限らず、通常
の半導体装置に適用することができる。すなわち、図１
０に示されるように、ＣＯＣタイプでなくても、半導体
装置では必ず外部リードとＡｕ線などで接続するため、
ワイヤボンディングされる電極パッドを有しているが、
このワイヤボンディングをする場合、超音波で擦りつけ
ながら加熱して行っている。そのため、半導体層にも圧
力がかかり、外部接続用電極パッド１３ａの下の半導体
層にはトランジスタなどの素子を形成することはでき
ず、半導体チップの縮小化に限界がある。しかし、この
電極パッド１３ａ上にもＡｕ層１９ａを０.５〜１μｍ
程度、Ｓｎ被膜１９ｂを０.２〜０.４μｍ程度づつ設け
ておくことにより、前述のバンプ電極の接続と同様に、
ワイヤボンディング時の２５０〜３５０℃への加熱によ
りＡｕ-Ｓｎ合金層が形成され、超音波で擦ることな
く、容易にボンディングすることができる。なお、図１
０において、１７ａは絶縁膜、１４は前述と同様のＴｉ
Ｗなどからなるバリアメタル層である。The method of providing the Au layer and the Sn film on the surface of the external connection electrode pad 13a for performing the wire bonding is not limited to the COC type semiconductor device, and the semiconductor device in which the wiring is formed on the outermost surface of the insulating film. The present invention is not limited to this, and can be applied to ordinary semiconductor devices. That is, FIG.
As shown in FIG. 0, even if the semiconductor device is not of the COC type, the semiconductor device is always connected to an external lead by an Au wire or the like.
It has electrode pads that are wire bonded,
When performing this wire bonding, heating is performed while rubbing with ultrasonic waves. For this reason, pressure is also applied to the semiconductor layer, and an element such as a transistor cannot be formed in the semiconductor layer below the external connection electrode pad 13a. However, the Au layer 19a is also formed on the electrode pad 13a by 0.5 to 1 μm.
By providing the Sn coating 19b by about 0.2 to 0.4 μm at a time, as in the connection of the bump electrodes described above,
An Au—Sn alloy layer is formed by heating to 250 to 350 ° C. during wire bonding, and bonding can be easily performed without rubbing with ultrasonic waves. FIG.
At 0, 17a is an insulating film, and 14 is Ti
This is a barrier metal layer made of W or the like.

【００３７】この構造にすることにより、電極パッド１
３ａ下の半導体層にトランジスタなどの回路素子２０を
形成しても、破損させたり、特性変動を来すことはな
い。その結果、ワイヤボンディング工程が容易になると
共に、接着の信頼性が向上すると共に、その電極パッド
の下にも素子形成をすることができるため、集積度の向
上を図ることができる。With this structure, the electrode pad 1
Even if a circuit element 20 such as a transistor is formed in the semiconductor layer below 3a, it will not be damaged or change in characteristics. As a result, the wire bonding process is facilitated, the bonding reliability is improved, and the element can be formed under the electrode pad, so that the degree of integration can be improved.

【００３８】以上の各例では、第１半導体チップ１の電
極端子にバリア層とＡｕ膜を設けたが、Ａｕ膜には限定
されず、第２半導体チップ２に設けられるバンプ電極と
融着しやすいバンプと接合し得る材料であればよい。In each of the above examples, the barrier layer and the Au film are provided on the electrode terminals of the first semiconductor chip 1. However, the present invention is not limited to the Au film, and the electrode terminals are fused to the bump electrodes provided on the second semiconductor chip 2. Any material can be used as long as it can be bonded to an easy bump.

【００３９】[0039]

【発明の効果】以上説明したように、本発明によれば、
第１半導体チップ上に２個以上の第２半導体チップをマ
ウントするＣＯＣタイプの半導体装置で、複数個の第２
半導体チップ間で接続する必要がある場合でも、第１半
導体チップのパシベーション膜の最表面に配線を形成す
ることにより接続しているため、第２半導体チップを変
更することに伴う第２半導体チップ間同士の配線仕様が
異なっても、第１半導体チップの内部設計などを変更す
ることなく、簡単に組み立てることができる。その結
果、第１半導体チップの汎用性が向上し、種々のタイプ
の半導体装置に用いることができる。As described above, according to the present invention,
A COC type semiconductor device in which two or more second semiconductor chips are mounted on a first semiconductor chip.
Even when it is necessary to connect between the semiconductor chips, the connection is made by forming a wiring on the outermost surface of the passivation film of the first semiconductor chip. Even if the wiring specifications are different from each other, the first semiconductor chip can be easily assembled without changing the internal design or the like. As a result, the versatility of the first semiconductor chip is improved, and the first semiconductor chip can be used for various types of semiconductor devices.

【００４０】また、第２半導体チップ間の接続のみなら
ず、外部リードとの接続用電極パッドと第２半導体チッ
プを接続するための電極端子との間にも、絶縁膜の最表
面に配線を形成することにより、第２の半導体チップに
直接外部から信号を伝達する場合でも、第１半導体チッ
プをそれ専用に作製しなくても、簡単に外部から信号を
伝送することができる。In addition to the connection between the second semiconductor chips, a wiring is formed on the outermost surface of the insulating film not only between the electrode pad for connection with the external lead and the electrode terminal for connecting the second semiconductor chip. By forming, the signal can be easily transmitted from the outside even when the signal is directly transmitted from the outside to the second semiconductor chip, without the first semiconductor chip being manufactured for exclusive use.

【００４１】さらに、接続部にＡｕ層とＳｎ層またはＡ
ｕ-Ｓｎ合金層を設けて行うことにより、Ａｕ-Ｓｎ共晶
合金層が低温で形成されるため、接続の際に、超音波な
どをかけたり、高温にしなくてもよいため、電極パッド
の直ぐ下の半導体層にも素子形成をすることができ、集
積密度を向上させることができる。Further, an Au layer and a Sn layer or A
By providing the u-Sn alloy layer, the Au-Sn eutectic alloy layer is formed at a low temperature, so that it is not necessary to apply ultrasonic waves or the like at the time of connection, and it is not necessary to raise the temperature. An element can be formed also in the semiconductor layer immediately below, and the integration density can be improved.

【００４２】また、ワイヤボンディングをするための電
極パッドにもＡｕ層とＳｎ層またはＡｕ-Ｓｎ合金層を
設けることにより、ワイヤボンディング時に超音波など
により圧力をかけなくても容易にワイヤボンディングを
することができる。その結果、電極パッドの下まで素子
を形成することができ、半導体素子の集積度を向上させ
ることができる。Also, by providing an Au layer and a Sn layer or an Au—Sn alloy layer on the electrode pad for wire bonding, wire bonding can be easily performed without applying pressure by ultrasonic waves or the like during wire bonding. be able to. As a result, the element can be formed below the electrode pad, and the degree of integration of the semiconductor element can be improved.

【図面の簡単な説明】[Brief description of the drawings]

【図１】本発明による半導体装置の一実施形態を示す断
面説明図および配線部の拡大説明図である。FIG. 1 is an explanatory cross-sectional view and an enlarged explanatory view of a wiring portion showing an embodiment of a semiconductor device according to the present invention.

【図２】バンプ電極の接合部をＡｕ-Ｓｎ合金層で形成
した場合の説明図である。FIG. 2 is an explanatory diagram in a case where a bonding portion of a bump electrode is formed of an Au—Sn alloy layer.

【図３】図１のバンプ電極にＳｎ被膜を一方のバンプ電
極の全面に設ける場合の説明図である。FIG. 3 is a diagram illustrating a case where an Sn film is provided on the entire surface of one bump electrode on the bump electrode of FIG. 1;

【図４】本発明による半導体装置の第１半導体チップの
平面説明図である。FIG. 4 is an explanatory plan view of a first semiconductor chip of the semiconductor device according to the present invention;

【図５】本発明による半導体装置の他の実施形態を示す
配線部の拡大説明図である。FIG. 5 is an enlarged explanatory view of a wiring portion showing another embodiment of the semiconductor device according to the present invention.

【図６】第１半導体チップと第２半導体チップとの接合
部にバンプを形成しないで接合する例の説明図である。FIG. 6 is an explanatory diagram of an example in which a first semiconductor chip and a second semiconductor chip are joined without forming a bump at the joint.

【図７】第１半導体チップと第２半導体チップとの隙間
に絶縁性樹脂を充填した例の説明図である。FIG. 7 is an explanatory diagram of an example in which a gap between a first semiconductor chip and a second semiconductor chip is filled with an insulating resin.

【図８】図１に示される例の変形例を示す説明図であ
る。FIG. 8 is an explanatory diagram showing a modification of the example shown in FIG. 1;

【図９】本発明による半導体装置の他の実施形態を説明
する図である。FIG. 9 is a diagram illustrating another embodiment of the semiconductor device according to the present invention.

【図１０】ワイヤボンディング用電極パッドにＡｕ層と
Ｓｎ層とを設けてワイヤボンディングする例の説明図で
ある。FIG. 10 is an explanatory diagram of an example in which an Au layer and a Sn layer are provided on a wire bonding electrode pad to perform wire bonding.

【図１１】従来のＣＯＣタイプで２個のチップを１個の
チップにマウントした例のチップ間の接続部を説明する
図である。FIG. 11 is a diagram illustrating a connection part between chips in an example in which two chips of the conventional COC type are mounted on one chip.

【符号の説明】[Explanation of symbols]

１ 第１半導体チップ ２(2a,2b) 第２半導体チップ ９ 配線 １１ バンプ電極 １２ 電極端子 １７ パシベーション膜 ２１ バンプ電極 ２２ 電極端子 DESCRIPTION OF SYMBOLS 1 1st semiconductor chip 2 (2a, 2b) 2nd semiconductor chip 9 Wiring 11 Bump electrode 12 Electrode terminal 17 Passivation film 21 Bump electrode 22 Electrode terminal

───────────────────────────────────────────────────── フロントページの続き (72)発明者 江南 俊夫 京都市右京区西院溝崎町21番地 ローム株 式会社内 Ｆターム(参考） 5F044 EE04 EE06 EE11 EE13 EE20 EE21  ────────────────────────────────────────────────── ─── Continuing on the front page (72) Inventor Toshio Konan 21 Ryozaki-cho, Saiin, Ukyo-ku, Kyoto F-term within ROHM Co., Ltd. (reference) 5F044 EE04 EE06 EE11 EE13 EE20 EE21

Claims (1)

【特許請求の範囲】[Claims] 【請求項１】 半導体層に回路素子が形成された半導体
基板と、該半導体基板の表面に絶縁膜を介して、または
半導体基板と接触して設けられるワイヤボンディング用
の電極パッドと、該電極パッドに外部リードと接続する
ためボンディングされるワイヤとを有する半導体装置で
あって、前記電極パッド表面にＡｕ層とＳｎ層とが設け
られ、前記ワイヤと電極パッドとの接続部がＡｕ-Ｓｎ
合金層を介して接続されてなる半導体装置。1. A semiconductor substrate having a circuit element formed on a semiconductor layer, an electrode pad for wire bonding provided on a surface of the semiconductor substrate via an insulating film or in contact with the semiconductor substrate, and the electrode pad A wire bonded to an external lead for connection to an external lead, wherein an Au layer and a Sn layer are provided on a surface of the electrode pad, and a connection portion between the wire and the electrode pad is formed of Au-Sn.
A semiconductor device connected through an alloy layer.
JP2002168959A 2000-09-12 2002-06-10 Semiconductor device Expired - Lifetime JP4754763B2 (en)

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WO2010030474A1 (en) * 2008-09-11 2010-03-18 Micron Technology, Inc. Interconnect structures for stacked dies, including penetrating structures for through-silicon vias

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JPS6035552A (en) * 1983-08-08 1985-02-23 Hitachi Ltd Semiconductor device
JPH09326465A (en) * 1996-06-06 1997-12-16 Matsushita Electric Ind Co Ltd Semiconductor device and its manufacturing method
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JPS57106140A (en) * 1980-12-24 1982-07-01 Hitachi Ltd Semiconductor device and manufacture thereof
JPS6035552A (en) * 1983-08-08 1985-02-23 Hitachi Ltd Semiconductor device
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Publication number Priority date Publication date Assignee Title
WO2010030474A1 (en) * 2008-09-11 2010-03-18 Micron Technology, Inc. Interconnect structures for stacked dies, including penetrating structures for through-silicon vias
US7872332B2 (en) 2008-09-11 2011-01-18 Micron Technology, Inc. Interconnect structures for stacked dies, including penetrating structures for through-silicon vias, and associated systems and methods
US8435836B2 (en) 2008-09-11 2013-05-07 Micron Technology, Inc. Interconnect structures for stacked dies, including penetrating structures for through-silicon vias, and associated systems and methods
US8680654B2 (en) 2008-09-11 2014-03-25 Micron Technology, Inc. Interconnect structures for stacked dies, including penetrating structures for through-silicon vias, and associated systems and methods
US9165888B2 (en) 2008-09-11 2015-10-20 Micron Technology, Inc. Interconnect structures for stacked dies, including penetrating structures for through-silicon vias, and associated systems and methods

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